diff --git a/1ano/2semestre/lsd/pratica01/part1/GateDemo.qpf b/1ano/2semestre/lsd/pratica01/part1/GateDemo.qpf
deleted file mode 100644
index 0145ea3..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/GateDemo.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 14:43:19 February 18, 2023
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "20.1"
-DATE = "14:43:19 February 18, 2023"
-
-# Revisions
-
-PROJECT_REVISION = "GateDemo"
diff --git a/1ano/2semestre/lsd/pratica01/part1/GateDemo.qsf b/1ano/2semestre/lsd/pratica01/part1/GateDemo.qsf
deleted file mode 100644
index c4a4293..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/GateDemo.qsf
+++ /dev/null
@@ -1,582 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 14:43:19 February 18, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# GateDemo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY GateDemo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:43:19 FEBRUARY 18, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name BDF_FILE GateDemo.bdf
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VECTOR_WAVEFORM_FILE GateDemo.vwf
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part1/GateDemo.qsf.bak b/1ano/2semestre/lsd/pratica01/part1/GateDemo.qsf.bak
deleted file mode 100644
index c4a4293..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/GateDemo.qsf.bak
+++ /dev/null
@@ -1,582 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 14:43:19 February 18, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# GateDemo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY GateDemo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:43:19 FEBRUARY 18, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name BDF_FILE GateDemo.bdf
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VECTOR_WAVEFORM_FILE GateDemo.vwf
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part1/GateDemo.qws b/1ano/2semestre/lsd/pratica01/part1/GateDemo.qws
deleted file mode 100644
index 242003f..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.(0).cnf.cdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.(0).cnf.cdb
deleted file mode 100644
index 191147e..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.(0).cnf.hdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.(0).cnf.hdb
deleted file mode 100644
index df8721c..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.asm.qmsg b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.asm.qmsg
deleted file mode 100644
index 75053a3..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.asm.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677672096545 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677672096546 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 1 12:01:36 2023 " "Processing started: Wed Mar 1 12:01:36 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677672096546 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1677672096546 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1677672096546 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1677672096703 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1677672098451 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1677672098548 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677672098774 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 1 12:01:38 2023 " "Processing ended: Wed Mar 1 12:01:38 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677672098774 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677672098774 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677672098774 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1677672098774 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.asm.rdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.asm.rdb
deleted file mode 100644
index b1975fd..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.asm_labs.ddb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.asm_labs.ddb
deleted file mode 100644
index 26951bc..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.asm_labs.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cbx.xml b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cbx.xml
deleted file mode 100644
index 139c92d..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.bpm b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.bpm
deleted file mode 100644
index 3c438ac..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.cdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.cdb
deleted file mode 100644
index f542c7b..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.hdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.hdb
deleted file mode 100644
index 9d09c8e..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.idb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.idb
deleted file mode 100644
index d4787d1..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.idb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.logdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.logdb
deleted file mode 100644
index 20a0aac..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.logdb
+++ /dev/null
@@ -1,45 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;3;3;0;0;3;3;0;0;0;0;0;0;1;0;0;0;2;1;0;2;0;0;1;0;3;3;3;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,3;0;0;3;3;0;0;3;3;3;3;3;3;2;3;3;3;1;2;3;1;3;3;2;3;0;0;0;3;3,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.rdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp.rdb
deleted file mode 100644
index 840925b..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp_merge.kpt b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cmp_merge.kpt
deleted file mode 100644
index d8b24f8..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index d9c61ce..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
deleted file mode 100644
index 218eca7..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
deleted file mode 100644
index 201d97d..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.db_info b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.db_info
deleted file mode 100644
index d9f9c6f..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Wed Mar 1 12:01:11 2023
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.eda.qmsg b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.eda.qmsg
deleted file mode 100644
index 438b5bf..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677672101088 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677672101088 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 1 12:01:41 2023 " "Processing started: Wed Mar 1 12:01:41 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677672101088 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1677672101088 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1677672101088 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1677672101272 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "GateDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/modelsim/ simulation " "Generated file GateDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1677672101305 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677672101324 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 1 12:01:41 2023 " "Processing ended: Wed Mar 1 12:01:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677672101324 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677672101324 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677672101324 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1677672101324 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.fit.qmsg b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.fit.qmsg
deleted file mode 100644
index 67cd0fd..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.fit.qmsg
+++ /dev/null
@@ -1,48 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1677672088193 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1677672088193 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "GateDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"GateDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1677672088195 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1677672088264 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1677672088264 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1677672088572 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1677672088581 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677672088733 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677672088733 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677672088733 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677672088733 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677672088733 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677672088733 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677672088733 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677672088733 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677672088733 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1677672088733 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/" { { 0 { 0 ""} 0 570 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677672088738 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/" { { 0 { 0 ""} 0 572 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677672088738 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/" { { 0 { 0 ""} 0 574 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677672088738 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/" { { 0 { 0 ""} 0 576 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677672088738 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/" { { 0 { 0 ""} 0 578 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677672088738 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1677672088738 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1677672088747 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GateDemo.sdc " "Synopsys Design Constraints File file not found: 'GateDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1677672089465 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1677672089465 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1677672089465 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1677672089466 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1677672089467 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1677672089467 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1677672089467 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1677672089471 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1677672089471 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1677672089471 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1677672089471 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1677672089472 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1677672089472 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1677672089472 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1677672089472 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1677672089472 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1677672089472 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1677672089472 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677672089486 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1677672089486 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677672089496 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1677672089502 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1677672091318 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677672091410 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1677672091445 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1677672091629 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677672091629 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1677672091795 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y24 X115_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y24 to location X115_Y36" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y24 to location X115_Y36"} { { 12 { 0 ""} 104 24 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1677672094085 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1677672094085 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1677672094213 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1677672094213 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1677672094213 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677672094214 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1677672094294 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1677672094299 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1677672094499 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1677672094499 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1677672094664 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677672094921 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1677672095101 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1677672095148 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 523 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 523 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1148 " "Peak virtual memory: 1148 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677672095309 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 1 12:01:35 2023 " "Processing ended: Wed Mar 1 12:01:35 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677672095309 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677672095309 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677672095309 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1677672095309 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.hier_info b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.hier_info
deleted file mode 100644
index 78fb306..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.hier_info
+++ /dev/null
@@ -1,6 +0,0 @@
-|GateDemo
-LEDR[0] <= inst.DB_MAX_OUTPUT_PORT_TYPE
-SW[0] => inst.IN0
-SW[1] => inst.IN1
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.hif b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.hif
deleted file mode 100644
index a74d112..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.lpc.html b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.lpc.html
deleted file mode 100644
index fbc5ab5..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.lpc.html
+++ /dev/null
@@ -1,18 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.lpc.rdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.lpc.rdb
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index b1e0351..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.lpc.txt b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.lpc.txt
deleted file mode 100644
index a463804..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.lpc.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.ammdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.ammdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.bpm b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.bpm
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.cdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.cdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.hdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.kpt b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.kpt
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.logdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.qmsg b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.qmsg
deleted file mode 100644
index 70a6bd7..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.qmsg
+++ /dev/null
@@ -1,11 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677672079639 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677672079639 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 1 12:01:19 2023 " "Processing started: Wed Mar 1 12:01:19 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677672079639 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677672079639 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GateDemo -c GateDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677672079639 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1677672079816 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1677672079816 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GateDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file GateDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 GateDemo " "Found entity 1: GateDemo" { } { { "GateDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677672086056 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677672086056 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "GateDemo " "Elaborating entity \"GateDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1677672086110 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1677672086590 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1677672087002 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1677672087002 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "4 " "Implemented 4 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1677672087178 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1677672087178 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1677672087178 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1677672087178 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "407 " "Peak virtual memory: 407 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677672087185 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 1 12:01:27 2023 " "Processing ended: Wed Mar 1 12:01:27 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677672087185 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677672087185 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:19 " "Total CPU time (on all processors): 00:00:19" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677672087185 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1677672087185 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.rdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map.rdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map_bb.cdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map_bb.cdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map_bb.hdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map_bb.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map_bb.logdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.pplq.rdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.pplq.rdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.pre_map.hdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.root_partition.map.reg_db.cdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.routing.rdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.rtlv.hdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.rtlv_sg.cdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.rtlv_sg.cdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.rtlv_sg_swap.cdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.rtlv_sg_swap.cdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.sld_design_entry.sci b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.smart_action.txt b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.smart_action.txt
deleted file mode 100644
index c8e8a13..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.sta.qmsg b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.sta.qmsg
deleted file mode 100644
index a2505f8..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677672099335 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677672099335 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 1 12:01:39 2023 " "Processing started: Wed Mar 1 12:01:39 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677672099335 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1677672099335 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GateDemo -c GateDemo " "Command: quartus_sta GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1677672099335 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1677672099360 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1677672099433 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1677672099433 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677672099486 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677672099486 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GateDemo.sdc " "Synopsys Design Constraints File file not found: 'GateDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1677672099831 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1677672099831 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1677672099832 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1677672099832 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1677672099832 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1677672099832 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1677672099832 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1677672099836 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1677672099836 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672099838 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672099841 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672099841 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672099842 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672099842 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672099843 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1677672099845 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1677672099860 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1677672100077 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1677672100090 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1677672100090 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1677672100090 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1677672100090 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672100091 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672100092 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672100093 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672100094 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672100094 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672100094 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1677672100096 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1677672100153 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1677672100153 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1677672100153 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1677672100153 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672100154 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672100154 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672100155 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672100156 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672100156 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677672100400 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677672100400 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "535 " "Peak virtual memory: 535 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677672100413 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 1 12:01:40 2023 " "Processing ended: Wed Mar 1 12:01:40 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677672100413 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677672100413 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677672100413 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1677672100413 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.sta.rdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.sta.rdb
deleted file mode 100644
index 0ee57ea..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.sta_cmp.7_slow_1200mv_85c.tdb
deleted file mode 100644
index 6cc8ccf..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.tis_db_list.ddb
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index 73e5ec9..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index cc44864..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index 6d4c57f..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index a7b7427..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.tmw_info b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.tmw_info
deleted file mode 100644
index 7feb755..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.tmw_info
+++ /dev/null
@@ -1,7 +0,0 @@
-start_full_compilation:s:00:00:23
-start_analysis_synthesis:s:00:00:09-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:08-start_full_compilation
-start_assembler:s:00:00:03-start_full_compilation
-start_timing_analyzer:s:00:00:02-start_full_compilation
-start_eda_netlist_writer:s:00:00:01-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.vpr.ammdb b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.vpr.ammdb
deleted file mode 100644
index cf1007c..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo_partition_pins.json b/1ano/2semestre/lsd/pratica01/part1/db/GateDemo_partition_pins.json
deleted file mode 100644
index d1f8e6a..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/GateDemo_partition_pins.json
+++ /dev/null
@@ -1,21 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "LEDR[0]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part1/db/prev_cmp_GateDemo.qmsg b/1ano/2semestre/lsd/pratica01/part1/db/prev_cmp_GateDemo.qmsg
deleted file mode 100644
index 58e6d2f..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/db/prev_cmp_GateDemo.qmsg
+++ /dev/null
@@ -1,129 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677067867223 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677067867224 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 22 12:11:07 2023 " "Processing started: Wed Feb 22 12:11:07 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677067867224 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677067867224 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GateDemo -c GateDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677067867224 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1677067867364 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1677067867364 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GateDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file GateDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 GateDemo " "Found entity 1: GateDemo" { } { { "GateDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677067872269 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677067872269 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "GateDemo " "Elaborating entity \"GateDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1677067872298 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1677067872660 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1677067873020 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1677067873020 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "4 " "Implemented 4 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1677067873036 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1677067873036 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1677067873036 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1677067873036 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "404 " "Peak virtual memory: 404 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677067873039 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 22 12:11:13 2023 " "Processing ended: Wed Feb 22 12:11:13 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677067873039 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677067873039 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677067873039 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1677067873039 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1677067873937 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677067873938 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 22 12:11:13 2023 " "Processing started: Wed Feb 22 12:11:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677067873938 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1677067873938 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1677067873938 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1677067873964 ""}
-{ "Info" "0" "" "Project = GateDemo" { } { } 0 0 "Project = GateDemo" 0 0 "Fitter" 0 0 1677067873965 ""}
-{ "Info" "0" "" "Revision = GateDemo" { } { } 0 0 "Revision = GateDemo" 0 0 "Fitter" 0 0 1677067873965 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1677067874007 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1677067874007 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "GateDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"GateDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1677067874010 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1677067874062 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1677067874062 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1677067874349 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1677067874359 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677067874550 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677067874550 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677067874550 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677067874550 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677067874550 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677067874550 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677067874550 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677067874550 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677067874550 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1677067874550 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/" { { 0 { 0 ""} 0 570 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677067874556 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/" { { 0 { 0 ""} 0 572 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677067874556 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/" { { 0 { 0 ""} 0 574 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677067874556 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/" { { 0 { 0 ""} 0 576 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677067874556 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/" { { 0 { 0 ""} 0 578 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677067874556 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1677067874556 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1677067874565 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GateDemo.sdc " "Synopsys Design Constraints File file not found: 'GateDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1677067875194 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1677067875194 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1677067875194 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1677067875195 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1677067875196 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1677067875196 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1677067875196 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1677067875199 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1677067875199 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1677067875199 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1677067875200 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1677067875200 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1677067875200 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1677067875200 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1677067875200 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1677067875200 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1677067875200 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1677067875200 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677067875212 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1677067875212 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677067875220 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1677067875225 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1677067876658 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677067876737 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1677067876764 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1677067876908 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677067876908 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1677067877031 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y24 X115_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y24 to location X115_Y36" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y24 to location X115_Y36"} { { 12 { 0 ""} 104 24 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1677067878976 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1677067878976 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1677067879085 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1677067879085 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1677067879085 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677067879086 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1677067879154 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1677067879159 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1677067879316 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1677067879316 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1677067879452 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677067879671 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1677067879834 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1677067879873 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 523 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 523 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1148 " "Peak virtual memory: 1148 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677067880006 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 22 12:11:19 2023 " "Processing ended: Wed Feb 22 12:11:19 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677067880006 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677067880006 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677067880006 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1677067880006 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1677067880716 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677067880716 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 22 12:11:20 2023 " "Processing started: Wed Feb 22 12:11:20 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677067880716 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1677067880716 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1677067880716 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1677067880841 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1677067882286 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1677067882356 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677067882547 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 22 12:11:22 2023 " "Processing ended: Wed Feb 22 12:11:22 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677067882547 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677067882547 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677067882547 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1677067882547 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1677067882669 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1677067883057 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677067883058 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 22 12:11:22 2023 " "Processing started: Wed Feb 22 12:11:22 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677067883058 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1677067883058 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GateDemo -c GateDemo " "Command: quartus_sta GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1677067883058 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1677067883079 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1677067883134 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1677067883134 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677067883178 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677067883178 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GateDemo.sdc " "Synopsys Design Constraints File file not found: 'GateDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1677067883469 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1677067883469 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1677067883469 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1677067883469 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1677067883469 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1677067883469 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1677067883470 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1677067883472 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1677067883473 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883473 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883475 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883476 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883476 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883476 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883477 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1677067883478 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1677067883492 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1677067883643 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1677067883653 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1677067883653 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1677067883654 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1677067883654 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883654 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883655 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883655 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883655 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883656 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883656 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1677067883657 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1677067883693 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1677067883693 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1677067883693 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1677067883693 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883694 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883694 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883694 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883695 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677067883695 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677067883893 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677067883893 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "535 " "Peak virtual memory: 535 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677067883901 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 22 12:11:23 2023 " "Processing ended: Wed Feb 22 12:11:23 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677067883901 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677067883901 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677067883901 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1677067883901 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1677067884467 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677067884467 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 22 12:11:24 2023 " "Processing started: Wed Feb 22 12:11:24 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677067884467 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1677067884467 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1677067884467 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1677067884620 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "GateDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/modelsim/ simulation " "Generated file GateDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1677067884647 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677067884656 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 22 12:11:24 2023 " "Processing ended: Wed Feb 22 12:11:24 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677067884656 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677067884656 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677067884656 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1677067884656 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 531 s " "Quartus Prime Full Compilation was successful. 0 errors, 531 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1677067885229 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/README b/1ano/2semestre/lsd/pratica01/part1/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.db_info b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.db_info
deleted file mode 100644
index 8bcd46e..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Sat Feb 18 14:46:48 2023
diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.ammdb
deleted file mode 100644
index d4435e5..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.cdb
deleted file mode 100644
index 811ef2e..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.dfp and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.hdb
deleted file mode 100644
index 29b8e2e..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.rcfdb
deleted file mode 100644
index 74b2766..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.cdb
deleted file mode 100644
index 2f4753a..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.dpi
deleted file mode 100644
index 55346ef..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.cdb
deleted file mode 100644
index 3e9c98d..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.hdb
deleted file mode 100644
index cf1f8d9..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hdb
deleted file mode 100644
index d9a0de1..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.kpt
deleted file mode 100644
index cb2fa34..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.rrp.hdb b/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.rrp.hdb
deleted file mode 100644
index d218e51..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part1/incremental_db/compiled_partitions/GateDemo.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.asm.rpt b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.asm.rpt
deleted file mode 100644
index 64891d9..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for GateDemo
-Wed Mar 1 12:01:38 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: GateDemo.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Wed Mar 1 12:01:38 2023 ;
-; Revision Name ; GateDemo ;
-; Top-level Entity Name ; GateDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+--------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+--------------------------------------------------------------------------------------------+
-; File Name ;
-+--------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.sof ;
-+--------------------------------------------------------------------------------------------+
-
-
-+----------------------------------------+
-; Assembler Device Options: GateDemo.sof ;
-+----------------+-----------------------+
-; Option ; Setting ;
-+----------------+-----------------------+
-; JTAG usercode ; 0x00562D0A ;
-; Checksum ; 0x00562D0A ;
-+----------------+-----------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 1 12:01:36 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 367 megabytes
- Info: Processing ended: Wed Mar 1 12:01:38 2023
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.done b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.done
deleted file mode 100644
index 0d7bb8f..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.done
+++ /dev/null
@@ -1 +0,0 @@
-Wed Mar 1 12:01:41 2023
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.eda.rpt b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.eda.rpt
deleted file mode 100644
index a72b280..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.eda.rpt
+++ /dev/null
@@ -1,94 +0,0 @@
-EDA Netlist Writer report for GateDemo
-Wed Mar 1 12:01:41 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Wed Mar 1 12:01:41 2023 ;
-; Revision Name ; GateDemo ;
-; Top-level Entity Name ; GateDemo ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+---------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+---------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/modelsim/GateDemo.vho ;
-+---------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 1 12:01:41 2023
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file GateDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 612 megabytes
- Info: Processing ended: Wed Mar 1 12:01:41 2023
- Info: Elapsed time: 00:00:00
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.fit.rpt b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.fit.rpt
deleted file mode 100644
index f6b6a18..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.fit.rpt
+++ /dev/null
@@ -1,2501 +0,0 @@
-Fitter report for GateDemo
-Wed Mar 1 12:01:35 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Wed Mar 1 12:01:35 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; GateDemo ;
-; Top-level Entity Name ; GateDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 1 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 1 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 3 / 529 ( < 1 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.1% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; CLOCK_50 ; PIN_Y2 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
-; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
-; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
-; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
-; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
-; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
-; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[0] ; PIN_M23 ; QSF Assignment ;
-; Location ; ; ; KEY[1] ; PIN_M21 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[0] ; PIN_E21 ; QSF Assignment ;
-; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
-; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
-; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[1] ; PIN_F19 ; QSF Assignment ;
-; Location ; ; ; LEDR[2] ; PIN_E19 ; QSF Assignment ;
-; Location ; ; ; LEDR[3] ; PIN_F21 ; QSF Assignment ;
-; Location ; ; ; LEDR[4] ; PIN_F18 ; QSF Assignment ;
-; Location ; ; ; LEDR[5] ; PIN_E18 ; QSF Assignment ;
-; Location ; ; ; LEDR[6] ; PIN_J19 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_H19 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; SW[10] ; PIN_AC24 ; QSF Assignment ;
-; Location ; ; ; SW[11] ; PIN_AB24 ; QSF Assignment ;
-; Location ; ; ; SW[12] ; PIN_AB23 ; QSF Assignment ;
-; Location ; ; ; SW[13] ; PIN_AA24 ; QSF Assignment ;
-; Location ; ; ; SW[14] ; PIN_AA23 ; QSF Assignment ;
-; Location ; ; ; SW[15] ; PIN_AA22 ; QSF Assignment ;
-; Location ; ; ; SW[16] ; PIN_Y24 ; QSF Assignment ;
-; Location ; ; ; SW[17] ; PIN_Y23 ; QSF Assignment ;
-; Location ; ; ; SW[2] ; PIN_AC27 ; QSF Assignment ;
-; Location ; ; ; SW[3] ; PIN_AD27 ; QSF Assignment ;
-; Location ; ; ; SW[4] ; PIN_AB27 ; QSF Assignment ;
-; Location ; ; ; SW[5] ; PIN_AC26 ; QSF Assignment ;
-; Location ; ; ; SW[6] ; PIN_AD26 ; QSF Assignment ;
-; Location ; ; ; SW[7] ; PIN_AB26 ; QSF Assignment ;
-; Location ; ; ; SW[8] ; PIN_AC25 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AB25 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 18 ) ; 0.00 % ( 0 / 18 ) ; 0.00 % ( 0 / 18 ) ;
-; -- Achieved ; 0.00 % ( 0 / 18 ) ; 0.00 % ( 0 / 18 ) ; 0.00 % ( 0 / 18 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 8 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+-----------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-----------------------+
-; Total logic elements ; 1 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 1 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 0 ;
-; -- <=2 input functions ; 1 ;
-; -- Register only ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers* ; 0 / 117,053 ( 0 % ) ;
-; -- Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 1 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 3 / 529 ( < 1 % ) ;
-; -- Clock pins ; 0 / 7 ( 0 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ;
-; Maximum fan-out ; 1 ;
-; Highest non-global fan-out ; 1 ;
-; Total fan-out ; 11 ;
-; Average fan-out ; 0.65 ;
-+---------------------------------------------+-----------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 1 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 1 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 0 ; 0 ;
-; -- 3 input functions ; 0 ; 0 ;
-; -- <=2 input functions ; 1 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 1 ; 0 ;
-; -- arithmetic mode ; 0 ; 0 ;
-; ; ; ;
-; Total registers ; 0 ; 0 ;
-; -- Dedicated logic registers ; 0 / 114480 ( 0 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 1 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 3 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 6 ; 5 ;
-; -- Registered Connections ; 0 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 2 ; 0 ;
-; -- Output Ports ; 1 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+----------------------+--------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+----------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+----------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+----------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 0 / 63 ( 0 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 2 / 65 ( 3 % ) ; 2.5V ; -- ;
-; 6 ; 1 / 58 ( 2 % ) ; 2.5V ; -- ;
-; 7 ; 1 / 72 ( 1 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+----------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA23 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA24 ; 279 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB24 ; 274 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB25 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB26 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB27 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC25 ; 272 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC26 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC27 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD27 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y24 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; LEDR[0] ; Incomplete set of assignments ;
-; SW[1] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+-------------+--------------+
-; |GateDemo ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |GateDemo ; GateDemo ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-----------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+---------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+---------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+---------------------+-------------------+---------+
-; SW[1] ; ; ;
-; - inst ; 0 ; 6 ;
-; SW[0] ; ; ;
-; - inst ; 0 ; 6 ;
-+---------------------+-------------------+---------+
-
-
-+-----------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+-----------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+-----------------------+
-; Block interconnects ; 3 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 4 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 2 / 209,544 ( < 1 % ) ;
-; Direct links ; 0 / 342,891 ( 0 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 0 / 119,088 ( 0 % ) ;
-; R24 interconnects ; 2 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 0 / 289,782 ( 0 % ) ;
-+-----------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 1.00) ; Number of LABs (Total = 1) ;
-+--------------------------------------------+-----------------------------+
-; 1 ; 1 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-+--------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 1.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 1) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 1 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 2.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 3 ; 3 ; 0 ; 0 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 2 ; 1 ; 0 ; 2 ; 0 ; 0 ; 1 ; 0 ; 3 ; 3 ; 3 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 3 ; 0 ; 0 ; 3 ; 3 ; 0 ; 0 ; 3 ; 3 ; 3 ; 3 ; 3 ; 3 ; 2 ; 3 ; 3 ; 3 ; 1 ; 2 ; 3 ; 1 ; 3 ; 3 ; 2 ; 3 ; 0 ; 0 ; 0 ; 3 ; 3 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "GateDemo"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'GateDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y24 to location X115_Y36
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 523 warnings
- Info: Peak virtual memory: 1148 megabytes
- Info: Processing ended: Wed Mar 1 12:01:35 2023
- Info: Elapsed time: 00:00:08
- Info: Total CPU time (on all processors): 00:00:11
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.fit.smsg b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.fit.summary b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.fit.summary
deleted file mode 100644
index 9280014..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Wed Mar 1 12:01:35 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : GateDemo
-Top-level Entity Name : GateDemo
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 1 / 114,480 ( < 1 % )
- Total combinational functions : 1 / 114,480 ( < 1 % )
- Dedicated logic registers : 0 / 114,480 ( 0 % )
-Total registers : 0
-Total pins : 3 / 529 ( < 1 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.flow.rpt b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.flow.rpt
deleted file mode 100644
index e27fc1f..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.flow.rpt
+++ /dev/null
@@ -1,134 +0,0 @@
-Flow report for GateDemo
-Wed Mar 1 12:01:41 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Wed Mar 1 12:01:41 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; GateDemo ;
-; Top-level Entity Name ; GateDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 1 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 1 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 3 / 529 ( < 1 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/01/2023 12:01:19 ;
-; Main task ; Compilation ;
-; Revision Name ; GateDemo ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 198516037997543.167767207905236 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 401 MB ; 00:00:19 ;
-; Fitter ; 00:00:08 ; 1.0 ; 1148 MB ; 00:00:11 ;
-; Assembler ; 00:00:02 ; 1.0 ; 367 MB ; 00:00:02 ;
-; Timing Analyzer ; 00:00:01 ; 1.0 ; 535 MB ; 00:00:01 ;
-; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 612 MB ; 00:00:00 ;
-; Total ; 00:00:18 ; -- ; -- ; 00:00:33 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off GateDemo -c GateDemo
-quartus_fit --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo
-quartus_asm --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo
-quartus_sta GateDemo -c GateDemo
-quartus_eda --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo
-
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.jdi b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.jdi
deleted file mode 100644
index 00227e9..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.map.rpt b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.map.rpt
deleted file mode 100644
index 58fad1e..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.map.rpt
+++ /dev/null
@@ -1,281 +0,0 @@
-Analysis & Synthesis report for GateDemo
-Wed Mar 1 12:01:27 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Post-Synthesis Netlist Statistics for Top Partition
- 10. Elapsed Time Per Partition
- 11. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Wed Mar 1 12:01:27 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; GateDemo ;
-; Top-level Entity Name ; GateDemo ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 1 ;
-; Total combinational functions ; 1 ;
-; Dedicated logic registers ; 0 ;
-; Total registers ; 0 ;
-; Total pins ; 3 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; GateDemo ; GateDemo ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------+---------+
-; GateDemo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.bdf ; ;
-+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------+---------+
-
-
-+-----------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+-------+
-; Resource ; Usage ;
-+---------------------------------------------+-------+
-; Estimated Total logic elements ; 1 ;
-; ; ;
-; Total combinational functions ; 1 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 0 ;
-; -- <=2 input functions ; 1 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers ; 0 ;
-; -- Dedicated logic registers ; 0 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 3 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; inst ;
-; Maximum fan-out ; 1 ;
-; Total fan-out ; 6 ;
-; Average fan-out ; 0.86 ;
-+---------------------------------------------+-------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+
-; |GateDemo ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 3 ; 0 ; |GateDemo ; GateDemo ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 0 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 3 ;
-; cycloneiii_lcell_comb ; 1 ;
-; normal ; 1 ;
-; 2 data inputs ; 1 ;
-; ; ;
-; Max LUT depth ; 1.00 ;
-; Average LUT depth ; 1.00 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 1 12:01:19 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GateDemo -c GateDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file GateDemo.bdf
- Info (12023): Found entity 1: GateDemo
-Info (12127): Elaborating entity "GateDemo" for the top level hierarchy
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 4 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 2 input pins
- Info (21059): Implemented 1 output pins
- Info (21061): Implemented 1 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 407 megabytes
- Info: Processing ended: Wed Mar 1 12:01:27 2023
- Info: Elapsed time: 00:00:08
- Info: Total CPU time (on all processors): 00:00:19
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.map.summary b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.map.summary
deleted file mode 100644
index 2f0de94..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Wed Mar 1 12:01:27 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : GateDemo
-Top-level Entity Name : GateDemo
-Family : Cyclone IV E
-Total logic elements : 1
- Total combinational functions : 1
- Dedicated logic registers : 0
-Total registers : 0
-Total pins : 3
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.pin b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.pin
deleted file mode 100644
index 2e1015e..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "GateDemo" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5 :
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 5 :
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7 :
-VCCIO7 : E20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
-VCCIO7 : E23 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7 :
-GND : F20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
-LEDR[0] : G19 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
-VCCIO7 : H18 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7 :
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6 :
-MSEL2 : M22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-GND+ : Y2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.sld b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.sta.rpt b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.sta.rpt
deleted file mode 100644
index 7555004..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.sta.rpt
+++ /dev/null
@@ -1,431 +0,0 @@
-Timing Analyzer report for GateDemo
-Wed Mar 1 12:01:40 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Unconstrained Input Ports
- 37. Unconstrained Output Ports
- 38. Unconstrained Input Ports
- 39. Unconstrained Output Ports
- 40. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; GateDemo ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.2% ;
-+----------------------------+-------------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 2 ; 2 ;
-; Unconstrained Input Port Paths ; 2 ; 2 ;
-; Unconstrained Output Ports ; 1 ; 1 ;
-; Unconstrained Output Port Paths ; 2 ; 2 ;
-+---------------------------------+-------+------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 1 12:01:39 2023
-Info: Command: quartus_sta GateDemo -c GateDemo
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'GateDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 535 megabytes
- Info: Processing ended: Wed Mar 1 12:01:40 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.sta.summary b/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.sta.summary
deleted file mode 100644
index aa5b327..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/modelsim/GateDemo.sft b/1ano/2semestre/lsd/pratica01/part1/simulation/modelsim/GateDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/modelsim/GateDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/modelsim/GateDemo.vho b/1ano/2semestre/lsd/pratica01/part1/simulation/modelsim/GateDemo.vho
deleted file mode 100644
index cd597d8..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/modelsim/GateDemo.vho
+++ /dev/null
@@ -1,180 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/01/2023 12:01:41"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY GateDemo IS
- PORT (
- LEDR : OUT std_logic_vector(0 DOWNTO 0);
- SW : IN std_logic_vector(1 DOWNTO 0)
- );
-END GateDemo;
-
--- Design Ports Information
--- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF GateDemo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDR : std_logic_vector(0 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(1 DOWNTO 0);
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \inst~combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-LEDR <= ww_LEDR;
-ww_SW <= SW;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X69_Y73_N16
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst~combout\,
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: LCCOMB_X114_Y17_N8
-inst : cycloneive_lcell_comb
--- Equation(s):
--- \inst~combout\ = (\SW[1]~input_o\ & \SW[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010101000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[1]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \inst~combout\);
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/modelsim/GateDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica01/part1/simulation/modelsim/GateDemo_modelsim.xrf
deleted file mode 100644
index 32e1767..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/modelsim/GateDemo_modelsim.xrf
+++ /dev/null
@@ -1,9 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.bdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.vwf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/db/GateDemo.cbx.xml
-design_name = hard_block
-design_name = GateDemo
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, GateDemo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, GateDemo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, GateDemo, 1
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.do b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.do
deleted file mode 100644
index cb366b6..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.do
+++ /dev/null
@@ -1,17 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vcom -work work GateDemo.vho
-vcom -work work GateDemo.vwf.vht
-vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.GateDemo_vhd_vec_tst
-vcd file -direction GateDemo.msim.vcd
-vcd add -internal GateDemo_vhd_vec_tst/*
-vcd add -internal GateDemo_vhd_vec_tst/i1/*
-proc simTimestamp {} {
- echo "Simulation time: $::now ps"
- if { [string equal running [runStatus]] } {
- after 2500 simTimestamp
- }
-}
-after 2500 simTimestamp
-run -all
-quit -f
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.msim.vcd b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.msim.vcd
deleted file mode 100644
index 1f7ec21..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.msim.vcd
+++ /dev/null
@@ -1,148 +0,0 @@
-$comment
- File created using the following command:
- vcd file GateDemo.msim.vcd -direction
-$end
-$date
- Sat Feb 18 14:55:14 2023
-$end
-$version
- ModelSim Version 2020.1
-$end
-$timescale
- 1ps
-$end
-
-$scope module gatedemo_vhd_vec_tst $end
-$var wire 1 ! LEDR [0] $end
-$var wire 1 " SW [1] $end
-$var wire 1 # SW [0] $end
-
-$scope module i1 $end
-$var wire 1 $ gnd $end
-$var wire 1 % vcc $end
-$var wire 1 & unknown $end
-$var wire 1 ' devoe $end
-$var wire 1 ( devclrn $end
-$var wire 1 ) devpor $end
-$var wire 1 * ww_devoe $end
-$var wire 1 + ww_devclrn $end
-$var wire 1 , ww_devpor $end
-$var wire 1 - ww_LEDR [0] $end
-$var wire 1 . ww_SW [1] $end
-$var wire 1 / ww_SW [0] $end
-$var wire 1 0 \LEDR[0]~output_o\ $end
-$var wire 1 1 \SW[1]~input_o\ $end
-$var wire 1 2 \SW[0]~input_o\ $end
-$var wire 1 3 \inst~combout\ $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0$
-1%
-x&
-1'
-1(
-1)
-1*
-1+
-1,
-00
-01
-02
-03
-0"
-0#
-0-
-0.
-0/
-0!
-$end
-#80000
-1#
-1/
-12
-#180000
-0#
-0/
-02
-#240000
-1"
-1.
-11
-#340000
-0"
-0.
-01
-#420000
-1#
-1/
-12
-#480000
-1"
-1.
-11
-13
-10
-1-
-1!
-#560000
-0"
-0.
-01
-03
-00
-0-
-0!
-#620000
-0#
-0/
-02
-#660000
-1#
-1"
-1/
-1.
-11
-12
-13
-10
-1-
-1!
-#720000
-0#
-0"
-0/
-0.
-01
-02
-03
-00
-0-
-0!
-#760000
-1"
-1.
-11
-#800000
-1#
-1/
-12
-13
-10
-1-
-1!
-#900000
-0#
-0/
-02
-03
-00
-0-
-0!
-#960000
-0"
-0.
-01
-#1000000
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.sft b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.vho b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.vho
deleted file mode 100644
index 8ef6c35..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.vho
+++ /dev/null
@@ -1,115 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "02/18/2023 14:55:13"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY GateDemo IS
- PORT (
- LEDR : OUT std_logic_vector(0 DOWNTO 0);
- SW : IN std_logic_vector(1 DOWNTO 0)
- );
-END GateDemo;
-
-ARCHITECTURE structure OF GateDemo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDR : std_logic_vector(0 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(1 DOWNTO 0);
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \inst~combout\ : std_logic;
-
-BEGIN
-
-LEDR <= ww_LEDR;
-ww_SW <= SW;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst~combout\,
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
-inst : cycloneive_lcell_comb
--- Equation(s):
--- \inst~combout\ = (\SW[1]~input_o\ & \SW[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000100010001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[1]~input_o\,
- datab => \SW[0]~input_o\,
- combout => \inst~combout\);
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.vwf.vht b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.vwf.vht
deleted file mode 100644
index 6e6f34a..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo.vwf.vht
+++ /dev/null
@@ -1,98 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- *****************************************************************************
--- This file contains a Vhdl test bench with test vectors .The test vectors
--- are exported from a vector file in the Quartus Waveform Editor and apply to
--- the top level entity of the current Quartus project .The user can use this
--- testbench to simulate his design using a third-party simulation tool .
--- *****************************************************************************
--- Generated on "02/18/2023 14:55:12"
-
--- Vhdl Test Bench(with test vectors) for design : GateDemo
---
--- Simulation tool : 3rd Party
---
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY GateDemo_vhd_vec_tst IS
-END GateDemo_vhd_vec_tst;
-ARCHITECTURE GateDemo_arch OF GateDemo_vhd_vec_tst IS
--- constants
--- signals
-SIGNAL LEDR : STD_LOGIC_VECTOR(0 DOWNTO 0);
-SIGNAL SW : STD_LOGIC_VECTOR(1 DOWNTO 0);
-COMPONENT GateDemo
- PORT (
- LEDR : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- SW : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
- );
-END COMPONENT;
-BEGIN
- i1 : GateDemo
- PORT MAP (
--- list connections between master ports and signals
- LEDR => LEDR,
- SW => SW
- );
-
--- SW[0]
-t_prcs_SW_0: PROCESS
-BEGIN
- SW(0) <= '0';
- WAIT FOR 80000 ps;
- SW(0) <= '1';
- WAIT FOR 100000 ps;
- SW(0) <= '0';
- WAIT FOR 240000 ps;
- SW(0) <= '1';
- WAIT FOR 200000 ps;
- SW(0) <= '0';
- WAIT FOR 40000 ps;
- SW(0) <= '1';
- WAIT FOR 60000 ps;
- SW(0) <= '0';
- WAIT FOR 80000 ps;
- SW(0) <= '1';
- WAIT FOR 100000 ps;
- SW(0) <= '0';
-WAIT;
-END PROCESS t_prcs_SW_0;
-
--- SW[1]
-t_prcs_SW_1: PROCESS
-BEGIN
- SW(1) <= '0';
- WAIT FOR 240000 ps;
- SW(1) <= '1';
- WAIT FOR 100000 ps;
- SW(1) <= '0';
- WAIT FOR 140000 ps;
- SW(1) <= '1';
- WAIT FOR 80000 ps;
- SW(1) <= '0';
- WAIT FOR 100000 ps;
- SW(1) <= '1';
- WAIT FOR 60000 ps;
- SW(1) <= '0';
- WAIT FOR 40000 ps;
- SW(1) <= '1';
- WAIT FOR 200000 ps;
- SW(1) <= '0';
-WAIT;
-END PROCESS t_prcs_SW_1;
-END GateDemo_arch;
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo_20230218145515.sim.vwf b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo_20230218145515.sim.vwf
deleted file mode 100644
index 189fe9c..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo_20230218145515.sim.vwf
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("LEDR[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("SW[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("SW[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-TRANSITION_LIST("LEDR[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 480.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 60.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 240.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 60.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 240.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 140.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 60.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 40.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDR[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo_modelsim.xrf
deleted file mode 100644
index b2a85ac..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/GateDemo_modelsim.xrf
+++ /dev/null
@@ -1,7 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.bdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/db/GateDemo.cbx.xml
-design_name = GateDemo
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, GateDemo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, GateDemo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, GateDemo, 1
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/transcript
deleted file mode 100644
index d9da00f..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/transcript
+++ /dev/null
@@ -1,43 +0,0 @@
-# do GateDemo.do
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 14:55:14 on Feb 18,2023
-# vcom -work work GateDemo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity GateDemo
-# -- Compiling architecture structure of GateDemo
-# End time: 14:55:14 on Feb 18,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 14:55:14 on Feb 18,2023
-# vcom -work work GateDemo.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity GateDemo_vhd_vec_tst
-# -- Compiling architecture GateDemo_arch of GateDemo_vhd_vec_tst
-# End time: 14:55:14 on Feb 18,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.GateDemo_vhd_vec_tst
-# Start time: 14:55:14 on Feb 18,2023
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading work.gatedemo_vhd_vec_tst(gatedemo_arch)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading cycloneive.cycloneive_atom_pack(body)
-# Loading cycloneive.cycloneive_components
-# Loading work.gatedemo(structure)
-# Loading ieee.std_logic_arith(body)
-# Loading cycloneive.cycloneive_io_obuf(arch)
-# Loading cycloneive.cycloneive_io_ibuf(arch)
-# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#29
-# End time: 14:55:14 on Feb 18,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/vwf_sim_transcript
deleted file mode 100644
index 212f8d4..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/vwf_sim_transcript
+++ /dev/null
@@ -1,67 +0,0 @@
-Determining the location of the ModelSim executable...
-
-Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
-
-To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
-Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
-
-**** Generating the ModelSim Testbench ****
-
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off GateDemo -c GateDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/GateDemo.vwf.vht"
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Sat Feb 18 14:55:12 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off GateDemo -c GateDemo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/GateDemo.vwf.vhtInfo (119006): Selected device EP4CE115F29C7 for design "GateDemo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Completed successfully.
-
-**** Generating the functional simulation netlist ****
-
-quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/" GateDemo -c GateDemo
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Sat Feb 18 14:55:13 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/ GateDemo -c GateDemoInfo (119006): Selected device EP4CE115F29C7 for design "GateDemo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file GateDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 615 megabytes Info: Processing ended: Sat Feb 18 14:55:13 2023 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00
-Completed successfully.
-
-**** Generating the ModelSim .do script ****
-
-/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/GateDemo.do generated.
-
-Completed successfully.
-
-**** Running the ModelSim simulation ****
-
-/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do GateDemo.do
-
-Reading pref.tcl
-# 2020.1
-# do GateDemo.do
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 14:55:14 on Feb 18,2023# vcom -work work GateDemo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164# -- Loading package VITAL_Timing# -- Loading package VITAL_Primitives# -- Loading package cycloneive_atom_pack# -- Loading package cycloneive_components# -- Compiling entity GateDemo# -- Compiling architecture structure of GateDemo
-# End time: 14:55:14 on Feb 18,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020# Start time: 14:55:14 on Feb 18,2023
-# vcom -work work GateDemo.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164# -- Compiling entity GateDemo_vhd_vec_tst# -- Compiling architecture GateDemo_arch of GateDemo_vhd_vec_tst
-# End time: 14:55:14 on Feb 18,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.GateDemo_vhd_vec_tst # Start time: 14:55:14 on Feb 18,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.gatedemo_vhd_vec_tst(gatedemo_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.gatedemo(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#29
-# End time: 14:55:14 on Feb 18,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-Completed successfully.
-
-**** Converting ModelSim VCD to vector waveform ****
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.vwf...
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/GateDemo.msim.vcd...
-
-Processing channel transitions...
-
-Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/GateDemo_20230218145515.sim.vwf
-
-Finished VCD to VWF conversion.
-
-Completed successfully.
-
-All completed.
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_info
deleted file mode 100644
index 79d7988..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_info
+++ /dev/null
@@ -1,101 +0,0 @@
-m255
-K4
-z2
-!s11e vcom 2020.1 2020.02, Feb 28 2020
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-Z0 d/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim
-Egatedemo
-Z1 w1676732113
-Z2 DPx4 ieee 16 vital_primitives 0 22 G>kiXP8Q9dRClKfK1Zn7j1
-Z3 DPx10 cycloneive 20 cycloneive_atom_pack 0 22 WOh:M[al;oVzG5c`D0
-Z4 DPx4 ieee 12 vital_timing 0 22 J>EBealN09f8GzldA[z2>3
-Z5 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
-Z6 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
-Z7 DPx10 cycloneive 21 cycloneive_components 0 22 zGMDhP>8e@2k@f0eUSo020
-!s100 XYFQ4nK6noeeQ6Oi7R@NC2
-R10
-32
-R11
-!i10b 1
-R12
-Z20 !s90 -work|work|GateDemo.vwf.vht|
-!s107 GateDemo.vwf.vht|
-!i113 1
-R15
-R16
-Agatedemo_arch
-R5
-R6
-DEx4 work 20 gatedemo_vhd_vec_tst 0 22 6cP6Ym2gH5GlGLc>USo020
-!i122 1
-l45
-L34 65
-VAWn[ofOfCQJAS:J35V3Ag3
-!s100 ld`k5>H9L8ZlW>XlPiCJF0
-R10
-32
-R11
-!i10b 1
-R12
-R20
-Z21 !s107 GateDemo.vwf.vht|
-!i113 1
-R15
-R16
diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_lib.qdb b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_lib.qdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_lib1_0.qdb b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_lib1_0.qdb
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diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_lib1_0.qpg b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_lib1_0.qpg
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diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_lib1_0.qtl b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_lib1_0.qtl
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diff --git a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_vmake b/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_vmake
deleted file mode 100644
index 37aa36a..0000000
--- a/1ano/2semestre/lsd/pratica01/part1/simulation/qsim/work/_vmake
+++ /dev/null
@@ -1,4 +0,0 @@
-m255
-K4
-z0
-cModel Technology
diff --git a/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qsf b/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qsf
deleted file mode 100644
index 6f920ee..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qsf
+++ /dev/null
@@ -1,588 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 15:12:52 February 18, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# AND2Gate_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY GateDemo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:12:52 FEBRUARY 18, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_global_assignment -name BDF_FILE NAND2Block.bdf
-set_global_assignment -name VHDL_FILE AND2Gate.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE AND2Gate.vwf
-set_global_assignment -name VHDL_FILE GateDemo.vhd
-set_global_assignment -name VHDL_FILE NOTGate.vhd
-set_global_assignment -name VHDL_FILE NAND2Gate.vhd
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qsf.bak b/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qsf.bak
deleted file mode 100644
index 6f920ee..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qsf.bak
+++ /dev/null
@@ -1,588 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 15:12:52 February 18, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# AND2Gate_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY GateDemo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:12:52 FEBRUARY 18, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_global_assignment -name BDF_FILE NAND2Block.bdf
-set_global_assignment -name VHDL_FILE AND2Gate.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE AND2Gate.vwf
-set_global_assignment -name VHDL_FILE GateDemo.vhd
-set_global_assignment -name VHDL_FILE NOTGate.vhd
-set_global_assignment -name VHDL_FILE NAND2Gate.vhd
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qws b/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qws
deleted file mode 100644
index 5d92ff2..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qws and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd.bak b/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd.bak
deleted file mode 100644
index 3514f17..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd.bak
+++ /dev/null
@@ -1,17 +0,0 @@
--- Bibliotecas
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
--- Interface (portos)
-entity AND2Gate is
- port(
- inPort0 : in std_logic;
- inPort1 : in std_logic;
- outPort : out std_logic
- );
-end AND2Gate;
-
--- Implementação (descrição do funcionalidade)
-architecture Behavioral of AND2Gate is begin
- outPort <= inPort0 and inPort1;
-end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd.bak b/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd.bak
deleted file mode 100644
index 1d16ab4..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd.bak
+++ /dev/null
@@ -1,19 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity GateDemo is
- port (
- SW : in std_logic_vector(1 downto 0);
- LEDR : out std_logic_vector(1 downto 0)
- );
-end GateDemo;
-
-architecture Shell of GateDemo is
-begin
- system_core: entity work.AND2Gate(Behavioral)
- port map(
- inPort0 => SW(0),
- inPort1 => SW(1),
- outPort => LEDR(0),
- );
-end Shell;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd.bak b/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd.bak
deleted file mode 100644
index e69de29..0000000
diff --git a/1ano/2semestre/lsd/pratica01/part2/VHDLDemo.qpf b/1ano/2semestre/lsd/pratica01/part2/VHDLDemo.qpf
deleted file mode 100644
index a27f912..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/VHDLDemo.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 15:12:52 February 18, 2023
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "20.1"
-DATE = "15:12:52 February 18, 2023"
-
-# Revisions
-
-PROJECT_REVISION = "AND2Gate"
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(0).cnf.cdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(0).cnf.cdb
deleted file mode 100644
index 40b2b7c..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(0).cnf.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(0).cnf.hdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(0).cnf.hdb
deleted file mode 100644
index fd16ba8..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(1).cnf.cdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(1).cnf.cdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(1).cnf.hdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(1).cnf.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(2).cnf.cdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(2).cnf.cdb
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(2).cnf.hdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(2).cnf.hdb
deleted file mode 100644
index a9f3553..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(3).cnf.cdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(3).cnf.cdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(3).cnf.hdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(3).cnf.hdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(4).cnf.cdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(4).cnf.cdb
deleted file mode 100644
index 1b1f545..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(4).cnf.hdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.(4).cnf.hdb
deleted file mode 100644
index 3a44305..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.asm.qmsg b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.asm.qmsg
deleted file mode 100644
index 56d8deb..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.asm.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678230237613 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678230237614 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 23:03:57 2023 " "Processing started: Tue Mar 7 23:03:57 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678230237614 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678230237614 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678230237614 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678230237753 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678230239241 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678230239304 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678230239490 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 23:03:59 2023 " "Processing ended: Tue Mar 7 23:03:59 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678230239490 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678230239490 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678230239490 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678230239490 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.asm.rdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.asm.rdb
deleted file mode 100644
index 4f4ef2a..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.asm_labs.ddb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.asm_labs.ddb
deleted file mode 100644
index 26951bc..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.asm_labs.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cbx.xml b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cbx.xml
deleted file mode 100644
index cb70f48..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.bpm b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.bpm
deleted file mode 100644
index 797aaa1..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.cdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.cdb
deleted file mode 100644
index a636a62..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.hdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.hdb
deleted file mode 100644
index 2665eab..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.idb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.idb
deleted file mode 100644
index d67347b..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.idb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.logdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.logdb
deleted file mode 100644
index 3a1cd31..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.logdb
+++ /dev/null
@@ -1,46 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;4;4;0;0;4;4;0;0;0;0;0;0;2;0;0;0;2;2;0;2;0;0;2;0;4;4;4;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,4;0;0;4;4;0;0;4;4;4;4;4;4;2;4;4;4;2;2;4;2;4;4;2;4;0;0;0;4;4,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.rdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp.rdb
deleted file mode 100644
index 707398d..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp_merge.kpt b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cmp_merge.kpt
deleted file mode 100644
index 40f9d76..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index d9c61ce..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
deleted file mode 100644
index 218eca7..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
deleted file mode 100644
index 201d97d..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.db_info b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.db_info
deleted file mode 100644
index 5fba7ad..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Tue Mar 7 23:03:12 2023
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.eda.qmsg b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.eda.qmsg
deleted file mode 100644
index 1d2badc..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678230241841 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678230241842 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 23:04:01 2023 " "Processing started: Tue Mar 7 23:04:01 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678230241842 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678230241842 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678230241842 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678230241997 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "AND2Gate.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/ simulation " "Generated file AND2Gate.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678230242022 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678230242037 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 23:04:02 2023 " "Processing ended: Tue Mar 7 23:04:02 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678230242037 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678230242037 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678230242037 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678230242037 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.fit.qmsg b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.fit.qmsg
deleted file mode 100644
index 45cbcb7..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.fit.qmsg
+++ /dev/null
@@ -1,48 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678230231049 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678230231049 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "AND2Gate EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"AND2Gate\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678230231051 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678230231098 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678230231098 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678230231325 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678230231328 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678230231358 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678230231358 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678230231358 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678230231358 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678230231358 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678230231358 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678230231358 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678230231358 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678230231358 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678230231358 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/" { { 0 { 0 ""} 0 576 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678230231360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/" { { 0 { 0 ""} 0 578 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678230231360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/" { { 0 { 0 ""} 0 580 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678230231360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/" { { 0 { 0 ""} 0 582 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678230231360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/" { { 0 { 0 ""} 0 584 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678230231360 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678230231360 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678230231360 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AND2Gate.sdc " "Synopsys Design Constraints File file not found: 'AND2Gate.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678230231827 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678230231827 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678230231827 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678230231827 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678230231828 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678230231828 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678230231828 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678230231829 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678230231830 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678230231830 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678230231830 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678230231830 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678230231830 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678230231830 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678230231830 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678230231830 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678230231830 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678230231830 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678230231839 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678230231839 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678230231846 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678230231848 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678230233317 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678230233383 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678230233411 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678230233570 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678230233571 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678230233695 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y24 X115_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y24 to location X115_Y36" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y24 to location X115_Y36"} { { 12 { 0 ""} 104 24 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678230235929 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678230235929 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678230236056 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678230236056 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678230236056 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678230236058 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678230236139 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678230236144 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678230236309 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678230236309 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678230236469 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678230236715 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678230236882 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678230236920 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 522 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 522 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1149 " "Peak virtual memory: 1149 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678230237054 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 23:03:57 2023 " "Processing ended: Tue Mar 7 23:03:57 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678230237054 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678230237054 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678230237054 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678230237054 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.hier_info b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.hier_info
deleted file mode 100644
index a325dca..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.hier_info
+++ /dev/null
@@ -1,24 +0,0 @@
-|GateDemo
-SW[0] => nand2gate:system_core.inPort0
-SW[1] => nand2gate:system_core.inPort1
-LEDR[0] << nand2gate:system_core.outPort
-LEDR[1] <<
-
-
-|GateDemo|NAND2Gate:system_core
-inPort0 => and2gate:and_gate.inPort0
-inPort1 => and2gate:and_gate.inPort1
-outPort <= notgate:not_gate.outPort
-
-
-|GateDemo|NAND2Gate:system_core|AND2Gate:and_gate
-inPort0 => outPort.IN0
-inPort1 => outPort.IN1
-outPort <= outPort.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|GateDemo|NAND2Gate:system_core|NOTGate:not_gate
-inPort => outPort.DATAIN
-outPort <= inPort.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.hif b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.hif
deleted file mode 100644
index ee29040..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.lpc.html b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.lpc.html
deleted file mode 100644
index 24c88fa..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.lpc.html
+++ /dev/null
@@ -1,66 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| system_core|not_gate |
-1 |
-0 |
-0 |
-0 |
-1 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
-| system_core|and_gate |
-2 |
-0 |
-0 |
-0 |
-1 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
-| system_core |
-2 |
-0 |
-0 |
-0 |
-1 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.lpc.rdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.lpc.rdb
deleted file mode 100644
index 0fdf26d..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.lpc.txt b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.lpc.txt
deleted file mode 100644
index 54485ec..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.lpc.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+----------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+----------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; system_core|not_gate ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; system_core|and_gate ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; system_core ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+----------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.ammdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.ammdb
deleted file mode 100644
index 790b913..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.bpm b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.bpm
deleted file mode 100644
index 8e20dd6..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.cdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.cdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.hdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.hdb
deleted file mode 100644
index e0a3768..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.kpt b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.kpt
deleted file mode 100644
index 2e103e2..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.qmsg b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.qmsg
deleted file mode 100644
index 623ce42..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.qmsg
+++ /dev/null
@@ -1,20 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678230224767 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678230224767 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 23:03:44 2023 " "Processing started: Tue Mar 7 23:03:44 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678230224767 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230224767 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230224767 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678230224894 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678230224894 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NAND2Block.bdf 1 1 " "Found 1 design units, including 1 entities, in source file NAND2Block.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 NAND2Block " "Found entity 1: NAND2Block" { } { { "NAND2Block.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229573 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230229573 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AND2Gate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AND2Gate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AND2Gate-Behavioral " "Found design unit 1: AND2Gate-Behavioral" { } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229787 ""} { "Info" "ISGN_ENTITY_NAME" "1 AND2Gate " "Found entity 1: AND2Gate" { } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229787 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230229787 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GateDemo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file GateDemo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 GateDemo-Shell " "Found design unit 1: GateDemo-Shell" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229788 ""} { "Info" "ISGN_ENTITY_NAME" "1 GateDemo " "Found entity 1: GateDemo" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230229788 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NOTGate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file NOTGate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NOTGate-Behavioral " "Found design unit 1: NOTGate-Behavioral" { } { { "NOTGate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229788 ""} { "Info" "ISGN_ENTITY_NAME" "1 NOTGate " "Found entity 1: NOTGate" { } { { "NOTGate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230229788 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NAND2Gate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file NAND2Gate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NAND2Gate-Structural " "Found design unit 1: NAND2Gate-Structural" { } { { "NAND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229788 ""} { "Info" "ISGN_ENTITY_NAME" "1 NAND2Gate " "Found entity 1: NAND2Gate" { } { { "NAND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230229788 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "GateDemo " "Elaborating entity \"GateDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678230229819 ""}
-{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[1\] GateDemo.vhd(7) " "Using initial value X (don't care) for net \"LEDR\[1\]\" at GateDemo.vhd(7)" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 7 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230229820 "|GateDemo"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "NAND2Gate NAND2Gate:system_core A:structural " "Elaborating entity \"NAND2Gate\" using architecture \"A:structural\" for hierarchy \"NAND2Gate:system_core\"" { } { { "GateDemo.vhd" "system_core" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 13 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678230229821 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "AND2Gate NAND2Gate:system_core\|AND2Gate:and_gate A:behavioral " "Elaborating entity \"AND2Gate\" using architecture \"A:behavioral\" for hierarchy \"NAND2Gate:system_core\|AND2Gate:and_gate\"" { } { { "NAND2Gate.vhd" "and_gate" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 15 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678230229821 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "NOTGate NAND2Gate:system_core\|NOTGate:not_gate A:behavioral " "Elaborating entity \"NOTGate\" using architecture \"A:behavioral\" for hierarchy \"NAND2Gate:system_core\|NOTGate:not_gate\"" { } { { "NAND2Gate.vhd" "not_gate" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 22 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678230229822 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[1\] GND " "Pin \"LEDR\[1\]\" is stuck at GND" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678230230102 "|GateDemo|LEDR[1]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1678230230102 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678230230161 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678230230471 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678230230471 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "5 " "Implemented 5 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678230230485 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678230230485 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678230230485 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678230230485 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678230230488 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 23:03:50 2023 " "Processing ended: Tue Mar 7 23:03:50 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678230230488 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678230230488 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678230230488 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230230488 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.rdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.rdb
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map_bb.hdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map_bb.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.pre_map.hdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.root_partition.map.reg_db.cdb
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.routing.rdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.rtlv.hdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.rtlv_sg.cdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.rtlv_sg.cdb
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.rtlv_sg_swap.cdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.rtlv_sg_swap.cdb
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.sld_design_entry.sci b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.smart_action.txt b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.smart_action.txt
deleted file mode 100644
index c8e8a13..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.sta.qmsg b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.sta.qmsg
deleted file mode 100644
index 92dc7c8..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678230239960 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678230239960 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 23:03:59 2023 " "Processing started: Tue Mar 7 23:03:59 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678230239960 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678230239960 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta VHDLDemo -c AND2Gate " "Command: quartus_sta VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678230239960 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678230239981 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678230240041 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678230240041 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678230240091 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678230240091 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AND2Gate.sdc " "Synopsys Design Constraints File file not found: 'AND2Gate.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678230240398 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678230240398 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678230240398 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678230240398 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678230240398 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678230240399 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678230240399 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678230240402 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678230240402 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240402 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240404 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240405 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240405 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240405 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240405 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678230240407 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678230240421 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678230240582 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678230240596 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678230240596 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678230240596 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678230240596 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240597 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240597 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240598 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240598 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240598 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240598 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678230240600 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678230240638 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678230240639 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678230240639 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678230240639 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240639 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240640 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240640 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240640 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240641 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678230240845 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678230240845 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "533 " "Peak virtual memory: 533 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678230240853 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 23:04:00 2023 " "Processing ended: Tue Mar 7 23:04:00 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678230240853 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678230240853 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678230240853 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678230240853 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.sta.rdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.sta.rdb
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.sta_cmp.7_slow_1200mv_85c.tdb
deleted file mode 100644
index efe67f5..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.tis_db_list.ddb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.tis_db_list.ddb
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.tiscmp.fast_1200mv_0c.ddb
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index ff87e3a..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.tmw_info b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.tmw_info
deleted file mode 100644
index 9d748df..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.tmw_info
+++ /dev/null
@@ -1,7 +0,0 @@
-start_full_compilation:s:00:00:18
-start_analysis_synthesis:s:00:00:06-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:07-start_full_compilation
-start_assembler:s:00:00:02-start_full_compilation
-start_timing_analyzer:s:00:00:02-start_full_compilation
-start_eda_netlist_writer:s:00:00:01-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.vpr.ammdb b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.vpr.ammdb
deleted file mode 100644
index df57b4b..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate_partition_pins.json b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate_partition_pins.json
deleted file mode 100644
index c571473..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate_partition_pins.json
+++ /dev/null
@@ -1,21 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "LEDR[0]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/VHDLDemo.map_bb.logdb b/1ano/2semestre/lsd/pratica01/part2/db/VHDLDemo.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/VHDLDemo.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica01/part2/db/prev_cmp_VHDLDemo.qmsg b/1ano/2semestre/lsd/pratica01/part2/db/prev_cmp_VHDLDemo.qmsg
deleted file mode 100644
index afc49e5..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/db/prev_cmp_VHDLDemo.qmsg
+++ /dev/null
@@ -1,13 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678221015692 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221015692 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:30:15 2023 " "Processing started: Tue Mar 7 20:30:15 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678221015692 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221015692 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221015692 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678221015844 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678221015844 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NAND2Block.bdf 1 1 " "Found 1 design units, including 1 entities, in source file NAND2Block.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 NAND2Block " "Found entity 1: NAND2Block" { } { { "NAND2Block.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221021063 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221021063 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AND2Gate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AND2Gate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AND2Gate-Behavioral " "Found design unit 1: AND2Gate-Behavioral" { } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221021302 ""} { "Info" "ISGN_ENTITY_NAME" "1 AND2Gate " "Found entity 1: AND2Gate" { } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221021302 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221021302 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GateDemo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file GateDemo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 GateDemo-Shell " "Found design unit 1: GateDemo-Shell" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221021302 ""} { "Info" "ISGN_ENTITY_NAME" "1 GateDemo " "Found entity 1: GateDemo" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221021302 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221021302 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NOTGate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file NOTGate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NOTGate-Behavioral " "Found design unit 1: NOTGate-Behavioral" { } { { "NOTGate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221021302 ""} { "Info" "ISGN_ENTITY_NAME" "1 NOTGate " "Found entity 1: NOTGate" { } { { "NOTGate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221021302 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221021302 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NAND2Gate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file NAND2Gate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NAND2Gate-Structural " "Found design unit 1: NAND2Gate-Structural" { } { { "NAND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221021303 ""} { "Info" "ISGN_ENTITY_NAME" "1 NAND2Gate " "Found entity 1: NAND2Gate" { } { { "NAND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221021303 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221021303 ""}
-{ "Error" "EVRFX_VHDL_IS_NOT_COMPILED_IN_LIBRARY" "NAND2Block work GateDemo.vhd(13) " "VHDL Use Clause error at GateDemo.vhd(13): design library \"work\" does not contain primary unit \"NAND2Block\". Verify that the primary unit exists in the library and has been successfully compiled." { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 13 0 0 } } } 0 10481 "VHDL Use Clause error at %3!s!: design library \"%2!s!\" does not contain primary unit \"%1!s!\". Verify that the primary unit exists in the library and has been successfully compiled." 0 0 "Analysis & Synthesis" 0 -1 1678221021303 ""}
-{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "420 " "Peak virtual memory: 420 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678221021380 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Mar 7 20:30:21 2023 " "Processing ended: Tue Mar 7 20:30:21 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678221021380 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678221021380 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678221021380 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221021380 ""}
-{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1 " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221021455 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/README b/1ano/2semestre/lsd/pratica01/part2/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.db_info b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.db_info
deleted file mode 100644
index 4bc5884..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Sat Feb 18 15:25:21 2023
diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.ammdb
deleted file mode 100644
index 367d91a..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.cdb
deleted file mode 100644
index fbe6f80..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.dfp and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.hdb
deleted file mode 100644
index 092bdee..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.cmp.rcfdb
deleted file mode 100644
index f17e66a..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.cdb b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.cdb
deleted file mode 100644
index 321268c..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.dpi b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.dpi
deleted file mode 100644
index bd05d17..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.hbdb.cdb
deleted file mode 100644
index 7a00f27..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.hbdb.hdb
deleted file mode 100644
index 4423e12..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.hdb b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.hdb
deleted file mode 100644
index 6ce19e7..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.kpt b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.root_partition.map.kpt
deleted file mode 100644
index 99f07fb..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.rrp.hdb b/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.rrp.hdb
deleted file mode 100644
index f47f7ea..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part2/incremental_db/compiled_partitions/AND2Gate.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.asm.rpt b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.asm.rpt
deleted file mode 100644
index 29ffe47..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for AND2Gate
-Tue Mar 7 23:03:59 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: AND2Gate.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Tue Mar 7 23:03:59 2023 ;
-; Revision Name ; AND2Gate ;
-; Top-level Entity Name ; GateDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+-----------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+-----------------------------------------------------------------------------------------------+
-; File Name ;
-+-----------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.sof ;
-+-----------------------------------------------------------------------------------------------+
-
-
-+----------------------------------------+
-; Assembler Device Options: AND2Gate.sof ;
-+----------------+-----------------------+
-; Option ; Setting ;
-+----------------+-----------------------+
-; JTAG usercode ; 0x00562F27 ;
-; Checksum ; 0x00562F27 ;
-+----------------+-----------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 23:03:57 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 367 megabytes
- Info: Processing ended: Tue Mar 7 23:03:59 2023
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.done b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.done
deleted file mode 100644
index dfe2f75..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.done
+++ /dev/null
@@ -1 +0,0 @@
-Tue Mar 7 23:04:02 2023
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.eda.rpt b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.eda.rpt
deleted file mode 100644
index 1027da4..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.eda.rpt
+++ /dev/null
@@ -1,94 +0,0 @@
-EDA Netlist Writer report for AND2Gate
-Tue Mar 7 23:04:02 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Tue Mar 7 23:04:02 2023 ;
-; Revision Name ; AND2Gate ;
-; Top-level Entity Name ; GateDemo ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+------------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+------------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/AND2Gate.vho ;
-+------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 23:04:01 2023
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file AND2Gate.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 612 megabytes
- Info: Processing ended: Tue Mar 7 23:04:02 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.rpt b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.rpt
deleted file mode 100644
index bcbd3cb..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.rpt
+++ /dev/null
@@ -1,2505 +0,0 @@
-Fitter report for AND2Gate
-Tue Mar 7 23:03:56 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Tue Mar 7 23:03:56 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; AND2Gate ;
-; Top-level Entity Name ; GateDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 1 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 1 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 4 / 529 ( < 1 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; CLOCK_50 ; PIN_Y2 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
-; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
-; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
-; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
-; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
-; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
-; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[0] ; PIN_M23 ; QSF Assignment ;
-; Location ; ; ; KEY[1] ; PIN_M21 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[0] ; PIN_E21 ; QSF Assignment ;
-; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
-; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
-; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[2] ; PIN_E19 ; QSF Assignment ;
-; Location ; ; ; LEDR[3] ; PIN_F21 ; QSF Assignment ;
-; Location ; ; ; LEDR[4] ; PIN_F18 ; QSF Assignment ;
-; Location ; ; ; LEDR[5] ; PIN_E18 ; QSF Assignment ;
-; Location ; ; ; LEDR[6] ; PIN_J19 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_H19 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; SW[10] ; PIN_AC24 ; QSF Assignment ;
-; Location ; ; ; SW[11] ; PIN_AB24 ; QSF Assignment ;
-; Location ; ; ; SW[12] ; PIN_AB23 ; QSF Assignment ;
-; Location ; ; ; SW[13] ; PIN_AA24 ; QSF Assignment ;
-; Location ; ; ; SW[14] ; PIN_AA23 ; QSF Assignment ;
-; Location ; ; ; SW[15] ; PIN_AA22 ; QSF Assignment ;
-; Location ; ; ; SW[16] ; PIN_Y24 ; QSF Assignment ;
-; Location ; ; ; SW[17] ; PIN_Y23 ; QSF Assignment ;
-; Location ; ; ; SW[2] ; PIN_AC27 ; QSF Assignment ;
-; Location ; ; ; SW[3] ; PIN_AD27 ; QSF Assignment ;
-; Location ; ; ; SW[4] ; PIN_AB27 ; QSF Assignment ;
-; Location ; ; ; SW[5] ; PIN_AC26 ; QSF Assignment ;
-; Location ; ; ; SW[6] ; PIN_AD26 ; QSF Assignment ;
-; Location ; ; ; SW[7] ; PIN_AB26 ; QSF Assignment ;
-; Location ; ; ; SW[8] ; PIN_AC25 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AB25 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 20 ) ; 0.00 % ( 0 / 20 ) ; 0.00 % ( 0 / 20 ) ;
-; -- Achieved ; 0.00 % ( 0 / 20 ) ; 0.00 % ( 0 / 20 ) ; 0.00 % ( 0 / 20 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+-----------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-----------------------+
-; Total logic elements ; 1 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 1 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 0 ;
-; -- <=2 input functions ; 1 ;
-; -- Register only ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers* ; 0 / 117,053 ( 0 % ) ;
-; -- Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 1 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 4 / 529 ( < 1 % ) ;
-; -- Clock pins ; 0 / 7 ( 0 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ;
-; Maximum fan-out ; 1 ;
-; Highest non-global fan-out ; 1 ;
-; Total fan-out ; 12 ;
-; Average fan-out ; 0.63 ;
-+---------------------------------------------+-----------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 1 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 1 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 0 ; 0 ;
-; -- 3 input functions ; 0 ; 0 ;
-; -- <=2 input functions ; 1 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 1 ; 0 ;
-; -- arithmetic mode ; 0 ; 0 ;
-; ; ; ;
-; Total registers ; 0 ; 0 ;
-; -- Dedicated logic registers ; 0 / 114480 ( 0 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 1 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 4 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 7 ; 5 ;
-; -- Registered Connections ; 0 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 2 ; 0 ;
-; -- Output Ports ; 2 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+----------------------+--------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+----------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+----------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+----------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 0 / 63 ( 0 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 2 / 65 ( 3 % ) ; 2.5V ; -- ;
-; 6 ; 1 / 58 ( 2 % ) ; 2.5V ; -- ;
-; 7 ; 2 / 72 ( 3 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+----------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA23 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA24 ; 279 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB24 ; 274 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB25 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB26 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB27 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC25 ; 272 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC26 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC27 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD27 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y24 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; LEDR[0] ; Incomplete set of assignments ;
-; LEDR[1] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-; SW[1] ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------+-------------+--------------+
-; |GateDemo ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |GateDemo ; GateDemo ; work ;
-; |NAND2Gate:system_core| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |GateDemo|NAND2Gate:system_core ; NAND2Gate ; work ;
-; |AND2Gate:and_gate| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |GateDemo|NAND2Gate:system_core|AND2Gate:and_gate ; AND2Gate ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-----------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+--------------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+--------------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+--------------------------------------------------------+-------------------+---------+
-; SW[0] ; ; ;
-; - NAND2Gate:system_core|AND2Gate:and_gate|outPort ; 0 ; 6 ;
-; SW[1] ; ; ;
-; - NAND2Gate:system_core|AND2Gate:and_gate|outPort ; 0 ; 6 ;
-+--------------------------------------------------------+-------------------+---------+
-
-
-+-----------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+-----------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+-----------------------+
-; Block interconnects ; 3 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 4 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 2 / 209,544 ( < 1 % ) ;
-; Direct links ; 0 / 342,891 ( 0 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 0 / 119,088 ( 0 % ) ;
-; R24 interconnects ; 2 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 0 / 289,782 ( 0 % ) ;
-+-----------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 1.00) ; Number of LABs (Total = 1) ;
-+--------------------------------------------+-----------------------------+
-; 1 ; 1 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-+--------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 1.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 1) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 1 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 2.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 4 ; 4 ; 0 ; 0 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 2 ; 2 ; 0 ; 2 ; 0 ; 0 ; 2 ; 0 ; 4 ; 4 ; 4 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 4 ; 0 ; 0 ; 4 ; 4 ; 0 ; 0 ; 4 ; 4 ; 4 ; 4 ; 4 ; 4 ; 2 ; 4 ; 4 ; 4 ; 2 ; 2 ; 4 ; 2 ; 4 ; 4 ; 2 ; 4 ; 0 ; 0 ; 0 ; 4 ; 4 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "AND2Gate"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'AND2Gate.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y24 to location X115_Y36
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 522 warnings
- Info: Peak virtual memory: 1149 megabytes
- Info: Processing ended: Tue Mar 7 23:03:57 2023
- Info: Elapsed time: 00:00:07
- Info: Total CPU time (on all processors): 00:00:10
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.smsg b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.summary b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.summary
deleted file mode 100644
index 78aba89..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Tue Mar 7 23:03:56 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : AND2Gate
-Top-level Entity Name : GateDemo
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 1 / 114,480 ( < 1 % )
- Total combinational functions : 1 / 114,480 ( < 1 % )
- Dedicated logic registers : 0 / 114,480 ( 0 % )
-Total registers : 0
-Total pins : 4 / 529 ( < 1 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.flow.rpt b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.flow.rpt
deleted file mode 100644
index 7c2e0eb..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.flow.rpt
+++ /dev/null
@@ -1,137 +0,0 @@
-Flow report for AND2Gate
-Tue Mar 7 23:04:02 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Tue Mar 7 23:04:02 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; AND2Gate ;
-; Top-level Entity Name ; GateDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 1 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 1 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 4 / 529 ( < 1 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/07/2023 23:03:44 ;
-; Main task ; Compilation ;
-; Revision Name ; AND2Gate ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 2690080394329.167823022420872 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; GateDemo ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; GateDemo ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; GateDemo ; Top ;
-; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-; TOP_LEVEL_ENTITY ; GateDemo ; AND2Gate ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 433 MB ; 00:00:13 ;
-; Fitter ; 00:00:06 ; 1.0 ; 1149 MB ; 00:00:09 ;
-; Assembler ; 00:00:02 ; 1.0 ; 367 MB ; 00:00:02 ;
-; Timing Analyzer ; 00:00:01 ; 1.0 ; 533 MB ; 00:00:01 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 612 MB ; 00:00:00 ;
-; Total ; 00:00:16 ; -- ; -- ; 00:00:25 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate
-quartus_fit --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate
-quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate
-quartus_sta VHDLDemo -c AND2Gate
-quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate
-
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.jdi b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.jdi
deleted file mode 100644
index fd043bc..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.map.rpt b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.map.rpt
deleted file mode 100644
index 9f56a34..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.map.rpt
+++ /dev/null
@@ -1,306 +0,0 @@
-Analysis & Synthesis report for AND2Gate
-Tue Mar 7 23:03:50 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Post-Synthesis Netlist Statistics for Top Partition
- 10. Elapsed Time Per Partition
- 11. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Tue Mar 7 23:03:50 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; AND2Gate ;
-; Top-level Entity Name ; GateDemo ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 1 ;
-; Total combinational functions ; 1 ;
-; Dedicated logic registers ; 0 ;
-; Total registers ; 0 ;
-; Total pins ; 4 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; GateDemo ; AND2Gate ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+---------+
-; AND2Gate.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd ; ;
-; GateDemo.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd ; ;
-; NOTGate.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd ; ;
-; NAND2Gate.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd ; ;
-+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+---------+
-
-
-+-----------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+-------------------------------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-------------------------------------------------+
-; Estimated Total logic elements ; 1 ;
-; ; ;
-; Total combinational functions ; 1 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 0 ;
-; -- <=2 input functions ; 1 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers ; 0 ;
-; -- Dedicated logic registers ; 0 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 4 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; NAND2Gate:system_core|AND2Gate:and_gate|outPort ;
-; Maximum fan-out ; 1 ;
-; Total fan-out ; 7 ;
-; Average fan-out ; 0.78 ;
-+---------------------------------------------+-------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------+-------------+--------------+
-; |GateDemo ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; |GateDemo ; GateDemo ; work ;
-; |NAND2Gate:system_core| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GateDemo|NAND2Gate:system_core ; NAND2Gate ; work ;
-; |AND2Gate:and_gate| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |GateDemo|NAND2Gate:system_core|AND2Gate:and_gate ; AND2Gate ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 0 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 4 ;
-; cycloneiii_lcell_comb ; 3 ;
-; normal ; 3 ;
-; 0 data inputs ; 1 ;
-; 1 data inputs ; 1 ;
-; 2 data inputs ; 1 ;
-; ; ;
-; Max LUT depth ; 2.00 ;
-; Average LUT depth ; 1.60 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 23:03:44 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file NAND2Block.bdf
- Info (12023): Found entity 1: NAND2Block
-Info (12021): Found 2 design units, including 1 entities, in source file AND2Gate.vhd
- Info (12022): Found design unit 1: AND2Gate-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd Line: 15
- Info (12023): Found entity 1: AND2Gate File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd Line: 6
-Info (12021): Found 2 design units, including 1 entities, in source file GateDemo.vhd
- Info (12022): Found design unit 1: GateDemo-Shell File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd Line: 11
- Info (12023): Found entity 1: GateDemo File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd Line: 4
-Info (12021): Found 2 design units, including 1 entities, in source file NOTGate.vhd
- Info (12022): Found design unit 1: NOTGate-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd Line: 11
- Info (12023): Found entity 1: NOTGate File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd Line: 4
-Info (12021): Found 2 design units, including 1 entities, in source file NAND2Gate.vhd
- Info (12022): Found design unit 1: NAND2Gate-Structural File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd Line: 12
- Info (12023): Found entity 1: NAND2Gate File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd Line: 4
-Info (12127): Elaborating entity "GateDemo" for the top level hierarchy
-Warning (10873): Using initial value X (don't care) for net "LEDR[1]" at GateDemo.vhd(7) File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd Line: 7
-Info (12129): Elaborating entity "NAND2Gate" using architecture "A:structural" for hierarchy "NAND2Gate:system_core" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd Line: 13
-Info (12129): Elaborating entity "AND2Gate" using architecture "A:behavioral" for hierarchy "NAND2Gate:system_core|AND2Gate:and_gate" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd Line: 15
-Info (12129): Elaborating entity "NOTGate" using architecture "A:behavioral" for hierarchy "NAND2Gate:system_core|NOTGate:not_gate" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd Line: 22
-Warning (13024): Output pins are stuck at VCC or GND
- Warning (13410): Pin "LEDR[1]" is stuck at GND File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd Line: 7
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 5 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 2 input pins
- Info (21059): Implemented 2 output pins
- Info (21061): Implemented 1 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings
- Info: Peak virtual memory: 433 megabytes
- Info: Processing ended: Tue Mar 7 23:03:50 2023
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:13
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.map.summary b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.map.summary
deleted file mode 100644
index a409d8c..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Tue Mar 7 23:03:50 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : AND2Gate
-Top-level Entity Name : GateDemo
-Family : Cyclone IV E
-Total logic elements : 1
- Total combinational functions : 1
- Dedicated logic registers : 0
-Total registers : 0
-Total pins : 4
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.pin b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.pin
deleted file mode 100644
index 0e2ec4c..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "AND2Gate" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5 :
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 5 :
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7 :
-VCCIO7 : E20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
-VCCIO7 : E23 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7 :
-LEDR[1] : F19 : output : 2.5 V : : 7 : Y
-GND : F20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
-LEDR[0] : G19 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
-VCCIO7 : H18 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7 :
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6 :
-MSEL2 : M22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-GND+ : Y2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.sld b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.sta.rpt b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.sta.rpt
deleted file mode 100644
index be3cbbb..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.sta.rpt
+++ /dev/null
@@ -1,435 +0,0 @@
-Timing Analyzer report for AND2Gate
-Tue Mar 7 23:04:00 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Unconstrained Input Ports
- 37. Unconstrained Output Ports
- 38. Unconstrained Input Ports
- 39. Unconstrained Output Ports
- 40. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; AND2Gate ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.1% ;
-+----------------------------+-------------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 2 ; 2 ;
-; Unconstrained Input Port Paths ; 2 ; 2 ;
-; Unconstrained Output Ports ; 1 ; 1 ;
-; Unconstrained Output Port Paths ; 2 ; 2 ;
-+---------------------------------+-------+------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 23:03:59 2023
-Info: Command: quartus_sta VHDLDemo -c AND2Gate
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'AND2Gate.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 533 megabytes
- Info: Processing ended: Tue Mar 7 23:04:00 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.sta.summary b/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.sta.summary
deleted file mode 100644
index aa5b327..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/AND2Gate.sft b/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/AND2Gate.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/AND2Gate.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/AND2Gate.vho b/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/AND2Gate.vho
deleted file mode 100644
index af76c95..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/AND2Gate.vho
+++ /dev/null
@@ -1,198 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/07/2023 23:04:02"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY GateDemo IS
- PORT (
- SW : IN std_logic_vector(1 DOWNTO 0);
- LEDR : BUFFER std_logic_vector(1 DOWNTO 0)
- );
-END GateDemo;
-
--- Design Ports Information
--- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF GateDemo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_SW : std_logic_vector(1 DOWNTO 0);
-SIGNAL ww_LEDR : std_logic_vector(1 DOWNTO 0);
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \LEDR[1]~output_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \system_core|and_gate|outPort~combout\ : std_logic;
-SIGNAL \system_core|and_gate|ALT_INV_outPort~combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-ww_SW <= SW;
-LEDR <= ww_LEDR;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\system_core|and_gate|ALT_INV_outPort~combout\ <= NOT \system_core|and_gate|outPort~combout\;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X69_Y73_N16
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|and_gate|ALT_INV_outPort~combout\,
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N2
-\LEDR[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => GND,
- devoe => ww_devoe,
- o => \LEDR[1]~output_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: LCCOMB_X114_Y17_N8
-\system_core|and_gate|outPort\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|and_gate|outPort~combout\ = (\SW[1]~input_o\ & \SW[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010101000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[1]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \system_core|and_gate|outPort~combout\);
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-
-ww_LEDR(1) <= \LEDR[1]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/AND2Gate_modelsim.xrf b/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/AND2Gate_modelsim.xrf
deleted file mode 100644
index 6dcc488..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/AND2Gate_modelsim.xrf
+++ /dev/null
@@ -1,19 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vwf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cbx.xml
-design_name = hard_block
-design_name = GateDemo
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, GateDemo, 1
-instance = comp, \LEDR[1]~output\, LEDR[1]~output, GateDemo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, GateDemo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, GateDemo, 1
-instance = comp, \system_core|and_gate|outPort\, system_core|and_gate|outPort, GateDemo, 1
diff --git a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/AND2Gate.sft b/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/AND2Gate.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/AND2Gate.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/AND2Gate.vho b/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/AND2Gate.vho
deleted file mode 100644
index 17aa730..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/AND2Gate.vho
+++ /dev/null
@@ -1,118 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "02/18/2023 15:33:49"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY AND2Gate IS
- PORT (
- inPort0 : IN std_logic;
- inPort1 : IN std_logic;
- outPort : OUT std_logic
- );
-END AND2Gate;
-
-ARCHITECTURE structure OF AND2Gate IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_inPort0 : std_logic;
-SIGNAL ww_inPort1 : std_logic;
-SIGNAL ww_outPort : std_logic;
-SIGNAL \outPort~output_o\ : std_logic;
-SIGNAL \inPort0~input_o\ : std_logic;
-SIGNAL \inPort1~input_o\ : std_logic;
-SIGNAL \outPort~0_combout\ : std_logic;
-
-BEGIN
-
-ww_inPort0 <= inPort0;
-ww_inPort1 <= inPort1;
-outPort <= ww_outPort;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
-\outPort~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \outPort~0_combout\,
- devoe => ww_devoe,
- o => \outPort~output_o\);
-
-\inPort0~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_inPort0,
- o => \inPort0~input_o\);
-
-\inPort1~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_inPort1,
- o => \inPort1~input_o\);
-
-\outPort~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \outPort~0_combout\ = (\inPort0~input_o\ & \inPort1~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000100010001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inPort0~input_o\,
- datab => \inPort1~input_o\,
- combout => \outPort~0_combout\);
-
-ww_outPort <= \outPort~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/AND2Gate.vwf.vht b/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/AND2Gate.vwf.vht
deleted file mode 100644
index bd2a315..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/AND2Gate.vwf.vht
+++ /dev/null
@@ -1,93 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- *****************************************************************************
--- This file contains a Vhdl test bench with test vectors .The test vectors
--- are exported from a vector file in the Quartus Waveform Editor and apply to
--- the top level entity of the current Quartus project .The user can use this
--- testbench to simulate his design using a third-party simulation tool .
--- *****************************************************************************
--- Generated on "02/18/2023 15:33:49"
-
--- Vhdl Test Bench(with test vectors) for design : AND2Gate
---
--- Simulation tool : 3rd Party
---
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY AND2Gate_vhd_vec_tst IS
-END AND2Gate_vhd_vec_tst;
-ARCHITECTURE AND2Gate_arch OF AND2Gate_vhd_vec_tst IS
--- constants
--- signals
-SIGNAL inPort0 : STD_LOGIC;
-SIGNAL inPort1 : STD_LOGIC;
-SIGNAL outPort : STD_LOGIC;
-COMPONENT AND2Gate
- PORT (
- inPort0 : IN STD_LOGIC;
- inPort1 : IN STD_LOGIC;
- outPort : OUT STD_LOGIC
- );
-END COMPONENT;
-BEGIN
- i1 : AND2Gate
- PORT MAP (
--- list connections between master ports and signals
- inPort0 => inPort0,
- inPort1 => inPort1,
- outPort => outPort
- );
-
--- inPort0
-t_prcs_inPort0: PROCESS
-BEGIN
- inPort0 <= '0';
- WAIT FOR 40000 ps;
- inPort0 <= '1';
- WAIT FOR 180000 ps;
- inPort0 <= '0';
- WAIT FOR 220000 ps;
- inPort0 <= '1';
- WAIT FOR 220000 ps;
- inPort0 <= '0';
- WAIT FOR 120000 ps;
- inPort0 <= '1';
- WAIT FOR 120000 ps;
- inPort0 <= '0';
-WAIT;
-END PROCESS t_prcs_inPort0;
-
--- inPort1
-t_prcs_inPort1: PROCESS
-BEGIN
- inPort1 <= '0';
- WAIT FOR 280000 ps;
- inPort1 <= '1';
- WAIT FOR 80000 ps;
- inPort1 <= '0';
- WAIT FOR 140000 ps;
- inPort1 <= '1';
- WAIT FOR 120000 ps;
- inPort1 <= '0';
- WAIT FOR 100000 ps;
- inPort1 <= '1';
- WAIT FOR 220000 ps;
- inPort1 <= '0';
-WAIT;
-END PROCESS t_prcs_inPort1;
-END AND2Gate_arch;
diff --git a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/AND2Gate_modelsim.xrf b/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/AND2Gate_modelsim.xrf
deleted file mode 100644
index 2054b3c..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/AND2Gate_modelsim.xrf
+++ /dev/null
@@ -1,12 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/db/AND2Gate.cbx.xml
-design_name = AND2Gate
-instance = comp, \outPort~output\, outPort~output, AND2Gate, 1
-instance = comp, \inPort0~input\, inPort0~input, AND2Gate, 1
-instance = comp, \inPort1~input\, inPort1~input, AND2Gate, 1
-instance = comp, \outPort~0\, outPort~0, AND2Gate, 1
diff --git a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/VHDLDemo.do b/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/VHDLDemo.do
deleted file mode 100644
index b70c8df..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/VHDLDemo.do
+++ /dev/null
@@ -1,17 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vcom -work work AND2Gate.vho
-vcom -work work AND2Gate.vwf.vht
-vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.AND2Gate_vhd_vec_tst
-vcd file -direction VHDLDemo.msim.vcd
-vcd add -internal AND2Gate_vhd_vec_tst/*
-vcd add -internal AND2Gate_vhd_vec_tst/i1/*
-proc simTimestamp {} {
- echo "Simulation time: $::now ps"
- if { [string equal running [runStatus]] } {
- after 2500 simTimestamp
- }
-}
-after 2500 simTimestamp
-run -all
-quit -f
diff --git a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/VHDLDemo.msim.vcd b/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/VHDLDemo.msim.vcd
deleted file mode 100644
index 4b2a987..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/VHDLDemo.msim.vcd
+++ /dev/null
@@ -1,126 +0,0 @@
-$comment
- File created using the following command:
- vcd file VHDLDemo.msim.vcd -direction
-$end
-$date
- Sat Feb 18 15:33:50 2023
-$end
-$version
- ModelSim Version 2020.1
-$end
-$timescale
- 1ps
-$end
-
-$scope module and2gate_vhd_vec_tst $end
-$var wire 1 ! inPort0 $end
-$var wire 1 " inPort1 $end
-$var wire 1 # outPort $end
-
-$scope module i1 $end
-$var wire 1 $ gnd $end
-$var wire 1 % vcc $end
-$var wire 1 & unknown $end
-$var wire 1 ' devoe $end
-$var wire 1 ( devclrn $end
-$var wire 1 ) devpor $end
-$var wire 1 * ww_devoe $end
-$var wire 1 + ww_devclrn $end
-$var wire 1 , ww_devpor $end
-$var wire 1 - ww_inPort0 $end
-$var wire 1 . ww_inPort1 $end
-$var wire 1 / ww_outPort $end
-$var wire 1 0 \outPort~output_o\ $end
-$var wire 1 1 \inPort0~input_o\ $end
-$var wire 1 2 \inPort1~input_o\ $end
-$var wire 1 3 \outPort~0_combout\ $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0!
-0"
-0#
-0$
-1%
-x&
-1'
-1(
-1)
-1*
-1+
-1,
-0-
-0.
-0/
-00
-01
-02
-03
-$end
-#40000
-1!
-1-
-11
-#220000
-0!
-0-
-01
-#280000
-1"
-1.
-12
-#360000
-0"
-0.
-02
-#440000
-1!
-1-
-11
-#500000
-1"
-1.
-12
-13
-10
-1/
-1#
-#620000
-0"
-0.
-02
-03
-00
-0/
-0#
-#660000
-0!
-0-
-01
-#720000
-1"
-1.
-12
-#780000
-1!
-1-
-11
-13
-10
-1/
-1#
-#900000
-0!
-0-
-01
-03
-00
-0/
-0#
-#940000
-0"
-0.
-02
-#1000000
diff --git a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/VHDLDemo_20230218153350.sim.vwf b/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/VHDLDemo_20230218153350.sim.vwf
deleted file mode 100644
index b50f83b..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/VHDLDemo_20230218153350.sim.vwf
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("inPort0")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("inPort1")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("outPort")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-TRANSITION_LIST("inPort0")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 180.0;
- LEVEL 0 FOR 220.0;
- LEVEL 1 FOR 220.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 100.0;
- }
- }
-}
-
-TRANSITION_LIST("inPort1")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 280.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 140.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 220.0;
- LEVEL 0 FOR 60.0;
- }
- }
-}
-
-TRANSITION_LIST("outPort")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 500.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 160.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 100.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "inPort0";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "inPort1";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outPort";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/transcript
deleted file mode 100644
index 88a6e06..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/transcript
+++ /dev/null
@@ -1,44 +0,0 @@
-# do VHDLDemo.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 15:33:50 on Feb 18,2023
-# vcom -work work AND2Gate.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity AND2Gate
-# -- Compiling architecture structure of AND2Gate
-# End time: 15:33:50 on Feb 18,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 15:33:50 on Feb 18,2023
-# vcom -work work AND2Gate.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity AND2Gate_vhd_vec_tst
-# -- Compiling architecture AND2Gate_arch of AND2Gate_vhd_vec_tst
-# End time: 15:33:50 on Feb 18,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.AND2Gate_vhd_vec_tst
-# Start time: 15:33:50 on Feb 18,2023
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading work.and2gate_vhd_vec_tst(and2gate_arch)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading cycloneive.cycloneive_atom_pack(body)
-# Loading cycloneive.cycloneive_components
-# Loading work.and2gate(structure)
-# Loading ieee.std_logic_arith(body)
-# Loading cycloneive.cycloneive_io_obuf(arch)
-# Loading cycloneive.cycloneive_io_ibuf(arch)
-# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#31
-# End time: 15:33:50 on Feb 18,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
diff --git a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/vwf_sim_transcript
deleted file mode 100644
index 58499a9..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/vwf_sim_transcript
+++ /dev/null
@@ -1,75 +0,0 @@
-Determining the location of the ModelSim executable...
-
-Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
-
-To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
-Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
-
-**** Generating the ModelSim Testbench ****
-
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off VHDLDemo -c AND2Gate --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim/AND2Gate.vwf.vht"
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Sat Feb 18 15:33:48 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off VHDLDemo -c AND2Gate --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim/AND2Gate.vwf.vhtInfo (119006): Selected device EP4CE115F29C7 for design "AND2Gate"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Completed successfully.
-
-**** Generating the functional simulation netlist ****
-
-quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim/" VHDLDemo -c AND2Gate
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Sat Feb 18 15:33:49 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim/ VHDLDemo -c AND2GateInfo (119006): Selected device EP4CE115F29C7 for design "AND2Gate"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file AND2Gate.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 615 megabytes Info: Processing ended: Sat Feb 18 15:33:49 2023 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00
-Completed successfully.
-
-**** Generating the ModelSim .do script ****
-
-/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim/VHDLDemo.do generated.
-
-Completed successfully.
-
-**** Running the ModelSim simulation ****
-
-/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do VHDLDemo.do
-
-Reading pref.tcl
-# 2020.1
-# do VHDLDemo.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 15:33:50 on Feb 18,2023# vcom -work work AND2Gate.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity AND2Gate
-# -- Compiling architecture structure of AND2Gate
-# End time: 15:33:50 on Feb 18,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020# Start time: 15:33:50 on Feb 18,2023
-# vcom -work work AND2Gate.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity AND2Gate_vhd_vec_tst# -- Compiling architecture AND2Gate_arch of AND2Gate_vhd_vec_tst
-# End time: 15:33:50 on Feb 18,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.AND2Gate_vhd_vec_tst # Start time: 15:33:50 on Feb 18,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.and2gate_vhd_vec_tst(and2gate_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.and2gate(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#31
-# End time: 15:33:50 on Feb 18,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-Completed successfully.
-
-**** Converting ModelSim VCD to vector waveform ****
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vwf...
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim/VHDLDemo.msim.vcd...
-
-Processing channel transitions...
-
-Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim/VHDLDemo_20230218153350.sim.vwf
-
-Finished VCD to VWF conversion.
-
-Completed successfully.
-
-All completed.
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/work/_info
deleted file mode 100644
index 8fb18ad..0000000
--- a/1ano/2semestre/lsd/pratica01/part2/simulation/qsim/work/_info
+++ /dev/null
@@ -1,101 +0,0 @@
-m255
-K4
-z2
-!s11e vcom 2020.1 2020.02, Feb 28 2020
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-Z0 d/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim
-Eand2gate
-Z1 w1676734429
-Z2 DPx4 ieee 16 vital_primitives 0 22 G>kiXP8Q9dRClKfK1Zn7j1
-Z3 DPx10 cycloneive 20 cycloneive_atom_pack 0 22 WOh:M[al;oVzG5c`D0
-Z4 DPx4 ieee 12 vital_timing 0 22 J>EBealN09f8GzldA[z2>3
-Z5 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
-Z6 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
-Z7 DPx10 cycloneive 21 cycloneive_components 0 22 zGMDhP>8e@2k@f0e
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.bpm b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.bpm
deleted file mode 100644
index c99508d..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.bpm and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.cdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.cdb
deleted file mode 100644
index 3976056..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.hdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.hdb
deleted file mode 100644
index 602aa34..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.idb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.idb
deleted file mode 100644
index fd425d3..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.idb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.logdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.logdb
deleted file mode 100644
index f766588..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.logdb
+++ /dev/null
@@ -1,120 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,22 I/O(s) were assigned a toggle rate,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,22 I/O(s) were assigned a toggle rate,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;8;8;0;0;78;8;0;0;0;0;0;0;6;0;0;0;72;6;0;72;0;0;6;0;78;78;78;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,78;70;70;78;78;0;70;78;78;78;78;78;78;72;78;78;78;6;72;78;6;78;78;72;78;0;0;0;78;78,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,LEDR[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,AUD_ADCDAT,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CLOCK2_50,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CLOCK3_50,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CLOCK_50,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_INT_N,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_LINK100,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_MDIO,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_COL,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_CRS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_DATA[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_DATA[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_DATA[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_DATA[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_DV,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_ER,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_TX_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_INT_N,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_LINK100,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_MDIO,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_COL,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_CRS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_DATA[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_DATA[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_DATA[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_DATA[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_DV,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_ER,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_TX_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENETCLK_25,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,FL_RY,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HSMC_CLKIN0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,IRDA_RXD,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,OTG_INT,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SD_WP_N,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SMA_CLKIN,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[16],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[17],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_CLK27,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_HS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_VS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,UART_RTS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,UART_RXD,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.rdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp.rdb
deleted file mode 100644
index 228af4e..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp_merge.kpt b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cmp_merge.kpt
deleted file mode 100644
index 1ed83fa..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index 6642b88..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
deleted file mode 100644
index e357492..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
deleted file mode 100644
index 19c469a..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.db_info b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.db_info
deleted file mode 100644
index 8785bc0..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Tue Mar 7 20:31:43 2023
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.eda.qmsg b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.eda.qmsg
deleted file mode 100644
index bb75cf7..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678221946677 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2020 Intel Corporation. All rights reserved. " "Copyright (C) 2020 Intel Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions " "Your use of Intel Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and any partner logic " "and other software and tools, and any partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License " "to the terms and conditions of the Intel Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel FPGA IP License Agreement, or other applicable license " "the Intel FPGA IP License Agreement, or other applicable license" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement, including, without limitation, that your use is for " "agreement, including, without limitation, that your use is for" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the sole purpose of programming logic devices manufactured by " "the sole purpose of programming logic devices manufactured by" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Intel and sold by Intel or its authorized distributors. Please " "Intel and sold by Intel or its authorized distributors. Please" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "refer to the applicable agreement for further details, at " "refer to the applicable agreement for further details, at" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "https://fpgasoftware.intel.com/eula. " "https://fpgasoftware.intel.com/eula." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:45:46 2023 " "Processing started: Tue Mar 7 20:45:46 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678221946677 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/ LogicDemo -c LogicTop " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/ LogicDemo -c LogicTop" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678221946677 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678221946861 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "LogicTop.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim// simulation " "Generated file LogicTop.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678221946897 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "613 " "Peak virtual memory: 613 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678221946911 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:45:46 2023 " "Processing ended: Tue Mar 7 20:45:46 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678221946911 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678221946911 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678221946911 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678221946911 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.fit.qmsg b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.fit.qmsg
deleted file mode 100644
index 91a03b2..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.fit.qmsg
+++ /dev/null
@@ -1,123 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678104312371 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678104312371 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "LogicTop EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"LogicTop\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678104312373 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678104312417 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678104312417 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678104312696 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678104312712 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678104312880 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678104312880 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678104312880 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678104312880 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678104312880 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678104312880 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678104312880 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678104312880 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678104312880 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678104312880 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "AUD_ADCDAT " "Can't reserve pin AUD_ADCDAT -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312885 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK2_50 " "Can't reserve pin CLOCK2_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312885 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK3_50 " "Can't reserve pin CLOCK3_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312885 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK_50 " "Can't reserve pin CLOCK_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312885 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_INT_N " "Can't reserve pin ENET0_INT_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312885 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_LINK100 " "Can't reserve pin ENET0_LINK100 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312885 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_MDIO " "Can't reserve pin ENET0_MDIO -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312885 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_CLK " "Can't reserve pin ENET0_RX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312885 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_COL " "Can't reserve pin ENET0_RX_COL -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312885 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_CRS " "Can't reserve pin ENET0_RX_CRS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312885 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[0\] " "Can't reserve pin ENET0_RX_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[1\] " "Can't reserve pin ENET0_RX_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[2\] " "Can't reserve pin ENET0_RX_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[3\] " "Can't reserve pin ENET0_RX_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DV " "Can't reserve pin ENET0_RX_DV -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_ER " "Can't reserve pin ENET0_RX_ER -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_TX_CLK " "Can't reserve pin ENET0_TX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_INT_N " "Can't reserve pin ENET1_INT_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_LINK100 " "Can't reserve pin ENET1_LINK100 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_MDIO " "Can't reserve pin ENET1_MDIO -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_CLK " "Can't reserve pin ENET1_RX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_COL " "Can't reserve pin ENET1_RX_COL -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_CRS " "Can't reserve pin ENET1_RX_CRS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[0\] " "Can't reserve pin ENET1_RX_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[1\] " "Can't reserve pin ENET1_RX_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[2\] " "Can't reserve pin ENET1_RX_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[3\] " "Can't reserve pin ENET1_RX_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DV " "Can't reserve pin ENET1_RX_DV -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_ER " "Can't reserve pin ENET1_RX_ER -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_TX_CLK " "Can't reserve pin ENET1_TX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENETCLK_25 " "Can't reserve pin ENETCLK_25 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "FL_RY " "Can't reserve pin FL_RY -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "HSMC_CLKIN0 " "Can't reserve pin HSMC_CLKIN0 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "IRDA_RXD " "Can't reserve pin IRDA_RXD -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[0\] " "Can't reserve pin KEY\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[1\] " "Can't reserve pin KEY\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[2\] " "Can't reserve pin KEY\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[3\] " "Can't reserve pin KEY\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "OTG_INT " "Can't reserve pin OTG_INT -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SD_WP_N " "Can't reserve pin SD_WP_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SMA_CLKIN " "Can't reserve pin SMA_CLKIN -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[0\] " "Can't reserve pin SW\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[0\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[0\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[0] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "LogicTop.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicTop.bdf" { { 208 264 432 224 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 13 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[10\] " "Can't reserve pin SW\[10\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[11\] " "Can't reserve pin SW\[11\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[12\] " "Can't reserve pin SW\[12\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[13\] " "Can't reserve pin SW\[13\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[14\] " "Can't reserve pin SW\[14\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[15\] " "Can't reserve pin SW\[15\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[16\] " "Can't reserve pin SW\[16\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[17\] " "Can't reserve pin SW\[17\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[1\] " "Can't reserve pin SW\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[1\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[1\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[1] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "LogicTop.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicTop.bdf" { { 208 264 432 224 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 12 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[2\] " "Can't reserve pin SW\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[3\] " "Can't reserve pin SW\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[4\] " "Can't reserve pin SW\[4\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[5\] " "Can't reserve pin SW\[5\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[6\] " "Can't reserve pin SW\[6\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[7\] " "Can't reserve pin SW\[7\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[8\] " "Can't reserve pin SW\[8\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[9\] " "Can't reserve pin SW\[9\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_CLK27 " "Can't reserve pin TD_CLK27 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[0\] " "Can't reserve pin TD_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[1\] " "Can't reserve pin TD_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[2\] " "Can't reserve pin TD_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[3\] " "Can't reserve pin TD_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[4\] " "Can't reserve pin TD_DATA\[4\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[5\] " "Can't reserve pin TD_DATA\[5\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[6\] " "Can't reserve pin TD_DATA\[6\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[7\] " "Can't reserve pin TD_DATA\[7\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_HS " "Can't reserve pin TD_HS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_VS " "Can't reserve pin TD_VS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "UART_RTS " "Can't reserve pin UART_RTS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "UART_RXD " "Can't reserve pin UART_RXD -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678104312886 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 653 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678104312887 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 655 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678104312887 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 657 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678104312887 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 659 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678104312887 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 661 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678104312887 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678104312887 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678104312896 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "LogicTop.sdc " "Synopsys Design Constraints File file not found: 'LogicTop.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678104313580 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678104313580 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678104313580 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678104313580 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678104313581 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678104313581 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678104313582 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678104313587 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678104313587 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678104313587 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678104313588 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678104313588 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678104313588 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678104313588 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678104313588 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678104313588 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678104313588 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678104313588 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678104313627 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678104313627 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678104313633 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678104313638 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678104315001 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678104315079 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678104315106 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678104315252 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678104315252 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678104315464 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X92_Y61 X103_Y73 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X92_Y61 to location X103_Y73" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X92_Y61 to location X103_Y73"} { { 12 { 0 ""} 92 61 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678104317333 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678104317333 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678104317425 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678104317425 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678104317425 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678104317426 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678104317496 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678104317500 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678104317662 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678104317662 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678104317800 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678104318020 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678104318189 ""}
-{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "25 Cyclone IV E " "25 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D2 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 14 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK2_50 3.3-V LVTTL AG14 " "Pin CLOCK2_50 uses I/O standard 3.3-V LVTTL at AG14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { CLOCK2_50 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 20 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK3_50 3.3-V LVTTL AG15 " "Pin CLOCK3_50 uses I/O standard 3.3-V LVTTL at AG15" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { CLOCK3_50 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 21 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENET0_LINK100 3.3-V LVTTL C14 " "Pin ENET0_LINK100 uses I/O standard 3.3-V LVTTL at C14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENET0_LINK100 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 88 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENET1_LINK100 3.3-V LVTTL D13 " "Pin ENET1_LINK100 uses I/O standard 3.3-V LVTTL at D13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENET1_LINK100 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 112 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENETCLK_25 3.3-V LVTTL A14 " "Pin ENETCLK_25 uses I/O standard 3.3-V LVTTL at A14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENETCLK_25 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 134 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "FL_RY 3.3-V LVTTL Y1 " "Pin FL_RY uses I/O standard 3.3-V LVTTL at Y1" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { FL_RY } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 179 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "HSMC_CLKIN0 3.3-V LVTTL AH15 " "Pin HSMC_CLKIN0 uses I/O standard 3.3-V LVTTL at AH15" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { HSMC_CLKIN0 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 283 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "IRDA_RXD 3.3-V LVTTL Y15 " "Pin IRDA_RXD uses I/O standard 3.3-V LVTTL at Y15" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { IRDA_RXD } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 372 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "OTG_INT 3.3-V LVTTL D5 " "Pin OTG_INT uses I/O standard 3.3-V LVTTL at D5" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { OTG_INT } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 437 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SD_WP_N 3.3-V LVTTL AF14 " "Pin SD_WP_N uses I/O standard 3.3-V LVTTL at AF14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SD_WP_N } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 452 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SMA_CLKIN 3.3-V LVTTL AH14 " "Pin SMA_CLKIN uses I/O standard 3.3-V LVTTL at AH14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SMA_CLKIN } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 453 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_CLK27 3.3-V LVTTL B14 " "Pin TD_CLK27 uses I/O standard 3.3-V LVTTL at B14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_CLK27 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 514 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[0\] 3.3-V LVTTL E8 " "Pin TD_DATA\[0\] uses I/O standard 3.3-V LVTTL at E8" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[0] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 516 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[1\] 3.3-V LVTTL A7 " "Pin TD_DATA\[1\] uses I/O standard 3.3-V LVTTL at A7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[1] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 517 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[2\] 3.3-V LVTTL D8 " "Pin TD_DATA\[2\] uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[2] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 518 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[3\] 3.3-V LVTTL C7 " "Pin TD_DATA\[3\] uses I/O standard 3.3-V LVTTL at C7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[3] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 519 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[4\] 3.3-V LVTTL D7 " "Pin TD_DATA\[4\] uses I/O standard 3.3-V LVTTL at D7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[4] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 520 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[5\] 3.3-V LVTTL D6 " "Pin TD_DATA\[5\] uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[5] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 521 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[6\] 3.3-V LVTTL E7 " "Pin TD_DATA\[6\] uses I/O standard 3.3-V LVTTL at E7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[6] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 522 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[7\] 3.3-V LVTTL F7 " "Pin TD_DATA\[7\] uses I/O standard 3.3-V LVTTL at F7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[7] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 523 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_HS 3.3-V LVTTL E5 " "Pin TD_HS uses I/O standard 3.3-V LVTTL at E5" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_HS } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 524 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_VS 3.3-V LVTTL E4 " "Pin TD_VS uses I/O standard 3.3-V LVTTL at E4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_VS } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 526 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART_RTS 3.3-V LVTTL J13 " "Pin UART_RTS uses I/O standard 3.3-V LVTTL at J13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { UART_RTS } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 528 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART_RXD 3.3-V LVTTL G12 " "Pin UART_RXD uses I/O standard 3.3-V LVTTL at G12" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { UART_RXD } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/" { { 0 { 0 ""} 0 529 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678104318191 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1678104318191 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678104318241 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 523 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 523 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1147 " "Peak virtual memory: 1147 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678104318387 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 6 12:05:18 2023 " "Processing ended: Mon Mar 6 12:05:18 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678104318387 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678104318387 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678104318387 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678104318387 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.hier_info b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.hier_info
deleted file mode 100644
index 8af8a57..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.hier_info
+++ /dev/null
@@ -1,31 +0,0 @@
-|LogicTop
-LEDR[0] <= LogicUnit:inst.invOut
-LEDR[1] <= LogicUnit:inst.andOut
-LEDR[2] <= LogicUnit:inst.orOut
-LEDR[3] <= LogicUnit:inst.xorOut
-LEDR[4] <= LogicUnit:inst.nandOut
-LEDR[5] <= LogicUnit:inst.norOut
-SW[0] => LogicUnit:inst.input0
-SW[1] => LogicUnit:inst.input1
-
-
-|LogicTop|LogicUnit:inst
-input0 => andOut.IN0
-input0 => orOut.IN0
-input0 => xorOut.IN0
-input0 => nandOut.IN0
-input0 => norOut.IN0
-input0 => invOut.DATAIN
-input1 => andOut.IN1
-input1 => orOut.IN1
-input1 => xorOut.IN1
-input1 => nandOut.IN1
-input1 => norOut.IN1
-invOut <= input0.DB_MAX_OUTPUT_PORT_TYPE
-andOut <= andOut.DB_MAX_OUTPUT_PORT_TYPE
-orOut <= orOut.DB_MAX_OUTPUT_PORT_TYPE
-xorOut <= xorOut.DB_MAX_OUTPUT_PORT_TYPE
-nandOut <= nandOut.DB_MAX_OUTPUT_PORT_TYPE
-norOut <= norOut.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.hif b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.hif
deleted file mode 100644
index e87e270..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.hif and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.lpc.html b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.lpc.html
deleted file mode 100644
index d49e17c..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.lpc.html
+++ /dev/null
@@ -1,34 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| inst |
-2 |
-0 |
-0 |
-0 |
-6 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.lpc.rdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.lpc.rdb
deleted file mode 100644
index fa1cd0c..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.lpc.txt b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.lpc.txt
deleted file mode 100644
index 635011c..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.lpc.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; inst ; 2 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.map.ammdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.map.ammdb
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.map.bpm b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.map.bpm
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.map.hdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.map.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.map.kpt b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.map.kpt
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.map.qmsg b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.map.qmsg
deleted file mode 100644
index 97d67e8..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.map.qmsg
+++ /dev/null
@@ -1,13 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678104305655 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678104305655 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 6 12:05:05 2023 " "Processing started: Mon Mar 6 12:05:05 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678104305655 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678104305655 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LogicDemo -c LogicTop " "Command: quartus_map --read_settings_files=on --write_settings_files=off LogicDemo -c LogicTop" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678104305655 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678104305778 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678104305778 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LogicUnit.vhd 2 1 " "Found 2 design units, including 1 entities, in source file LogicUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LogicUnit-Behavioral " "Found design unit 1: LogicUnit-Behavioral" { } { { "LogicUnit.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd" 18 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678104310607 ""} { "Info" "ISGN_ENTITY_NAME" "1 LogicUnit " "Found entity 1: LogicUnit" { } { { "LogicUnit.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678104310607 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678104310607 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LogicTop.bdf 1 1 " "Found 1 design units, including 1 entities, in source file LogicTop.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 LogicTop " "Found entity 1: LogicTop" { } { { "LogicTop.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicTop.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678104310613 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678104310613 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "LogicTop " "Elaborating entity \"LogicTop\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678104310669 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LogicUnit LogicUnit:inst " "Elaborating entity \"LogicUnit\" for hierarchy \"LogicUnit:inst\"" { } { { "LogicTop.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicTop.bdf" { { 184 440 600 328 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678104310675 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678104311128 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678104311464 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678104311464 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "11 " "Implemented 11 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678104311690 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678104311690 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3 " "Implemented 3 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678104311690 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678104311690 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "430 " "Peak virtual memory: 430 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678104311696 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 6 12:05:11 2023 " "Processing ended: Mon Mar 6 12:05:11 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678104311696 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678104311696 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678104311696 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678104311696 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.map.rdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.map.rdb
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.pre_map.hdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.root_partition.map.reg_db.cdb
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.routing.rdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.rtlv.hdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.sld_design_entry.sci b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.smart_action.txt b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.smart_action.txt
deleted file mode 100644
index 11b531f..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-SOURCE
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.sta.qmsg b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.sta.qmsg
deleted file mode 100644
index 1bb0c2f..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678104321448 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678104321448 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 6 12:05:21 2023 " "Processing started: Mon Mar 6 12:05:21 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678104321448 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678104321448 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta LogicDemo -c LogicTop " "Command: quartus_sta LogicDemo -c LogicTop" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678104321448 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678104321469 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678104321539 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678104321539 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678104321583 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678104321583 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "LogicTop.sdc " "Synopsys Design Constraints File file not found: 'LogicTop.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678104321869 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678104321869 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678104321870 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678104321870 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678104321870 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678104321870 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678104321870 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678104321874 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678104321874 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104321875 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104321878 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104321878 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104321878 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104321879 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104321879 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678104321880 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678104321894 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678104322121 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678104322134 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678104322134 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678104322134 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678104322135 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104322135 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104322135 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104322136 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104322136 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104322136 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104322137 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678104322138 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678104322177 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678104322177 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678104322177 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678104322178 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104322178 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104322179 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104322179 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104322179 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678104322180 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678104322384 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678104322384 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "540 " "Peak virtual memory: 540 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678104322394 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 6 12:05:22 2023 " "Processing ended: Mon Mar 6 12:05:22 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678104322394 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678104322394 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678104322394 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678104322394 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.sta.rdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.sta.rdb
deleted file mode 100644
index 518179f..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.sta.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.sta_cmp.7_slow_1200mv_85c.tdb
deleted file mode 100644
index f55646c..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.sta_cmp.7_slow_1200mv_85c.tdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tis_db_list.ddb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tis_db_list.ddb
deleted file mode 100644
index 73e5ec9..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tis_db_list.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index e6b70d6..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tiscmp.fast_1200mv_0c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index 7b6c5d8..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tiscmp.slow_1200mv_0c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index cdabb9b..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tmw_info b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tmw_info
deleted file mode 100644
index 1bd50f7..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tmw_info
+++ /dev/null
@@ -1,4 +0,0 @@
-start_full_compilation:s
-start_assembler:s-start_full_compilation
-start_timing_analyzer:s-start_full_compilation
-start_eda_netlist_writer:s-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.vpr.ammdb b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.vpr.ammdb
deleted file mode 100644
index 78083dd..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop_partition_pins.json b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop_partition_pins.json
deleted file mode 100644
index 8522f94..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop_partition_pins.json
+++ /dev/null
@@ -1,41 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "LEDR[5]",
- "strict" : false
- },
- {
- "name" : "LEDR[4]",
- "strict" : false
- },
- {
- "name" : "LEDR[3]",
- "strict" : false
- },
- {
- "name" : "LEDR[2]",
- "strict" : false
- },
- {
- "name" : "LEDR[1]",
- "strict" : false
- },
- {
- "name" : "LEDR[0]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part3/db/prev_cmp_LogicDemo.qmsg b/1ano/2semestre/lsd/pratica01/part3/db/prev_cmp_LogicDemo.qmsg
deleted file mode 100644
index 3d83801..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/db/prev_cmp_LogicDemo.qmsg
+++ /dev/null
@@ -1,4 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678103539913 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus Prime " "Running Quartus Prime Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678103539913 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 6 11:52:19 2023 " "Processing started: Mon Mar 6 11:52:19 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678103539913 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1678103539913 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LogicDemo -c LogicTop --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd " "Command: quartus_map --read_settings_files=on --write_settings_files=off LogicDemo -c LogicTop --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1678103539913 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus Prime " "Quartus Prime Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "692 " "Peak virtual memory: 692 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678103540336 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 6 11:52:20 2023 " "Processing ended: Mon Mar 6 11:52:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678103540336 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678103540336 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678103540336 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1678103540336 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/README b/1ano/2semestre/lsd/pratica01/part3/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.db_info b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.db_info
deleted file mode 100644
index 1148bd2..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Mon Mar 6 12:05:10 2023
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.ammdb
deleted file mode 100644
index e6969d2..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.cdb
deleted file mode 100644
index 976884b..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.dfp and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.hdb
deleted file mode 100644
index 81cab0f..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.rcfdb
deleted file mode 100644
index 1b6ffe0..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.cmp.rcfdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.cdb b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.cdb
deleted file mode 100644
index f2be99d..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.dpi b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.dpi
deleted file mode 100644
index 4253fa1..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.dpi and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hbdb.cdb
deleted file mode 100644
index 9391ed2..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hbdb.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hbdb.hdb
deleted file mode 100644
index 2281e17..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hdb b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hdb
deleted file mode 100644
index 49dc1aa..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.kpt b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.kpt
deleted file mode 100644
index 818fbaa..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.root_partition.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.rrp.hdb b/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.rrp.hdb
deleted file mode 100644
index b94b1b7..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part3/incremental_db/compiled_partitions/LogicTop.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.asm.rpt b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.asm.rpt
deleted file mode 100644
index b4cb504..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for LogicTop
-Mon Mar 6 12:05:20 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: LogicTop.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Mon Mar 6 12:05:20 2023 ;
-; Revision Name ; LogicTop ;
-; Top-level Entity Name ; LogicTop ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+-----------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+-----------------------------------------------------------------------------------------------+
-; File Name ;
-+-----------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.sof ;
-+-----------------------------------------------------------------------------------------------+
-
-
-+----------------------------------------+
-; Assembler Device Options: LogicTop.sof ;
-+----------------+-----------------------+
-; Option ; Setting ;
-+----------------+-----------------------+
-; JTAG usercode ; 0x005631BE ;
-; Checksum ; 0x005631BE ;
-+----------------+-----------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Mon Mar 6 12:05:19 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off LogicDemo -c LogicTop
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 366 megabytes
- Info: Processing ended: Mon Mar 6 12:05:20 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.done b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.done
deleted file mode 100644
index d8fd9f5..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.done
+++ /dev/null
@@ -1 +0,0 @@
-Mon Mar 6 12:05:23 2023
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.eda.rpt b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.eda.rpt
deleted file mode 100644
index c5b2604..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.eda.rpt
+++ /dev/null
@@ -1,108 +0,0 @@
-EDA Netlist Writer report for LogicTop
-Tue Mar 7 20:45:46 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Tue Mar 7 20:45:46 2023 ;
-; Revision Name ; LogicTop ;
-; Top-level Entity Name ; LogicTop ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+---------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+---------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim//LogicTop.vho ;
-+---------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
- Info: Your use of Intel Corporation's design tools, logic functions
- Info: and other software and tools, and any partner logic
- Info: functions, and any output files from any of the foregoing
- Info: (including device programming or simulation files), and any
- Info: associated documentation or information are expressly subject
- Info: to the terms and conditions of the Intel Program License
- Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
- Info: the Intel FPGA IP License Agreement, or other applicable license
- Info: agreement, including, without limitation, that your use is for
- Info: the sole purpose of programming logic devices manufactured by
- Info: Intel and sold by Intel or its authorized distributors. Please
- Info: refer to the applicable agreement for further details, at
- Info: https://fpgasoftware.intel.com/eula.
- Info: Processing started: Tue Mar 7 20:45:46 2023
-Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/ LogicDemo -c LogicTop
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file LogicTop.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim//" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 613 megabytes
- Info: Processing ended: Tue Mar 7 20:45:46 2023
- Info: Elapsed time: 00:00:00
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.fit.rpt b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.fit.rpt
deleted file mode 100644
index fe29627..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.fit.rpt
+++ /dev/null
@@ -1,3078 +0,0 @@
-Fitter report for LogicTop
-Mon Mar 6 12:05:18 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Mon Mar 6 12:05:18 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; LogicTop ;
-; Top-level Entity Name ; LogicTop ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 3 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 3 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 78 / 529 ( 15 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.2% ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+-------------------------+----------------+--------------+------------------+---------------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+-------------------------+----------------+--------------+------------------+---------------------+----------------+
-; Reserve Pin ; ; ; SW[0] ; AS INPUT TRI-STATED ; QSF Assignment ;
-; Reserve Pin ; ; ; SW[1] ; AS INPUT TRI-STATED ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
-; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
-; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
-; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
-; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
-; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
-; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[0] ; PIN_E21 ; QSF Assignment ;
-; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
-; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
-; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[6] ; PIN_J19 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_H19 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-; I/O Maximum Toggle Rate ; LogicTop ; ; HEX0 ; 0 MHz ; QSF Assignment ;
-; I/O Maximum Toggle Rate ; LogicTop ; ; HEX1 ; 0 MHz ; QSF Assignment ;
-; I/O Maximum Toggle Rate ; LogicTop ; ; HEX2 ; 0 MHz ; QSF Assignment ;
-; I/O Maximum Toggle Rate ; LogicTop ; ; HEX3[0] ; 0 MHz ; QSF Assignment ;
-; I/O Maximum Toggle Rate ; LogicTop ; ; HEX3[1] ; 0 MHz ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; AUD_ADCLRCK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; AUD_BCLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; AUD_DACDAT ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; AUD_DACLRCK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; AUD_XCK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_BA[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_BA[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_CAS_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_CKE ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_CLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_CS_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQM[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQM[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQM[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQM[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[13] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[14] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[15] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[16] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[17] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[18] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[19] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[20] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[21] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[22] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[23] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[24] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[25] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[26] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[27] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[28] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[29] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[30] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[31] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_DQ[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_RAS_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; DRAM_WE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; EEP_I2C_SCLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; EEP_I2C_SDAT ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET0_GTX_CLK ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET0_MDC ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET0_RST_N ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET0_TX_DATA[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET0_TX_DATA[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET0_TX_DATA[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET0_TX_DATA[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET0_TX_EN ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET0_TX_ER ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET1_GTX_CLK ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET1_MDC ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET1_RST_N ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET1_TX_DATA[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET1_TX_DATA[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET1_TX_DATA[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET1_TX_DATA[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET1_TX_EN ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; ENET1_TX_ER ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; EX_IO[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; EX_IO[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; EX_IO[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; EX_IO[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; EX_IO[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; EX_IO[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; EX_IO[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[13] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[14] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[15] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[16] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[17] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[18] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[19] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[20] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[21] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[22] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_CE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_OE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_RST_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_WE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; FL_WP_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[13] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[14] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[15] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[16] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[17] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[18] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[19] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[20] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[21] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[22] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[23] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[24] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[25] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[26] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[27] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[28] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[29] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[30] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[31] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[32] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[33] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[34] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[35] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; GPIO[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX0[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX0[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX0[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX0[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX0[4] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX0[5] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX0[6] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX1[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX1[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX1[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX1[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX1[4] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX1[5] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX1[6] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX2[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX2[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX2[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX2[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX2[4] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX2[5] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX2[6] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX3[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX3[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX3[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX3[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX3[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX3[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX3[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX4[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX4[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX4[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX4[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX4[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX4[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX4[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX5[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX5[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX5[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX5[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX5[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX5[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX5[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX6[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX6[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX6[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX6[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX6[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX6[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX6[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX7[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX7[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX7[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX7[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX7[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX7[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HEX7[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_CLKIN_N1 ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_CLKIN_N2 ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_CLKIN_P1 ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_CLKIN_P2 ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_CLKOUT0 ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_CLKOUT_N1 ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_CLKOUT_N2 ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_CLKOUT_P1 ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_CLKOUT_P2 ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_D[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_D[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_D[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_D[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[0] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[10] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[11] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[12] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[13] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[14] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[15] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[16] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[1] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[2] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[3] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[4] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[5] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[6] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[7] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[8] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_N[9] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[0] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[10] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[11] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[12] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[13] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[14] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[15] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[16] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[1] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[2] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[3] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[4] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[5] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[6] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[7] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[8] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_RX_D_P[9] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[0] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[10] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[11] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[12] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[13] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[14] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[15] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[16] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[1] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[2] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[3] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[4] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[5] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[6] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[7] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[8] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_N[9] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[0] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[10] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[11] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[12] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[13] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[14] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[15] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[16] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[1] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[2] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[3] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[4] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[5] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[6] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[7] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[8] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; HSMC_TX_D_P[9] ; LVDS ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; I2C_SCLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; I2C_SDAT ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LCD_BLON ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LCD_DATA[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LCD_DATA[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LCD_DATA[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LCD_DATA[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LCD_DATA[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LCD_DATA[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LCD_DATA[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LCD_DATA[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LCD_EN ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LCD_ON ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LCD_RS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LCD_RW ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDG[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDG[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDG[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDG[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDG[4] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDG[5] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDG[6] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDG[7] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDG[8] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDR[10] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDR[11] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDR[12] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDR[13] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDR[14] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDR[15] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDR[16] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDR[17] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDR[6] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDR[7] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDR[8] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; LEDR[9] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_CS_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[13] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[14] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[15] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DATA[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_DREQ[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_RD_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_RST_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; OTG_WR_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; PS2_CLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; PS2_CLK2 ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; PS2_DAT ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; PS2_DAT2 ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SD_CLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SD_CMD ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SD_DAT[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SD_DAT[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SD_DAT[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SD_DAT[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SMA_CLKOUT ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[13] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[14] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[15] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[16] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[17] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[18] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[19] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_CE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[13] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[14] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[15] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_DQ[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_LB_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_OE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_UB_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; SRAM_WE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; TD_RESET_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; UART_CTS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; UART_TXD ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_BLANK_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_B[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_B[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_B[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_B[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_B[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_B[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_B[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_B[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_CLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_G[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_G[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_G[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_G[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_G[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_G[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_G[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_G[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_HS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_R[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_R[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_R[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_R[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_R[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_R[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_R[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_R[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_SYNC_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; LogicTop ; ; VGA_VS ; 3.3-V LVTTL ; QSF Assignment ;
-+-------------------------+----------------+--------------+------------------+---------------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 170 ) ; 0.00 % ( 0 / 170 ) ; 0.00 % ( 0 / 170 ) ;
-; -- Achieved ; 0.00 % ( 0 / 170 ) ; 0.00 % ( 0 / 170 ) ; 0.00 % ( 0 / 170 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+--------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 20 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 150 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+-----------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-----------------------+
-; Total logic elements ; 3 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 3 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 0 ;
-; -- <=2 input functions ; 3 ;
-; -- Register only ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 3 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers* ; 0 / 117,053 ( 0 % ) ;
-; -- Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 1 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 78 / 529 ( 15 % ) ;
-; -- Clock pins ; 5 / 7 ( 71 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ;
-; Maximum fan-out ; 4 ;
-; Highest non-global fan-out ; 4 ;
-; Total fan-out ; 95 ;
-; Average fan-out ; 0.56 ;
-+---------------------------------------------+-----------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 3 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 3 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 0 ; 0 ;
-; -- 3 input functions ; 0 ; 0 ;
-; -- <=2 input functions ; 3 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 3 ; 0 ;
-; -- arithmetic mode ; 0 ; 0 ;
-; ; ; ;
-; Total registers ; 0 ; 0 ;
-; -- Dedicated logic registers ; 0 / 114480 ( 0 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 1 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 8 ; 70 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 20 ; 75 ;
-; -- Registered Connections ; 0 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 2 ; 0 ;
-; -- Output Ports ; 6 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+----------------------+--------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; AUD_ADCDAT ; D2 ; 1 ; 0 ; 68 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; CLOCK2_50 ; AG14 ; 3 ; 58 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; CLOCK3_50 ; AG15 ; 4 ; 58 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; CLOCK_50 ; Y2 ; 2 ; 0 ; 36 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_INT_N ; A21 ; 7 ; 89 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_LINK100 ; C14 ; 8 ; 52 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; ENET0_MDIO ; B21 ; 7 ; 87 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_CLK ; A15 ; 7 ; 56 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_COL ; E15 ; 7 ; 58 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_CRS ; D15 ; 7 ; 58 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_DATA[0] ; C16 ; 7 ; 62 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_DATA[1] ; D16 ; 7 ; 62 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_DATA[2] ; D17 ; 7 ; 81 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_DATA[3] ; C15 ; 7 ; 58 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_DV ; C17 ; 7 ; 81 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_ER ; D18 ; 7 ; 85 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_TX_CLK ; B17 ; 7 ; 60 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_INT_N ; D24 ; 7 ; 98 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_LINK100 ; D13 ; 8 ; 54 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; ENET1_MDIO ; D25 ; 7 ; 105 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_CLK ; B15 ; 7 ; 56 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_COL ; B22 ; 7 ; 89 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_CRS ; D20 ; 7 ; 85 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_DATA[0] ; B23 ; 7 ; 102 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_DATA[1] ; C21 ; 7 ; 91 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_DATA[2] ; A23 ; 7 ; 102 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_DATA[3] ; D21 ; 7 ; 96 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_DV ; A22 ; 7 ; 89 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_ER ; C24 ; 7 ; 98 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_TX_CLK ; C22 ; 7 ; 96 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENETCLK_25 ; A14 ; 8 ; 56 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; FL_RY ; Y1 ; 2 ; 0 ; 36 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; HSMC_CLKIN0 ; AH15 ; 4 ; 58 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; IRDA_RXD ; Y15 ; 3 ; 56 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; KEY[0] ; M23 ; 6 ; 115 ; 40 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; KEY[1] ; M21 ; 6 ; 115 ; 53 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; KEY[2] ; N21 ; 6 ; 115 ; 42 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; KEY[3] ; R24 ; 5 ; 115 ; 35 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; OTG_INT ; D5 ; 8 ; 3 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; SD_WP_N ; AF14 ; 3 ; 49 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; SMA_CLKIN ; AH14 ; 3 ; 58 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[10] ; AC24 ; 5 ; 115 ; 4 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[11] ; AB24 ; 5 ; 115 ; 5 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[12] ; AB23 ; 5 ; 115 ; 7 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[13] ; AA24 ; 5 ; 115 ; 9 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[14] ; AA23 ; 5 ; 115 ; 10 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[15] ; AA22 ; 5 ; 115 ; 6 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[16] ; Y24 ; 5 ; 115 ; 13 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[17] ; Y23 ; 5 ; 115 ; 14 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[3] ; AD27 ; 5 ; 115 ; 13 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[4] ; AB27 ; 5 ; 115 ; 18 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[5] ; AC26 ; 5 ; 115 ; 11 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[6] ; AD26 ; 5 ; 115 ; 10 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[7] ; AB26 ; 5 ; 115 ; 15 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[8] ; AC25 ; 5 ; 115 ; 4 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[9] ; AB25 ; 5 ; 115 ; 16 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; TD_CLK27 ; B14 ; 8 ; 56 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[0] ; E8 ; 8 ; 11 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[1] ; A7 ; 8 ; 29 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[2] ; D8 ; 8 ; 16 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[3] ; C7 ; 8 ; 16 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[4] ; D7 ; 8 ; 13 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[5] ; D6 ; 8 ; 13 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[6] ; E7 ; 8 ; 13 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[7] ; F7 ; 8 ; 9 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_HS ; E5 ; 8 ; 1 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_VS ; E4 ; 8 ; 1 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; UART_RTS ; J13 ; 8 ; 40 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; UART_RXD ; G12 ; 8 ; 27 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-+------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[2] ; E19 ; 7 ; 94 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[3] ; F21 ; 7 ; 107 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[4] ; F18 ; 7 ; 87 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[5] ; E18 ; 7 ; 87 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-; B22 ; DIFFIO_T53p, PADD0 ; Use as regular IO ; ENET1_RX_COL ; Dual Purpose Pin ;
-; D18 ; DIFFIO_T50p, PADD2 ; Use as regular IO ; ENET0_RX_ER ; Dual Purpose Pin ;
-; C17 ; DIFFIO_T46n, PADD3 ; Use as regular IO ; ENET0_RX_DV ; Dual Purpose Pin ;
-; D17 ; DIFFIO_T46p, PADD4, DQS2T/CQ3T,DPCLK8 ; Use as regular IO ; ENET0_RX_DATA[2] ; Dual Purpose Pin ;
-; C16 ; DIFFIO_T36n, PADD9 ; Use as regular IO ; ENET0_RX_DATA[0] ; Dual Purpose Pin ;
-; D16 ; DIFFIO_T36p, PADD10 ; Use as regular IO ; ENET0_RX_DATA[1] ; Dual Purpose Pin ;
-; B17 ; DIFFIO_T35p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO ; ENET0_TX_CLK ; Dual Purpose Pin ;
-; C15 ; DIFFIO_T32n, PADD13 ; Use as regular IO ; ENET0_RX_DATA[3] ; Dual Purpose Pin ;
-; D15 ; DIFFIO_T32p, PADD14 ; Use as regular IO ; ENET0_RX_CRS ; Dual Purpose Pin ;
-; C7 ; DIFFIO_T9n, DATA10 ; Use as regular IO ; TD_DATA[3] ; Dual Purpose Pin ;
-; D7 ; DIFFIO_T9p, DATA11 ; Use as regular IO ; TD_DATA[4] ; Dual Purpose Pin ;
-+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1 ; 5 / 56 ( 9 % ) ; 3.3V ; -- ;
-; 2 ; 2 / 63 ( 3 % ) ; 2.5V ; -- ;
-; 3 ; 4 / 73 ( 5 % ) ; 3.3V ; -- ;
-; 4 ; 2 / 71 ( 3 % ) ; 3.3V ; -- ;
-; 5 ; 19 / 65 ( 29 % ) ; 2.5V ; -- ;
-; 6 ; 4 / 58 ( 7 % ) ; 2.5V ; -- ;
-; 7 ; 30 / 72 ( 42 % ) ; 2.5V ; -- ;
-; 8 ; 17 / 71 ( 24 % ) ; 3.3V ; -- ;
-+----------+------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; TD_DATA[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; ENETCLK_25 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; A15 ; 470 ; 7 ; ENET0_RX_CLK ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; ENET0_INT_N ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; A22 ; 423 ; 7 ; ENET1_RX_DV ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; A23 ; 412 ; 7 ; ENET1_RX_DATA[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; SW[15] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA23 ; 280 ; 5 ; SW[14] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA24 ; 279 ; 5 ; SW[13] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; SW[12] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB24 ; 274 ; 5 ; SW[11] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB25 ; 292 ; 5 ; SW[9] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB26 ; 291 ; 5 ; SW[7] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB27 ; 296 ; 5 ; SW[4] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; SW[10] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC25 ; 272 ; 5 ; SW[8] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC26 ; 282 ; 5 ; SW[5] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; SW[6] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD27 ; 286 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; SD_WP_N ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; CLOCK2_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AG15 ; 201 ; 4 ; CLOCK3_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; SMA_CLKIN ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AH15 ; 202 ; 4 ; HSMC_CLKIN0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; TD_CLK27 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; B15 ; 471 ; 7 ; ENET1_RX_CLK ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; ENET0_TX_CLK ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; ENET0_MDIO ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; B22 ; 424 ; 7 ; ENET1_RX_COL ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; B23 ; 413 ; 7 ; ENET1_RX_DATA[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; TD_DATA[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; ENET0_LINK100 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; C15 ; 468 ; 7 ; ENET0_RX_DATA[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; C16 ; 460 ; 7 ; ENET0_RX_DATA[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; C17 ; 438 ; 7 ; ENET0_RX_DV ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; ENET1_RX_DATA[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; C22 ; 418 ; 7 ; ENET1_TX_CLK ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; ENET1_RX_ER ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; AUD_ADCDAT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; OTG_INT ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; D6 ; 524 ; 8 ; TD_DATA[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; D7 ; 522 ; 8 ; TD_DATA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; D8 ; 520 ; 8 ; TD_DATA[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; ENET1_LINK100 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; ENET0_RX_CRS ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D16 ; 461 ; 7 ; ENET0_RX_DATA[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D17 ; 439 ; 7 ; ENET0_RX_DATA[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D18 ; 430 ; 7 ; ENET0_RX_ER ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; ENET1_RX_CRS ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D21 ; 419 ; 7 ; ENET1_RX_DATA[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; ENET1_INT_N ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D25 ; 410 ; 7 ; ENET1_MDIO ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; TD_VS ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; E5 ; 542 ; 8 ; TD_HS ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; TD_DATA[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; E8 ; 526 ; 8 ; TD_DATA[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; ENET0_RX_COL ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 427 ; 7 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E19 ; 421 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; TD_DATA[7] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; UART_RXD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; UART_RTS ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; KEY[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; KEY[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; KEY[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; FL_RY ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; Y2 ; 65 ; 2 ; CLOCK_50 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; IRDA_RXD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; SW[17] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y24 ; 287 ; 5 ; SW[16] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-------------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+--------------------------------------+
-; Pin Name ; Reason ;
-+----------+--------------------------------------+
-; LEDR[5] ; Missing drive strength and slew rate ;
-; LEDR[4] ; Missing drive strength and slew rate ;
-; LEDR[3] ; Missing drive strength and slew rate ;
-; LEDR[2] ; Missing drive strength and slew rate ;
-; LEDR[1] ; Missing drive strength and slew rate ;
-; LEDR[0] ; Missing drive strength and slew rate ;
-+----------+--------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------+-------------+--------------+
-; |LogicTop ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 78 ; 0 ; 3 (0) ; 0 (0) ; 0 (0) ; |LogicTop ; LogicTop ; work ;
-; |LogicUnit:inst| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |LogicTop|LogicUnit:inst ; LogicUnit ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-----------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[1] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+---------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+---------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+---------------------------------+-------------------+---------+
-; SW[1] ; ; ;
-; - LogicUnit:inst|norOut~0 ; 1 ; 6 ;
-; - LogicUnit:inst|nandOut~0 ; 1 ; 6 ;
-; - LogicUnit:inst|xorOut ; 1 ; 6 ;
-; SW[0] ; ; ;
-; - LogicUnit:inst|norOut~0 ; 0 ; 6 ;
-; - LogicUnit:inst|nandOut~0 ; 0 ; 6 ;
-; - LogicUnit:inst|xorOut ; 0 ; 6 ;
-; - LEDR[0]~output ; 0 ; 6 ;
-+---------------------------------+-------------------+---------+
-
-
-+-----------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+-----------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+-----------------------+
-; Block interconnects ; 8 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 8 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 7 / 209,544 ( < 1 % ) ;
-; Direct links ; 0 / 342,891 ( 0 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 0 / 119,088 ( 0 % ) ;
-; R24 interconnects ; 4 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 8 / 289,782 ( < 1 % ) ;
-+-----------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 3.00) ; Number of LABs (Total = 1) ;
-+--------------------------------------------+-----------------------------+
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-+--------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 3.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 3.00) ; Number of LABs (Total = 1) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 2.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+---------------------------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+---------------------------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; 22 I/O(s) were assigned a toggle rate ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; 22 I/O(s) were assigned a toggle rate ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+---------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 8 ; 8 ; 0 ; 0 ; 78 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 72 ; 6 ; 0 ; 72 ; 0 ; 0 ; 6 ; 0 ; 78 ; 78 ; 78 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 78 ; 70 ; 70 ; 78 ; 78 ; 0 ; 70 ; 78 ; 78 ; 78 ; 78 ; 78 ; 78 ; 72 ; 78 ; 78 ; 78 ; 6 ; 72 ; 78 ; 6 ; 78 ; 78 ; 72 ; 78 ; 0 ; 0 ; 0 ; 78 ; 78 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; LEDR[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; AUD_ADCDAT ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; CLOCK2_50 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; CLOCK3_50 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; CLOCK_50 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_INT_N ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_LINK100 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_MDIO ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_CLK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_COL ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_CRS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_DATA[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_DATA[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_DATA[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_DATA[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_DV ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_ER ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_TX_CLK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_INT_N ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_LINK100 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_MDIO ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_CLK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_COL ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_CRS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_DATA[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_DATA[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_DATA[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_DATA[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_DV ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_ER ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_TX_CLK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENETCLK_25 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; FL_RY ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HSMC_CLKIN0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; IRDA_RXD ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; OTG_INT ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SD_WP_N ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SMA_CLKIN ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[16] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[17] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_CLK27 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_HS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_VS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; UART_RTS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; UART_RXD ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "LogicTop"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Warning (169133): Can't reserve pin AUD_ADCDAT -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin CLOCK2_50 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin CLOCK3_50 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin CLOCK_50 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_INT_N -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_LINK100 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_MDIO -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_CLK -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_COL -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_CRS -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_DATA[0] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_DATA[1] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_DATA[2] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_DATA[3] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_DV -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_ER -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_TX_CLK -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_INT_N -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_LINK100 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_MDIO -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_CLK -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_COL -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_CRS -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_DATA[0] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_DATA[1] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_DATA[2] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_DATA[3] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_DV -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_ER -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_TX_CLK -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENETCLK_25 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin FL_RY -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin HSMC_CLKIN0 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin IRDA_RXD -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin KEY[0] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin KEY[1] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin KEY[2] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin KEY[3] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin OTG_INT -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SD_WP_N -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SMA_CLKIN -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[0] -- pin name is an illegal or unsupported format
-Warning (169140): Reserve pin assignment ignored because of existing pin with name "SW[0]"
-Warning (169133): Can't reserve pin SW[10] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[11] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[12] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[13] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[14] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[15] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[16] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[17] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[1] -- pin name is an illegal or unsupported format
-Warning (169140): Reserve pin assignment ignored because of existing pin with name "SW[1]"
-Warning (169133): Can't reserve pin SW[2] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[3] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[4] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[5] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[6] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[7] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[8] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[9] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_CLK27 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[0] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[1] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[2] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[3] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[4] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[5] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[6] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[7] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_HS -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_VS -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin UART_RTS -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin UART_RXD -- pin name is an illegal or unsupported format
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'LogicTop.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X92_Y61 to location X103_Y73
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Warning (169177): 25 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
- Info (169178): Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D2
- Info (169178): Pin CLOCK2_50 uses I/O standard 3.3-V LVTTL at AG14
- Info (169178): Pin CLOCK3_50 uses I/O standard 3.3-V LVTTL at AG15
- Info (169178): Pin ENET0_LINK100 uses I/O standard 3.3-V LVTTL at C14
- Info (169178): Pin ENET1_LINK100 uses I/O standard 3.3-V LVTTL at D13
- Info (169178): Pin ENETCLK_25 uses I/O standard 3.3-V LVTTL at A14
- Info (169178): Pin FL_RY uses I/O standard 3.3-V LVTTL at Y1
- Info (169178): Pin HSMC_CLKIN0 uses I/O standard 3.3-V LVTTL at AH15
- Info (169178): Pin IRDA_RXD uses I/O standard 3.3-V LVTTL at Y15
- Info (169178): Pin OTG_INT uses I/O standard 3.3-V LVTTL at D5
- Info (169178): Pin SD_WP_N uses I/O standard 3.3-V LVTTL at AF14
- Info (169178): Pin SMA_CLKIN uses I/O standard 3.3-V LVTTL at AH14
- Info (169178): Pin TD_CLK27 uses I/O standard 3.3-V LVTTL at B14
- Info (169178): Pin TD_DATA[0] uses I/O standard 3.3-V LVTTL at E8
- Info (169178): Pin TD_DATA[1] uses I/O standard 3.3-V LVTTL at A7
- Info (169178): Pin TD_DATA[2] uses I/O standard 3.3-V LVTTL at D8
- Info (169178): Pin TD_DATA[3] uses I/O standard 3.3-V LVTTL at C7
- Info (169178): Pin TD_DATA[4] uses I/O standard 3.3-V LVTTL at D7
- Info (169178): Pin TD_DATA[5] uses I/O standard 3.3-V LVTTL at D6
- Info (169178): Pin TD_DATA[6] uses I/O standard 3.3-V LVTTL at E7
- Info (169178): Pin TD_DATA[7] uses I/O standard 3.3-V LVTTL at F7
- Info (169178): Pin TD_HS uses I/O standard 3.3-V LVTTL at E5
- Info (169178): Pin TD_VS uses I/O standard 3.3-V LVTTL at E4
- Info (169178): Pin UART_RTS uses I/O standard 3.3-V LVTTL at J13
- Info (169178): Pin UART_RXD uses I/O standard 3.3-V LVTTL at G12
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 523 warnings
- Info: Peak virtual memory: 1147 megabytes
- Info: Processing ended: Mon Mar 6 12:05:18 2023
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:09
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.fit.smsg b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.fit.summary b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.fit.summary
deleted file mode 100644
index 0085205..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Mon Mar 6 12:05:18 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : LogicTop
-Top-level Entity Name : LogicTop
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 3 / 114,480 ( < 1 % )
- Total combinational functions : 3 / 114,480 ( < 1 % )
- Dedicated logic registers : 0 / 114,480 ( 0 % )
-Total registers : 0
-Total pins : 78 / 529 ( 15 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.flow.rpt b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.flow.rpt
deleted file mode 100644
index 213bbbd..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.flow.rpt
+++ /dev/null
@@ -1,140 +0,0 @@
-Flow report for LogicTop
-Tue Mar 7 20:45:46 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Tue Mar 7 20:45:46 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; LogicTop ;
-; Top-level Entity Name ; LogicTop ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 3 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 3 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 78 / 529 ( 15 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/06/2023 12:05:05 ;
-; Main task ; Compilation ;
-; Revision Name ; LogicTop ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 198516037997543.167810430507620 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 430 MB ; 00:00:13 ;
-; Fitter ; 00:00:06 ; 1.0 ; 1147 MB ; 00:00:09 ;
-; Assembler ; 00:00:01 ; 1.0 ; 366 MB ; 00:00:02 ;
-; Timing Analyzer ; 00:00:01 ; 1.0 ; 540 MB ; 00:00:01 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 612 MB ; 00:00:00 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 609 MB ; 00:00:00 ;
-; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 613 MB ; 00:00:00 ;
-; Total ; 00:00:16 ; -- ; -- ; 00:00:25 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off LogicDemo -c LogicTop
-quartus_fit --read_settings_files=off --write_settings_files=off LogicDemo -c LogicTop
-quartus_asm --read_settings_files=off --write_settings_files=off LogicDemo -c LogicTop
-quartus_sta LogicDemo -c LogicTop
-quartus_eda --read_settings_files=off --write_settings_files=off LogicDemo -c LogicTop
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht
-quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/ LogicDemo -c LogicTop
-
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.jdi b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.jdi
deleted file mode 100644
index 40ede88..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.map.rpt b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.map.rpt
deleted file mode 100644
index 29564c4..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.map.rpt
+++ /dev/null
@@ -1,288 +0,0 @@
-Analysis & Synthesis report for LogicTop
-Mon Mar 6 12:05:11 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Post-Synthesis Netlist Statistics for Top Partition
- 10. Elapsed Time Per Partition
- 11. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Mon Mar 6 12:05:11 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; LogicTop ;
-; Top-level Entity Name ; LogicTop ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 3 ;
-; Total combinational functions ; 3 ;
-; Dedicated logic registers ; 0 ;
-; Total registers ; 0 ;
-; Total pins ; 8 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; LogicTop ; LogicTop ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
-; LogicUnit.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd ; ;
-; LogicTop.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicTop.bdf ; ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
-
-
-+-----------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+-------------+
-; Resource ; Usage ;
-+---------------------------------------------+-------------+
-; Estimated Total logic elements ; 3 ;
-; ; ;
-; Total combinational functions ; 3 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 0 ;
-; -- <=2 input functions ; 3 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 3 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers ; 0 ;
-; -- Dedicated logic registers ; 0 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 8 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; SW[0]~input ;
-; Maximum fan-out ; 4 ;
-; Total fan-out ; 20 ;
-; Average fan-out ; 1.05 ;
-+---------------------------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+-------------+--------------+
-; |LogicTop ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; |LogicTop ; LogicTop ; work ;
-; |LogicUnit:inst| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |LogicTop|LogicUnit:inst ; LogicUnit ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 0 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 8 ;
-; cycloneiii_lcell_comb ; 6 ;
-; normal ; 6 ;
-; 1 data inputs ; 3 ;
-; 2 data inputs ; 3 ;
-; ; ;
-; Max LUT depth ; 2.00 ;
-; Average LUT depth ; 1.75 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Mon Mar 6 12:05:05 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LogicDemo -c LogicTop
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 2 design units, including 1 entities, in source file LogicUnit.vhd
- Info (12022): Found design unit 1: LogicUnit-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd Line: 18
- Info (12023): Found entity 1: LogicUnit File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd Line: 4
-Info (12021): Found 1 design units, including 1 entities, in source file LogicTop.bdf
- Info (12023): Found entity 1: LogicTop
-Info (12127): Elaborating entity "LogicTop" for the top level hierarchy
-Info (12128): Elaborating entity "LogicUnit" for hierarchy "LogicUnit:inst"
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 11 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 2 input pins
- Info (21059): Implemented 6 output pins
- Info (21061): Implemented 3 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 430 megabytes
- Info: Processing ended: Mon Mar 6 12:05:11 2023
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:13
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.map.summary b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.map.summary
deleted file mode 100644
index e86260d..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Mon Mar 6 12:05:11 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : LogicTop
-Top-level Entity Name : LogicTop
-Family : Cyclone IV E
-Total logic elements : 3
- Total combinational functions : 3
- Dedicated logic registers : 0
-Total registers : 0
-Total pins : 8
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.pin b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.pin
deleted file mode 100644
index 1620335..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 3.3V
- -- Bank 2: 2.5V
- -- Bank 3: 3.3V
- -- Bank 4: 3.3V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 3.3V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "LogicTop" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 3.3V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 3.3V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-TD_DATA[1] : A7 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 3.3V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 3.3V : 8 :
-ENETCLK_25 : A14 : input : 3.3-V LVTTL : : 8 : Y
-ENET0_RX_CLK : A15 : input : 2.5 V : : 7 : Y
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-ENET0_INT_N : A21 : input : 2.5 V : : 7 : Y
-ENET1_RX_DV : A22 : input : 2.5 V : : 7 : Y
-ENET1_RX_DATA[2] : A23 : input : 2.5 V : : 7 : Y
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-SW[15] : AA22 : input : 2.5 V : : 5 : Y
-SW[14] : AA23 : input : 2.5 V : : 5 : Y
-SW[13] : AA24 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-SW[12] : AB23 : input : 2.5 V : : 5 : Y
-SW[11] : AB24 : input : 2.5 V : : 5 : Y
-SW[9] : AB25 : input : 2.5 V : : 5 : Y
-SW[7] : AB26 : input : 2.5 V : : 5 : Y
-SW[4] : AB27 : input : 2.5 V : : 5 : Y
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-SW[10] : AC24 : input : 2.5 V : : 5 : Y
-SW[8] : AC25 : input : 2.5 V : : 5 : Y
-SW[5] : AC26 : input : 2.5 V : : 5 : Y
-SW[2] : AC27 : input : 2.5 V : : 5 : Y
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-SW[6] : AD26 : input : 2.5 V : : 5 : Y
-SW[3] : AD27 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-SD_WP_N : AF14 : input : 3.3-V LVTTL : : 3 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-CLOCK2_50 : AG14 : input : 3.3-V LVTTL : : 3 : Y
-CLOCK3_50 : AG15 : input : 3.3-V LVTTL : : 4 : Y
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 3.3V : 3 :
-SMA_CLKIN : AH14 : input : 3.3-V LVTTL : : 3 : Y
-HSMC_CLKIN0 : AH15 : input : 3.3-V LVTTL : : 4 : Y
-VCCIO4 : AH16 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 3.3V : 4 :
-VCCIO1 : B1 : power : : 3.3V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-TD_CLK27 : B14 : input : 3.3-V LVTTL : : 8 : Y
-ENET1_RX_CLK : B15 : input : 2.5 V : : 7 : Y
-GND : B16 : gnd : : : :
-ENET0_TX_CLK : B17 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-ENET0_MDIO : B21 : input : 2.5 V : : 7 : Y
-ENET1_RX_COL : B22 : input : 2.5 V : : 7 : Y
-ENET1_RX_DATA[0] : B23 : input : 2.5 V : : 7 : Y
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-TD_DATA[3] : C7 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-ENET0_LINK100 : C14 : input : 3.3-V LVTTL : : 8 : Y
-ENET0_RX_DATA[3] : C15 : input : 2.5 V : : 7 : Y
-ENET0_RX_DATA[0] : C16 : input : 2.5 V : : 7 : Y
-ENET0_RX_DV : C17 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-ENET1_RX_DATA[1] : C21 : input : 2.5 V : : 7 : Y
-ENET1_TX_CLK : C22 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-ENET1_RX_ER : C24 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-AUD_ADCDAT : D2 : input : 3.3-V LVTTL : : 1 : Y
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-OTG_INT : D5 : input : 3.3-V LVTTL : : 8 : Y
-TD_DATA[5] : D6 : input : 3.3-V LVTTL : : 8 : Y
-TD_DATA[4] : D7 : input : 3.3-V LVTTL : : 8 : Y
-TD_DATA[2] : D8 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-ENET1_LINK100 : D13 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-ENET0_RX_CRS : D15 : input : 2.5 V : : 7 : Y
-ENET0_RX_DATA[1] : D16 : input : 2.5 V : : 7 : Y
-ENET0_RX_DATA[2] : D17 : input : 2.5 V : : 7 : Y
-ENET0_RX_ER : D18 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-ENET1_RX_CRS : D20 : input : 2.5 V : : 7 : Y
-ENET1_RX_DATA[3] : D21 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-ENET1_INT_N : D24 : input : 2.5 V : : 7 : Y
-ENET1_MDIO : D25 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 3.3-V LVTTL : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-TD_VS : E4 : input : 3.3-V LVTTL : : 8 : Y
-TD_HS : E5 : input : 3.3-V LVTTL : : 8 : Y
-VCCIO8 : E6 : power : : 3.3V : 8 :
-TD_DATA[6] : E7 : input : 3.3-V LVTTL : : 8 : Y
-TD_DATA[0] : E8 : input : 3.3-V LVTTL : : 8 : Y
-VCCIO8 : E9 : power : : 3.3V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 3.3V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-ENET0_RX_COL : E15 : input : 2.5 V : : 7 : Y
-VCCIO7 : E16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
-LEDR[5] : E18 : output : 2.5 V : : 7 : Y
-LEDR[2] : E19 : output : 2.5 V : : 7 : Y
-VCCIO7 : E20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
-VCCIO7 : E23 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 3.3-V LVTTL : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-TD_DATA[7] : F7 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-LEDR[4] : F18 : output : 2.5 V : : 7 : Y
-LEDR[1] : F19 : output : 2.5 V : : 7 : Y
-GND : F20 : gnd : : : :
-LEDR[3] : F21 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-UART_RXD : G12 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
-LEDR[0] : G19 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 3.3V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 3.3V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
-VCCIO7 : H18 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-UART_RTS : J13 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7 :
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 3.3V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-KEY[1] : M21 : input : 2.5 V : : 6 : Y
-MSEL2 : M22 : : : : 6 :
-KEY[0] : M23 : input : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 3.3V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 3.3V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 3.3-V LVTTL : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-KEY[2] : N21 : input : 2.5 V : : 6 : Y
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 3.3-V LVTTL : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-KEY[3] : R24 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-FL_RY : Y1 : input : 3.3-V LVTTL : : 2 : Y
-CLOCK_50 : Y2 : input : 2.5 V : : 2 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-IRDA_RXD : Y15 : input : 3.3-V LVTTL : : 3 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-SW[17] : Y23 : input : 2.5 V : : 5 : Y
-SW[16] : Y24 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.sld b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.sta.rpt b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.sta.rpt
deleted file mode 100644
index f145861..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.sta.rpt
+++ /dev/null
@@ -1,531 +0,0 @@
-Timing Analyzer report for LogicTop
-Mon Mar 6 12:05:22 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Unconstrained Input Ports
- 37. Unconstrained Output Ports
- 38. Unconstrained Input Ports
- 39. Unconstrained Output Ports
- 40. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; LogicTop ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.1% ;
-+----------------------------+-------------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; AUD_ADCDAT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; CLOCK2_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; CLOCK3_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; CLOCK_50 ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_INT_N ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_LINK100 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; ENET0_MDIO ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_CLK ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_COL ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_CRS ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_DATA[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_DATA[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_DATA[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_DATA[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_DV ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_ER ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_TX_CLK ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_INT_N ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_LINK100 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; ENET1_MDIO ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_CLK ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_COL ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_CRS ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_DATA[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_DATA[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_DATA[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_DATA[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_DV ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_ER ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_TX_CLK ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENETCLK_25 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; FL_RY ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; HSMC_CLKIN0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; IRDA_RXD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; OTG_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; SD_WP_N ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; SMA_CLKIN ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; SW[10] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[11] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[12] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[13] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[14] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[15] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[16] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[17] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; TD_CLK27 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_HS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_VS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; UART_RTS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; UART_RXD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.73e-09 V ; 3.19 V ; -0.173 V ; 0.151 V ; 0.259 V ; 2.79e-10 s ; 2.42e-10 s ; Yes ; Yes ; 3.08 V ; 5.73e-09 V ; 3.19 V ; -0.173 V ; 0.151 V ; 0.259 V ; 2.79e-10 s ; 2.42e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 2 ; 2 ;
-; Unconstrained Input Port Paths ; 11 ; 11 ;
-; Unconstrained Output Ports ; 6 ; 6 ;
-; Unconstrained Output Port Paths ; 11 ; 11 ;
-+---------------------------------+-------+------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Mon Mar 6 12:05:21 2023
-Info: Command: quartus_sta LogicDemo -c LogicTop
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'LogicTop.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 540 megabytes
- Info: Processing ended: Mon Mar 6 12:05:22 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.sta.summary b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.sta.summary
deleted file mode 100644
index aa5b327..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/LogicTop.sft b/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/LogicTop.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/LogicTop.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/LogicTop.vho b/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/LogicTop.vho
deleted file mode 100644
index 5f0d5b7..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/LogicTop.vho
+++ /dev/null
@@ -1,493 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/06/2023 12:05:23"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- AUD_ADCDAT => Location: PIN_D2, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- CLOCK2_50 => Location: PIN_AG14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- CLOCK3_50 => Location: PIN_AG15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- CLOCK_50 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_INT_N => Location: PIN_A21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_LINK100 => Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ENET0_MDIO => Location: PIN_B21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_CLK => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_COL => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_CRS => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[0] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[1] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[2] => Location: PIN_D17, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[3] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DV => Location: PIN_C17, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_ER => Location: PIN_D18, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_TX_CLK => Location: PIN_B17, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_INT_N => Location: PIN_D24, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_LINK100 => Location: PIN_D13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ENET1_MDIO => Location: PIN_D25, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_CLK => Location: PIN_B15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_COL => Location: PIN_B22, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_CRS => Location: PIN_D20, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[0] => Location: PIN_B23, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[1] => Location: PIN_C21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[2] => Location: PIN_A23, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[3] => Location: PIN_D21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DV => Location: PIN_A22, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_ER => Location: PIN_C24, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_TX_CLK => Location: PIN_C22, I/O Standard: 2.5 V, Current Strength: Default
--- ENETCLK_25 => Location: PIN_A14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- FL_RY => Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- HSMC_CLKIN0 => Location: PIN_AH15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- IRDA_RXD => Location: PIN_Y15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[2] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[3] => Location: PIN_R24, I/O Standard: 2.5 V, Current Strength: Default
--- OTG_INT => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- SD_WP_N => Location: PIN_AF14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- SMA_CLKIN => Location: PIN_AH14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- SW[10] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[11] => Location: PIN_AB24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[12] => Location: PIN_AB23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[13] => Location: PIN_AA24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[14] => Location: PIN_AA23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[15] => Location: PIN_AA22, I/O Standard: 2.5 V, Current Strength: Default
--- SW[16] => Location: PIN_Y24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[17] => Location: PIN_Y23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default
--- SW[9] => Location: PIN_AB25, I/O Standard: 2.5 V, Current Strength: Default
--- TD_CLK27 => Location: PIN_B14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[0] => Location: PIN_E8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[1] => Location: PIN_A7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[2] => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[3] => Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[4] => Location: PIN_D7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[5] => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[6] => Location: PIN_E7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[7] => Location: PIN_F7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_HS => Location: PIN_E5, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_VS => Location: PIN_E4, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- UART_RTS => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- UART_RXD => Location: PIN_G12, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \AUD_ADCDAT~padout\ : std_logic;
-SIGNAL \CLOCK2_50~padout\ : std_logic;
-SIGNAL \CLOCK3_50~padout\ : std_logic;
-SIGNAL \CLOCK_50~padout\ : std_logic;
-SIGNAL \ENET0_INT_N~padout\ : std_logic;
-SIGNAL \ENET0_LINK100~padout\ : std_logic;
-SIGNAL \ENET0_MDIO~padout\ : std_logic;
-SIGNAL \ENET0_RX_CLK~padout\ : std_logic;
-SIGNAL \ENET0_RX_COL~padout\ : std_logic;
-SIGNAL \ENET0_RX_CRS~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[0]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[1]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[2]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[3]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DV~padout\ : std_logic;
-SIGNAL \ENET0_RX_ER~padout\ : std_logic;
-SIGNAL \ENET0_TX_CLK~padout\ : std_logic;
-SIGNAL \ENET1_INT_N~padout\ : std_logic;
-SIGNAL \ENET1_LINK100~padout\ : std_logic;
-SIGNAL \ENET1_MDIO~padout\ : std_logic;
-SIGNAL \ENET1_RX_CLK~padout\ : std_logic;
-SIGNAL \ENET1_RX_COL~padout\ : std_logic;
-SIGNAL \ENET1_RX_CRS~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[0]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[1]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[2]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[3]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DV~padout\ : std_logic;
-SIGNAL \ENET1_RX_ER~padout\ : std_logic;
-SIGNAL \ENET1_TX_CLK~padout\ : std_logic;
-SIGNAL \ENETCLK_25~padout\ : std_logic;
-SIGNAL \FL_RY~padout\ : std_logic;
-SIGNAL \HSMC_CLKIN0~padout\ : std_logic;
-SIGNAL \IRDA_RXD~padout\ : std_logic;
-SIGNAL \KEY[0]~padout\ : std_logic;
-SIGNAL \KEY[1]~padout\ : std_logic;
-SIGNAL \KEY[2]~padout\ : std_logic;
-SIGNAL \KEY[3]~padout\ : std_logic;
-SIGNAL \OTG_INT~padout\ : std_logic;
-SIGNAL \SD_WP_N~padout\ : std_logic;
-SIGNAL \SMA_CLKIN~padout\ : std_logic;
-SIGNAL \TD_CLK27~padout\ : std_logic;
-SIGNAL \TD_DATA[0]~padout\ : std_logic;
-SIGNAL \TD_DATA[1]~padout\ : std_logic;
-SIGNAL \TD_DATA[2]~padout\ : std_logic;
-SIGNAL \TD_DATA[3]~padout\ : std_logic;
-SIGNAL \TD_DATA[4]~padout\ : std_logic;
-SIGNAL \TD_DATA[5]~padout\ : std_logic;
-SIGNAL \TD_DATA[6]~padout\ : std_logic;
-SIGNAL \TD_DATA[7]~padout\ : std_logic;
-SIGNAL \TD_HS~padout\ : std_logic;
-SIGNAL \TD_VS~padout\ : std_logic;
-SIGNAL \UART_RTS~padout\ : std_logic;
-SIGNAL \UART_RXD~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \AUD_ADCDAT~ibuf_o\ : std_logic;
-SIGNAL \CLOCK2_50~ibuf_o\ : std_logic;
-SIGNAL \CLOCK3_50~ibuf_o\ : std_logic;
-SIGNAL \CLOCK_50~ibuf_o\ : std_logic;
-SIGNAL \ENET0_INT_N~ibuf_o\ : std_logic;
-SIGNAL \ENET0_LINK100~ibuf_o\ : std_logic;
-SIGNAL \ENET0_MDIO~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_COL~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_CRS~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[0]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[1]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[2]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[3]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DV~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_ER~ibuf_o\ : std_logic;
-SIGNAL \ENET0_TX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENET1_INT_N~ibuf_o\ : std_logic;
-SIGNAL \ENET1_LINK100~ibuf_o\ : std_logic;
-SIGNAL \ENET1_MDIO~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_COL~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_CRS~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[0]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[1]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[2]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[3]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DV~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_ER~ibuf_o\ : std_logic;
-SIGNAL \ENET1_TX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENETCLK_25~ibuf_o\ : std_logic;
-SIGNAL \FL_RY~ibuf_o\ : std_logic;
-SIGNAL \HSMC_CLKIN0~ibuf_o\ : std_logic;
-SIGNAL \IRDA_RXD~ibuf_o\ : std_logic;
-SIGNAL \KEY[0]~ibuf_o\ : std_logic;
-SIGNAL \KEY[1]~ibuf_o\ : std_logic;
-SIGNAL \KEY[2]~ibuf_o\ : std_logic;
-SIGNAL \KEY[3]~ibuf_o\ : std_logic;
-SIGNAL \OTG_INT~ibuf_o\ : std_logic;
-SIGNAL \SD_WP_N~ibuf_o\ : std_logic;
-SIGNAL \SMA_CLKIN~ibuf_o\ : std_logic;
-SIGNAL \SW[10]~ibuf_o\ : std_logic;
-SIGNAL \SW[11]~ibuf_o\ : std_logic;
-SIGNAL \SW[12]~ibuf_o\ : std_logic;
-SIGNAL \SW[13]~ibuf_o\ : std_logic;
-SIGNAL \SW[14]~ibuf_o\ : std_logic;
-SIGNAL \SW[15]~ibuf_o\ : std_logic;
-SIGNAL \SW[16]~ibuf_o\ : std_logic;
-SIGNAL \SW[17]~ibuf_o\ : std_logic;
-SIGNAL \SW[2]~ibuf_o\ : std_logic;
-SIGNAL \SW[3]~ibuf_o\ : std_logic;
-SIGNAL \SW[4]~ibuf_o\ : std_logic;
-SIGNAL \SW[5]~ibuf_o\ : std_logic;
-SIGNAL \SW[6]~ibuf_o\ : std_logic;
-SIGNAL \SW[7]~ibuf_o\ : std_logic;
-SIGNAL \SW[8]~ibuf_o\ : std_logic;
-SIGNAL \SW[9]~ibuf_o\ : std_logic;
-SIGNAL \TD_CLK27~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[0]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[1]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[2]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[3]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[4]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[5]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[6]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[7]~ibuf_o\ : std_logic;
-SIGNAL \TD_HS~ibuf_o\ : std_logic;
-SIGNAL \TD_VS~ibuf_o\ : std_logic;
-SIGNAL \UART_RTS~ibuf_o\ : std_logic;
-SIGNAL \UART_RXD~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-SIGNAL SW : std_logic_vector(1 DOWNTO 0);
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY LogicTop IS
- PORT (
- LEDR : OUT std_logic_vector(5 DOWNTO 0);
- SW : IN std_logic_vector(1 DOWNTO 0)
- );
-END LogicTop;
-
--- Design Ports Information
--- LEDR[5] => Location: PIN_E18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[4] => Location: PIN_F18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF LogicTop IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDR : std_logic_vector(5 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(1 DOWNTO 0);
-SIGNAL \LEDR[5]~output_o\ : std_logic;
-SIGNAL \LEDR[4]~output_o\ : std_logic;
-SIGNAL \LEDR[3]~output_o\ : std_logic;
-SIGNAL \LEDR[2]~output_o\ : std_logic;
-SIGNAL \LEDR[1]~output_o\ : std_logic;
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \inst|norOut~0_combout\ : std_logic;
-SIGNAL \inst|nandOut~0_combout\ : std_logic;
-SIGNAL \inst|xorOut~combout\ : std_logic;
-SIGNAL \ALT_INV_SW[0]~input_o\ : std_logic;
-SIGNAL \inst|ALT_INV_nandOut~0_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_norOut~0_combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-LEDR <= ww_LEDR;
-ww_SW <= SW;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\ALT_INV_SW[0]~input_o\ <= NOT \SW[0]~input_o\;
-\inst|ALT_INV_nandOut~0_combout\ <= NOT \inst|nandOut~0_combout\;
-\inst|ALT_INV_norOut~0_combout\ <= NOT \inst|norOut~0_combout\;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X87_Y73_N9
-\LEDR[5]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|ALT_INV_norOut~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[5]~output_o\);
-
--- Location: IOOBUF_X87_Y73_N16
-\LEDR[4]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|ALT_INV_nandOut~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[4]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N16
-\LEDR[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|xorOut~combout\,
- devoe => ww_devoe,
- o => \LEDR[3]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N9
-\LEDR[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|norOut~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[2]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N2
-\LEDR[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|nandOut~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[1]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N16
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \ALT_INV_SW[0]~input_o\,
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: LCCOMB_X95_Y72_N16
-\inst|norOut~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|norOut~0_combout\ = (\SW[1]~input_o\) # (\SW[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111111001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[1]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \inst|norOut~0_combout\);
-
--- Location: LCCOMB_X95_Y72_N10
-\inst|nandOut~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|nandOut~0_combout\ = (\SW[1]~input_o\ & \SW[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100110000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[1]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \inst|nandOut~0_combout\);
-
--- Location: LCCOMB_X95_Y72_N28
-\inst|xorOut\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|xorOut~combout\ = \SW[1]~input_o\ $ (\SW[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011001111001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[1]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \inst|xorOut~combout\);
-
-ww_LEDR(5) <= \LEDR[5]~output_o\;
-
-ww_LEDR(4) <= \LEDR[4]~output_o\;
-
-ww_LEDR(3) <= \LEDR[3]~output_o\;
-
-ww_LEDR(2) <= \LEDR[2]~output_o\;
-
-ww_LEDR(1) <= \LEDR[1]~output_o\;
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/LogicTop_modelsim.xrf b/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/LogicTop_modelsim.xrf
deleted file mode 100644
index 3930aec..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/LogicTop_modelsim.xrf
+++ /dev/null
@@ -1,21 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicTop.bdf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cbx.xml
-design_name = hard_block
-design_name = LogicTop
-instance = comp, \LEDR[5]~output\, LEDR[5]~output, LogicTop, 1
-instance = comp, \LEDR[4]~output\, LEDR[4]~output, LogicTop, 1
-instance = comp, \LEDR[3]~output\, LEDR[3]~output, LogicTop, 1
-instance = comp, \LEDR[2]~output\, LEDR[2]~output, LogicTop, 1
-instance = comp, \LEDR[1]~output\, LEDR[1]~output, LogicTop, 1
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, LogicTop, 1
-instance = comp, \SW[1]~input\, SW[1]~input, LogicTop, 1
-instance = comp, \SW[0]~input\, SW[0]~input, LogicTop, 1
-instance = comp, \inst|norOut~0\, inst|norOut~0, LogicTop, 1
-instance = comp, \inst|nandOut~0\, inst|nandOut~0, LogicTop, 1
-instance = comp, \inst|xorOut\, inst|xorOut, LogicTop, 1
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.do b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.do
deleted file mode 100644
index f2d400f..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.do
+++ /dev/null
@@ -1,17 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vcom -work work LogicTop.vho
-vcom -work work LogicUnit.vwf.vht
-vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst
-vcd file -direction LogicDemo.msim.vcd
-vcd add -internal LogicTop_vhd_vec_tst/*
-vcd add -internal LogicTop_vhd_vec_tst/i1/*
-proc simTimestamp {} {
- echo "Simulation time: $::now ps"
- if { [string equal running [runStatus]] } {
- after 2500 simTimestamp
- }
-}
-after 2500 simTimestamp
-run -all
-quit -f
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.msim.vcd b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.msim.vcd
deleted file mode 100644
index e3becc2..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.msim.vcd
+++ /dev/null
@@ -1,180 +0,0 @@
-$comment
- File created using the following command:
- vcd file LogicDemo.msim.vcd -direction
-$end
-$date
- Tue Mar 7 20:45:48 2023
-$end
-$version
- ModelSim Version 2020.1
-$end
-$timescale
- 1ps
-$end
-
-$scope module logictop_vhd_vec_tst $end
-$var wire 1 ! LEDR [5] $end
-$var wire 1 " LEDR [4] $end
-$var wire 1 # LEDR [3] $end
-$var wire 1 $ LEDR [2] $end
-$var wire 1 % LEDR [1] $end
-$var wire 1 & LEDR [0] $end
-$var wire 1 ' SW [1] $end
-$var wire 1 ( SW [0] $end
-
-$scope module i1 $end
-$var wire 1 ) gnd $end
-$var wire 1 * vcc $end
-$var wire 1 + unknown $end
-$var wire 1 , devoe $end
-$var wire 1 - devclrn $end
-$var wire 1 . devpor $end
-$var wire 1 / ww_devoe $end
-$var wire 1 0 ww_devclrn $end
-$var wire 1 1 ww_devpor $end
-$var wire 1 2 ww_LEDR [5] $end
-$var wire 1 3 ww_LEDR [4] $end
-$var wire 1 4 ww_LEDR [3] $end
-$var wire 1 5 ww_LEDR [2] $end
-$var wire 1 6 ww_LEDR [1] $end
-$var wire 1 7 ww_LEDR [0] $end
-$var wire 1 8 ww_SW [1] $end
-$var wire 1 9 ww_SW [0] $end
-$var wire 1 : \LEDR[5]~output_o\ $end
-$var wire 1 ; \LEDR[4]~output_o\ $end
-$var wire 1 < \LEDR[3]~output_o\ $end
-$var wire 1 = \LEDR[2]~output_o\ $end
-$var wire 1 > \LEDR[1]~output_o\ $end
-$var wire 1 ? \LEDR[0]~output_o\ $end
-$var wire 1 @ \SW[1]~input_o\ $end
-$var wire 1 A \SW[0]~input_o\ $end
-$var wire 1 B \inst|norOut~0_combout\ $end
-$var wire 1 C \inst|nandOut~0_combout\ $end
-$var wire 1 D \inst|xorOut~combout\ $end
-$var wire 1 E \ALT_INV_SW[0]~input_o\ $end
-$var wire 1 F \inst|ALT_INV_nandOut~0_combout\ $end
-$var wire 1 G \inst|ALT_INV_norOut~0_combout\ $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0)
-1*
-x+
-1,
-1-
-1.
-1/
-10
-11
-1:
-1;
-0<
-0=
-0>
-1?
-0@
-0A
-0B
-0C
-0D
-1E
-1F
-1G
-0'
-0(
-12
-13
-04
-05
-06
-17
-08
-09
-1!
-1"
-0#
-0$
-0%
-1&
-$end
-#200000
-1(
-19
-1A
-0E
-1B
-1D
-0G
-0?
-1<
-1=
-07
-0:
-14
-15
-0&
-02
-1$
-1#
-0!
-#400000
-0(
-1'
-09
-18
-1@
-0A
-1E
-1?
-17
-1&
-#600000
-1(
-19
-1A
-0E
-1C
-0D
-0F
-0?
-0<
-1>
-07
-0;
-04
-16
-0&
-03
-1%
-0#
-0"
-#800000
-0(
-0'
-09
-08
-0@
-0A
-1E
-0B
-0C
-1F
-1G
-1?
-0>
-0=
-17
-1:
-1;
-06
-05
-1&
-12
-13
-0%
-0$
-1"
-1!
-#1000000
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo_20230307204548.sim.vwf b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo_20230307204548.sim.vwf
deleted file mode 100644
index 7eeca94..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo_20230307204548.sim.vwf
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("LEDR")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 6;
- LSB_INDEX = 0;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("LEDR[5]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "LEDR";
-}
-
-SIGNAL("LEDR[4]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "LEDR";
-}
-
-SIGNAL("LEDR[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "LEDR";
-}
-
-SIGNAL("LEDR[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "LEDR";
-}
-
-SIGNAL("LEDR[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "LEDR";
-}
-
-SIGNAL("LEDR[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "LEDR";
-}
-
-SIGNAL("SW")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 2;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("SW[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-TRANSITION_LIST("LEDR[5]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 600.0;
- LEVEL 1 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("LEDR[4]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 600.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("LEDR[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 400.0;
- LEVEL 0 FOR 400.0;
- }
- }
-}
-
-TRANSITION_LIST("LEDR[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 600.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("LEDR[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 600.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("LEDR[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 400.0;
- LEVEL 1 FOR 400.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
- CHILDREN = 1, 2;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDR";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 0;
- CHILDREN = 4, 5, 6, 7, 8, 9;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDR[5]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 1;
- PARENT = 3;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDR[4]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 5;
- TREE_LEVEL = 1;
- PARENT = 3;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDR[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 6;
- TREE_LEVEL = 1;
- PARENT = 3;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDR[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 7;
- TREE_LEVEL = 1;
- PARENT = 3;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDR[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 8;
- TREE_LEVEL = 1;
- PARENT = 3;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDR[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 9;
- TREE_LEVEL = 1;
- PARENT = 3;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.sft b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.vho b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.vho
deleted file mode 100644
index 884efcf..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.vho
+++ /dev/null
@@ -1,493 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/07/2023 20:45:46"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- AUD_ADCDAT => Location: PIN_D2, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- CLOCK2_50 => Location: PIN_AG14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- CLOCK3_50 => Location: PIN_AG15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- CLOCK_50 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_INT_N => Location: PIN_A21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_LINK100 => Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ENET0_MDIO => Location: PIN_B21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_CLK => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_COL => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_CRS => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[0] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[1] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[2] => Location: PIN_D17, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[3] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DV => Location: PIN_C17, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_ER => Location: PIN_D18, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_TX_CLK => Location: PIN_B17, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_INT_N => Location: PIN_D24, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_LINK100 => Location: PIN_D13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ENET1_MDIO => Location: PIN_D25, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_CLK => Location: PIN_B15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_COL => Location: PIN_B22, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_CRS => Location: PIN_D20, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[0] => Location: PIN_B23, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[1] => Location: PIN_C21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[2] => Location: PIN_A23, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[3] => Location: PIN_D21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DV => Location: PIN_A22, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_ER => Location: PIN_C24, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_TX_CLK => Location: PIN_C22, I/O Standard: 2.5 V, Current Strength: Default
--- ENETCLK_25 => Location: PIN_A14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- FL_RY => Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- HSMC_CLKIN0 => Location: PIN_AH15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- IRDA_RXD => Location: PIN_Y15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[2] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[3] => Location: PIN_R24, I/O Standard: 2.5 V, Current Strength: Default
--- OTG_INT => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- SD_WP_N => Location: PIN_AF14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- SMA_CLKIN => Location: PIN_AH14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- SW[10] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[11] => Location: PIN_AB24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[12] => Location: PIN_AB23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[13] => Location: PIN_AA24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[14] => Location: PIN_AA23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[15] => Location: PIN_AA22, I/O Standard: 2.5 V, Current Strength: Default
--- SW[16] => Location: PIN_Y24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[17] => Location: PIN_Y23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default
--- SW[9] => Location: PIN_AB25, I/O Standard: 2.5 V, Current Strength: Default
--- TD_CLK27 => Location: PIN_B14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[0] => Location: PIN_E8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[1] => Location: PIN_A7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[2] => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[3] => Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[4] => Location: PIN_D7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[5] => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[6] => Location: PIN_E7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[7] => Location: PIN_F7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_HS => Location: PIN_E5, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_VS => Location: PIN_E4, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- UART_RTS => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- UART_RXD => Location: PIN_G12, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \AUD_ADCDAT~padout\ : std_logic;
-SIGNAL \CLOCK2_50~padout\ : std_logic;
-SIGNAL \CLOCK3_50~padout\ : std_logic;
-SIGNAL \CLOCK_50~padout\ : std_logic;
-SIGNAL \ENET0_INT_N~padout\ : std_logic;
-SIGNAL \ENET0_LINK100~padout\ : std_logic;
-SIGNAL \ENET0_MDIO~padout\ : std_logic;
-SIGNAL \ENET0_RX_CLK~padout\ : std_logic;
-SIGNAL \ENET0_RX_COL~padout\ : std_logic;
-SIGNAL \ENET0_RX_CRS~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[0]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[1]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[2]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[3]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DV~padout\ : std_logic;
-SIGNAL \ENET0_RX_ER~padout\ : std_logic;
-SIGNAL \ENET0_TX_CLK~padout\ : std_logic;
-SIGNAL \ENET1_INT_N~padout\ : std_logic;
-SIGNAL \ENET1_LINK100~padout\ : std_logic;
-SIGNAL \ENET1_MDIO~padout\ : std_logic;
-SIGNAL \ENET1_RX_CLK~padout\ : std_logic;
-SIGNAL \ENET1_RX_COL~padout\ : std_logic;
-SIGNAL \ENET1_RX_CRS~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[0]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[1]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[2]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[3]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DV~padout\ : std_logic;
-SIGNAL \ENET1_RX_ER~padout\ : std_logic;
-SIGNAL \ENET1_TX_CLK~padout\ : std_logic;
-SIGNAL \ENETCLK_25~padout\ : std_logic;
-SIGNAL \FL_RY~padout\ : std_logic;
-SIGNAL \HSMC_CLKIN0~padout\ : std_logic;
-SIGNAL \IRDA_RXD~padout\ : std_logic;
-SIGNAL \KEY[0]~padout\ : std_logic;
-SIGNAL \KEY[1]~padout\ : std_logic;
-SIGNAL \KEY[2]~padout\ : std_logic;
-SIGNAL \KEY[3]~padout\ : std_logic;
-SIGNAL \OTG_INT~padout\ : std_logic;
-SIGNAL \SD_WP_N~padout\ : std_logic;
-SIGNAL \SMA_CLKIN~padout\ : std_logic;
-SIGNAL \TD_CLK27~padout\ : std_logic;
-SIGNAL \TD_DATA[0]~padout\ : std_logic;
-SIGNAL \TD_DATA[1]~padout\ : std_logic;
-SIGNAL \TD_DATA[2]~padout\ : std_logic;
-SIGNAL \TD_DATA[3]~padout\ : std_logic;
-SIGNAL \TD_DATA[4]~padout\ : std_logic;
-SIGNAL \TD_DATA[5]~padout\ : std_logic;
-SIGNAL \TD_DATA[6]~padout\ : std_logic;
-SIGNAL \TD_DATA[7]~padout\ : std_logic;
-SIGNAL \TD_HS~padout\ : std_logic;
-SIGNAL \TD_VS~padout\ : std_logic;
-SIGNAL \UART_RTS~padout\ : std_logic;
-SIGNAL \UART_RXD~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \AUD_ADCDAT~ibuf_o\ : std_logic;
-SIGNAL \CLOCK2_50~ibuf_o\ : std_logic;
-SIGNAL \CLOCK3_50~ibuf_o\ : std_logic;
-SIGNAL \CLOCK_50~ibuf_o\ : std_logic;
-SIGNAL \ENET0_INT_N~ibuf_o\ : std_logic;
-SIGNAL \ENET0_LINK100~ibuf_o\ : std_logic;
-SIGNAL \ENET0_MDIO~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_COL~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_CRS~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[0]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[1]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[2]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[3]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DV~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_ER~ibuf_o\ : std_logic;
-SIGNAL \ENET0_TX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENET1_INT_N~ibuf_o\ : std_logic;
-SIGNAL \ENET1_LINK100~ibuf_o\ : std_logic;
-SIGNAL \ENET1_MDIO~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_COL~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_CRS~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[0]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[1]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[2]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[3]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DV~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_ER~ibuf_o\ : std_logic;
-SIGNAL \ENET1_TX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENETCLK_25~ibuf_o\ : std_logic;
-SIGNAL \FL_RY~ibuf_o\ : std_logic;
-SIGNAL \HSMC_CLKIN0~ibuf_o\ : std_logic;
-SIGNAL \IRDA_RXD~ibuf_o\ : std_logic;
-SIGNAL \KEY[0]~ibuf_o\ : std_logic;
-SIGNAL \KEY[1]~ibuf_o\ : std_logic;
-SIGNAL \KEY[2]~ibuf_o\ : std_logic;
-SIGNAL \KEY[3]~ibuf_o\ : std_logic;
-SIGNAL \OTG_INT~ibuf_o\ : std_logic;
-SIGNAL \SD_WP_N~ibuf_o\ : std_logic;
-SIGNAL \SMA_CLKIN~ibuf_o\ : std_logic;
-SIGNAL \SW[10]~ibuf_o\ : std_logic;
-SIGNAL \SW[11]~ibuf_o\ : std_logic;
-SIGNAL \SW[12]~ibuf_o\ : std_logic;
-SIGNAL \SW[13]~ibuf_o\ : std_logic;
-SIGNAL \SW[14]~ibuf_o\ : std_logic;
-SIGNAL \SW[15]~ibuf_o\ : std_logic;
-SIGNAL \SW[16]~ibuf_o\ : std_logic;
-SIGNAL \SW[17]~ibuf_o\ : std_logic;
-SIGNAL \SW[2]~ibuf_o\ : std_logic;
-SIGNAL \SW[3]~ibuf_o\ : std_logic;
-SIGNAL \SW[4]~ibuf_o\ : std_logic;
-SIGNAL \SW[5]~ibuf_o\ : std_logic;
-SIGNAL \SW[6]~ibuf_o\ : std_logic;
-SIGNAL \SW[7]~ibuf_o\ : std_logic;
-SIGNAL \SW[8]~ibuf_o\ : std_logic;
-SIGNAL \SW[9]~ibuf_o\ : std_logic;
-SIGNAL \TD_CLK27~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[0]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[1]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[2]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[3]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[4]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[5]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[6]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[7]~ibuf_o\ : std_logic;
-SIGNAL \TD_HS~ibuf_o\ : std_logic;
-SIGNAL \TD_VS~ibuf_o\ : std_logic;
-SIGNAL \UART_RTS~ibuf_o\ : std_logic;
-SIGNAL \UART_RXD~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-SIGNAL SW : std_logic_vector(1 DOWNTO 0);
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY LogicTop IS
- PORT (
- LEDR : OUT std_logic_vector(5 DOWNTO 0);
- SW : IN std_logic_vector(1 DOWNTO 0)
- );
-END LogicTop;
-
--- Design Ports Information
--- LEDR[5] => Location: PIN_E18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[4] => Location: PIN_F18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF LogicTop IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDR : std_logic_vector(5 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(1 DOWNTO 0);
-SIGNAL \LEDR[5]~output_o\ : std_logic;
-SIGNAL \LEDR[4]~output_o\ : std_logic;
-SIGNAL \LEDR[3]~output_o\ : std_logic;
-SIGNAL \LEDR[2]~output_o\ : std_logic;
-SIGNAL \LEDR[1]~output_o\ : std_logic;
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \inst|norOut~0_combout\ : std_logic;
-SIGNAL \inst|nandOut~0_combout\ : std_logic;
-SIGNAL \inst|xorOut~combout\ : std_logic;
-SIGNAL \ALT_INV_SW[0]~input_o\ : std_logic;
-SIGNAL \inst|ALT_INV_nandOut~0_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_norOut~0_combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-LEDR <= ww_LEDR;
-ww_SW <= SW;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\ALT_INV_SW[0]~input_o\ <= NOT \SW[0]~input_o\;
-\inst|ALT_INV_nandOut~0_combout\ <= NOT \inst|nandOut~0_combout\;
-\inst|ALT_INV_norOut~0_combout\ <= NOT \inst|norOut~0_combout\;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X87_Y73_N9
-\LEDR[5]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|ALT_INV_norOut~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[5]~output_o\);
-
--- Location: IOOBUF_X87_Y73_N16
-\LEDR[4]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|ALT_INV_nandOut~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[4]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N16
-\LEDR[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|xorOut~combout\,
- devoe => ww_devoe,
- o => \LEDR[3]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N9
-\LEDR[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|norOut~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[2]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N2
-\LEDR[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|nandOut~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[1]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N16
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \ALT_INV_SW[0]~input_o\,
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: LCCOMB_X95_Y72_N16
-\inst|norOut~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|norOut~0_combout\ = (\SW[1]~input_o\) # (\SW[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111111001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[1]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \inst|norOut~0_combout\);
-
--- Location: LCCOMB_X95_Y72_N10
-\inst|nandOut~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|nandOut~0_combout\ = (\SW[1]~input_o\ & \SW[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100110000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[1]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \inst|nandOut~0_combout\);
-
--- Location: LCCOMB_X95_Y72_N28
-\inst|xorOut\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|xorOut~combout\ = \SW[1]~input_o\ $ (\SW[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011001111001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[1]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \inst|xorOut~combout\);
-
-ww_LEDR(5) <= \LEDR[5]~output_o\;
-
-ww_LEDR(4) <= \LEDR[4]~output_o\;
-
-ww_LEDR(3) <= \LEDR[3]~output_o\;
-
-ww_LEDR(2) <= \LEDR[2]~output_o\;
-
-ww_LEDR(1) <= \LEDR[1]~output_o\;
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop_modelsim.xrf b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop_modelsim.xrf
deleted file mode 100644
index 3930aec..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop_modelsim.xrf
+++ /dev/null
@@ -1,21 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicTop.bdf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cbx.xml
-design_name = hard_block
-design_name = LogicTop
-instance = comp, \LEDR[5]~output\, LEDR[5]~output, LogicTop, 1
-instance = comp, \LEDR[4]~output\, LEDR[4]~output, LogicTop, 1
-instance = comp, \LEDR[3]~output\, LEDR[3]~output, LogicTop, 1
-instance = comp, \LEDR[2]~output\, LEDR[2]~output, LogicTop, 1
-instance = comp, \LEDR[1]~output\, LEDR[1]~output, LogicTop, 1
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, LogicTop, 1
-instance = comp, \SW[1]~input\, SW[1]~input, LogicTop, 1
-instance = comp, \SW[0]~input\, SW[0]~input, LogicTop, 1
-instance = comp, \inst|norOut~0\, inst|norOut~0, LogicTop, 1
-instance = comp, \inst|nandOut~0\, inst|nandOut~0, LogicTop, 1
-instance = comp, \inst|xorOut\, inst|xorOut, LogicTop, 1
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht
deleted file mode 100644
index dfc5416..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht
+++ /dev/null
@@ -1,75 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- *****************************************************************************
--- This file contains a Vhdl test bench with test vectors .The test vectors
--- are exported from a vector file in the Quartus Waveform Editor and apply to
--- the top level entity of the current Quartus project .The user can use this
--- testbench to simulate his design using a third-party simulation tool .
--- *****************************************************************************
--- Generated on "03/07/2023 20:45:46"
-
--- Vhdl Test Bench(with test vectors) for design : LogicTop
---
--- Simulation tool : 3rd Party
---
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY LogicTop_vhd_vec_tst IS
-END LogicTop_vhd_vec_tst;
-ARCHITECTURE LogicTop_arch OF LogicTop_vhd_vec_tst IS
--- constants
--- signals
-SIGNAL LEDR : STD_LOGIC_VECTOR(5 DOWNTO 0);
-SIGNAL SW : STD_LOGIC_VECTOR(1 DOWNTO 0);
-COMPONENT LogicTop
- PORT (
- LEDR : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
- SW : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
- );
-END COMPONENT;
-BEGIN
- i1 : LogicTop
- PORT MAP (
--- list connections between master ports and signals
- LEDR => LEDR,
- SW => SW
- );
--- SW[1]
-t_prcs_SW_1: PROCESS
-BEGIN
- SW(1) <= '0';
- WAIT FOR 400000 ps;
- SW(1) <= '1';
- WAIT FOR 400000 ps;
- SW(1) <= '0';
-WAIT;
-END PROCESS t_prcs_SW_1;
--- SW[0]
-t_prcs_SW_0: PROCESS
-BEGIN
- FOR i IN 1 TO 2
- LOOP
- SW(0) <= '0';
- WAIT FOR 200000 ps;
- SW(0) <= '1';
- WAIT FOR 200000 ps;
- END LOOP;
- SW(0) <= '0';
-WAIT;
-END PROCESS t_prcs_SW_0;
-END LogicTop_arch;
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/transcript
deleted file mode 100644
index 5901b1c..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/transcript
+++ /dev/null
@@ -1,46 +0,0 @@
-# do LogicDemo.do
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 20:45:47 on Mar 07,2023
-# vcom -work work LogicTop.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity hard_block
-# -- Compiling architecture structure of hard_block
-# -- Compiling entity LogicTop
-# -- Compiling architecture structure of LogicTop
-# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 20:45:47 on Mar 07,2023
-# vcom -work work LogicUnit.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity LogicTop_vhd_vec_tst
-# -- Compiling architecture LogicTop_arch of LogicTop_vhd_vec_tst
-# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst
-# Start time: 20:45:47 on Mar 07,2023
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading work.logictop_vhd_vec_tst(logictop_arch)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading cycloneive.cycloneive_atom_pack(body)
-# Loading cycloneive.cycloneive_components
-# Loading work.logictop(structure)
-# Loading work.hard_block(structure)
-# Loading ieee.std_logic_arith(body)
-# Loading cycloneive.cycloneive_io_obuf(arch)
-# Loading cycloneive.cycloneive_io_ibuf(arch)
-# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#31
-# End time: 20:45:48 on Mar 07,2023, Elapsed time: 0:00:01
-# Errors: 0, Warnings: 0
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/vwf_sim_transcript
deleted file mode 100644
index dc656c4..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/vwf_sim_transcript
+++ /dev/null
@@ -1,66 +0,0 @@
-Determining the location of the ModelSim executable...
-
-Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
-
-To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
-Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
-
-**** Generating the ModelSim Testbench ****
-
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht"
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Mar 7 20:45:45 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vhtWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Completed successfully.
-
-**** Generating the functional simulation netlist ****
-
-quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/" LogicDemo -c LogicTop
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Mar 7 20:45:46 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/ LogicDemo -c LogicTopWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file LogicTop.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 613 megabytes Info: Processing ended: Tue Mar 7 20:45:46 2023 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00
-Completed successfully.
-
-**** Generating the ModelSim .do script ****
-
-/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.do generated.
-
-Completed successfully.
-
-**** Running the ModelSim simulation ****
-
-/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do LogicDemo.do
-
-Reading pref.tcl
-# 2020.1
-# do LogicDemo.do
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 20:45:47 on Mar 07,2023# vcom -work work LogicTop.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164# -- Loading package VITAL_Timing# -- Loading package VITAL_Primitives# -- Loading package cycloneive_atom_pack# -- Loading package cycloneive_components
-# -- Compiling entity hard_block# -- Compiling architecture structure of hard_block
-# -- Compiling entity LogicTop
-# -- Compiling architecture structure of LogicTop
-# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 20:45:47 on Mar 07,2023# vcom -work work LogicUnit.vwf.vht # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164
-# -- Compiling entity LogicTop_vhd_vec_tst# -- Compiling architecture LogicTop_arch of LogicTop_vhd_vec_tst# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst # Start time: 20:45:47 on Mar 07,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.logictop_vhd_vec_tst(logictop_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.logictop(structure)# Loading work.hard_block(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#31
-# End time: 20:45:48 on Mar 07,2023, Elapsed time: 0:00:01# Errors: 0, Warnings: 0
-Completed successfully.
-
-**** Converting ModelSim VCD to vector waveform ****
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf...
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.msim.vcd...
-
-Processing channel transitions...
-
-Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo_20230307204548.sim.vwf
-
-Finished VCD to VWF conversion.
-
-Completed successfully.
-
-All completed.
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_info
deleted file mode 100644
index cfadd6d..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_info
+++ /dev/null
@@ -1,150 +0,0 @@
-m255
-K4
-z2
-!s11e vcom 2020.1 2020.02, Feb 28 2020
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-Z0 d/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim
-Ehard_block
-Z1 w1678221946
-Z2 DPx4 ieee 16 vital_primitives 0 22 G>kiXP8Q9dRClKfK1Zn7j1
-Z3 DPx10 cycloneive 20 cycloneive_atom_pack 0 22 WOh:M[al;oVzG5c`D0
-Z4 DPx4 ieee 12 vital_timing 0 22 J>EBealN09f8GzldA[z2>3
-Z5 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
-Z6 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
-Z7 DPx10 cycloneive 21 cycloneive_components 0 22 zGMDhP>8e@2k@f0emXi5[`cD`bFC`UBKAd7S@ez]d>m<1J[fSE0
-R10
-32
-R11
-!i10b 1
-R12
-R13
-R14
-!i113 1
-R15
-R16
-Elogictop
-R1
-R2
-R3
-R4
-R5
-R6
-R7
-!i122 0
-R0
-R8
-R9
-l0
-L273 1
-VamRNemglHiOn]lDzli8RS0
-!s100 @neTjOkn_jg[3Ya6ohP`O3
-R10
-32
-R11
-!i10b 1
-R12
-R13
-R14
-!i113 1
-R15
-R16
-Astructure
-R2
-R3
-R4
-R5
-R6
-R7
-DEx4 work 8 logictop 0 22 amRNemglHiOn]lDzli8RS0
-!i122 0
-l325
-L291 201
-VzN2a:JlON9MaLYa22KCGW3
-!s100 lg1G1cg;lW_hK:DMNT2mA0
-R10
-32
-R11
-!i10b 1
-R12
-R13
-R14
-!i113 1
-R15
-R16
-Elogictop_vhd_vec_tst
-R1
-R5
-R6
-!i122 1
-R0
-Z17 8LogicUnit.vwf.vht
-Z18 FLogicUnit.vwf.vht
-l0
-L32 1
-VIV@:01Q:J;Cf@:fS?_PGl1
-!s100 lj;CCYfN7eE^F0O89PHXM;AAWK2
-!s100 S10b?0dIc:b41zfWl2eDd2
-R10
-32
-R11
-!i10b 1
-R12
-R19
-Z20 !s107 LogicUnit.vwf.vht|
-!i113 1
-R15
-R16
diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_lib.qdb b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_lib.qdb
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diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_lib1_0.qtl b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_lib1_0.qtl
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diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_vmake b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_vmake
deleted file mode 100644
index 37aa36a..0000000
--- a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_vmake
+++ /dev/null
@@ -1,4 +0,0 @@
-m255
-K4
-z0
-cModel Technology
diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd.bak b/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd.bak
deleted file mode 100644
index e69de29..0000000
diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qpf b/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qpf
deleted file mode 100644
index f74c793..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 17:39:56 March 07, 2023
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "20.1"
-DATE = "17:39:56 March 07, 2023"
-
-# Revisions
-
-PROJECT_REVISION = "EqCmpDemo"
diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf b/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf
deleted file mode 100644
index c611c2b..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf
+++ /dev/null
@@ -1,1185 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 17:39:56 March 07, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# EqCmpDemo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY EqCmpDemo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:39:56 MARCH 07, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name BDF_FILE EqCmp4.bdf
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "2.5 V" -to CLOCK_50
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to KEY[3]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to KEY
-set_location_assignment PIN_AB28 -to SW[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[17]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to SW
-set_location_assignment PIN_G19 -to LEDR[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX0
-set_location_assignment PIN_M24 -to HEX1[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX1
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX2
-set_location_assignment PIN_V21 -to HEX3[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[0]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[1]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HSMC_CLKIN0
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6]
-set_global_assignment -name BDF_FILE EqCmpDemo.bdf
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VHDL_FILE EqCmp8.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE EqCmp8.vwf
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-set_global_assignment -name VECTOR_WAVEFORM_FILE EqCmp4.vwf
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf.bak b/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf.bak
deleted file mode 100644
index 34c1f6f..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf.bak
+++ /dev/null
@@ -1,1183 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 17:39:56 March 07, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# EqCmpDemo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY EqCmpDemo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:39:56 MARCH 07, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name BDF_FILE EqCmp4.bdf
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "2.5 V" -to CLOCK_50
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to KEY[3]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to KEY
-set_location_assignment PIN_AB28 -to SW[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[17]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to SW
-set_location_assignment PIN_G19 -to LEDR[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX0
-set_location_assignment PIN_M24 -to HEX1[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX1
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX2
-set_location_assignment PIN_V21 -to HEX3[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[0]
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[1]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7]
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HSMC_CLKIN0
-set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6]
-set_global_assignment -name BDF_FILE EqCmpDemo.bdf
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VHDL_FILE EqCmp8.vhd
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qws b/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qws
deleted file mode 100644
index 43954ed..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(0).cnf.cdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(0).cnf.cdb
deleted file mode 100644
index 2e17b34..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(0).cnf.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(0).cnf.hdb
deleted file mode 100644
index 5052fed..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(1).cnf.cdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(1).cnf.cdb
deleted file mode 100644
index 0d28112..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(1).cnf.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(1).cnf.hdb
deleted file mode 100644
index 4430d1f..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(2).cnf.cdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(2).cnf.cdb
deleted file mode 100644
index eaf9f32..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(2).cnf.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(2).cnf.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(2).cnf.hdb
deleted file mode 100644
index ea0a1ed..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(2).cnf.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.asm.qmsg b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.asm.qmsg
deleted file mode 100644
index 1a626aa..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.asm.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678222514063 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222514063 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:55:13 2023 " "Processing started: Tue Mar 7 20:55:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678222514063 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678222514063 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678222514063 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678222514271 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678222516408 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678222516505 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "366 " "Peak virtual memory: 366 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678222516764 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:55:16 2023 " "Processing ended: Tue Mar 7 20:55:16 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678222516764 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678222516764 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678222516764 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678222516764 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.asm.rdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.asm.rdb
deleted file mode 100644
index 2e7fbff..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.asm_labs.ddb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.asm_labs.ddb
deleted file mode 100644
index 1d2b1e4..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.asm_labs.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cbx.xml b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cbx.xml
deleted file mode 100644
index eda0a61..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.bpm b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.bpm
deleted file mode 100644
index f31dda4..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.cdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.cdb
deleted file mode 100644
index 3a0b6b0..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.hdb
deleted file mode 100644
index 3bbff07..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.idb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.idb
deleted file mode 100644
index 037c75c..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.idb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.logdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.logdb
deleted file mode 100644
index 90d91d6..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.logdb
+++ /dev/null
@@ -1,115 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,22 I/O(s) were assigned a toggle rate,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,22 I/O(s) were assigned a toggle rate,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;9;9;0;0;73;9;0;0;0;0;0;0;1;0;0;0;72;1;0;72;0;0;1;0;73;73;73;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,73;64;64;73;73;0;64;73;73;73;73;73;73;72;73;73;73;1;72;73;1;73;73;72;73;0;0;0;73;73,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,LEDG[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,AUD_ADCDAT,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CLOCK2_50,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CLOCK3_50,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CLOCK_50,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_INT_N,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_LINK100,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_MDIO,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_COL,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_CRS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_DATA[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_DATA[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_DATA[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_DATA[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_DV,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_RX_ER,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET0_TX_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_INT_N,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_LINK100,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_MDIO,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_COL,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_CRS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_DATA[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_DATA[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_DATA[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_DATA[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_DV,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_RX_ER,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENET1_TX_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENETCLK_25,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,FL_RY,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HSMC_CLKIN0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,IRDA_RXD,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,OTG_INT,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SD_WP_N,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SMA_CLKIN,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[16],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[17],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_CLK27,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_DATA[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_HS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,TD_VS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,UART_RTS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,UART_RXD,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.rdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp.rdb
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp_merge.kpt b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cmp_merge.kpt
deleted file mode 100644
index 2424507..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index 6642b88..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
deleted file mode 100644
index e357492..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
deleted file mode 100644
index 19c469a..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.db_info b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.db_info
deleted file mode 100644
index 4b36e2b..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Tue Mar 7 20:46:10 2023
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.eda.qmsg b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.eda.qmsg
deleted file mode 100644
index 8889b12..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678222677857 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2020 Intel Corporation. All rights reserved. " "Copyright (C) 2020 Intel Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions " "Your use of Intel Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and any partner logic " "and other software and tools, and any partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License " "to the terms and conditions of the Intel Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel FPGA IP License Agreement, or other applicable license " "the Intel FPGA IP License Agreement, or other applicable license" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement, including, without limitation, that your use is for " "agreement, including, without limitation, that your use is for" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the sole purpose of programming logic devices manufactured by " "the sole purpose of programming logic devices manufactured by" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Intel and sold by Intel or its authorized distributors. Please " "Intel and sold by Intel or its authorized distributors. Please" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "refer to the applicable agreement for further details, at " "refer to the applicable agreement for further details, at" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "https://fpgasoftware.intel.com/eula. " "https://fpgasoftware.intel.com/eula." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:57:57 2023 " "Processing started: Tue Mar 7 20:57:57 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678222677858 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/ EqCmpDemo -c EqCmpDemo " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/ EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678222677858 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678222678041 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "EqCmpDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim// simulation " "Generated file EqCmpDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678222678072 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "613 " "Peak virtual memory: 613 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678222678086 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:57:58 2023 " "Processing ended: Tue Mar 7 20:57:58 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678222678086 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678222678086 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678222678086 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678222678086 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.fit.qmsg b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.fit.qmsg
deleted file mode 100644
index e034d3e..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.fit.qmsg
+++ /dev/null
@@ -1,129 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678222504333 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678222504333 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "EqCmpDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"EqCmpDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504339 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678222504440 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678222504440 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678222504830 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678222504834 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678222504892 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "AUD_ADCDAT " "Can't reserve pin AUD_ADCDAT -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK2_50 " "Can't reserve pin CLOCK2_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK3_50 " "Can't reserve pin CLOCK3_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK_50 " "Can't reserve pin CLOCK_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_INT_N " "Can't reserve pin ENET0_INT_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_LINK100 " "Can't reserve pin ENET0_LINK100 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_MDIO " "Can't reserve pin ENET0_MDIO -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_CLK " "Can't reserve pin ENET0_RX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_COL " "Can't reserve pin ENET0_RX_COL -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_CRS " "Can't reserve pin ENET0_RX_CRS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[0\] " "Can't reserve pin ENET0_RX_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[1\] " "Can't reserve pin ENET0_RX_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[2\] " "Can't reserve pin ENET0_RX_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[3\] " "Can't reserve pin ENET0_RX_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DV " "Can't reserve pin ENET0_RX_DV -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_ER " "Can't reserve pin ENET0_RX_ER -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_TX_CLK " "Can't reserve pin ENET0_TX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_INT_N " "Can't reserve pin ENET1_INT_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_LINK100 " "Can't reserve pin ENET1_LINK100 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_MDIO " "Can't reserve pin ENET1_MDIO -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_CLK " "Can't reserve pin ENET1_RX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_COL " "Can't reserve pin ENET1_RX_COL -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_CRS " "Can't reserve pin ENET1_RX_CRS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[0\] " "Can't reserve pin ENET1_RX_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[1\] " "Can't reserve pin ENET1_RX_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[2\] " "Can't reserve pin ENET1_RX_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[3\] " "Can't reserve pin ENET1_RX_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DV " "Can't reserve pin ENET1_RX_DV -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_ER " "Can't reserve pin ENET1_RX_ER -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_TX_CLK " "Can't reserve pin ENET1_TX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENETCLK_25 " "Can't reserve pin ENETCLK_25 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "FL_RY " "Can't reserve pin FL_RY -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "HSMC_CLKIN0 " "Can't reserve pin HSMC_CLKIN0 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "IRDA_RXD " "Can't reserve pin IRDA_RXD -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[0\] " "Can't reserve pin KEY\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[1\] " "Can't reserve pin KEY\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[2\] " "Can't reserve pin KEY\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[3\] " "Can't reserve pin KEY\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "OTG_INT " "Can't reserve pin OTG_INT -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SD_WP_N " "Can't reserve pin SD_WP_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SMA_CLKIN " "Can't reserve pin SMA_CLKIN -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[0\] " "Can't reserve pin SW\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[0\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[0\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[0] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 14 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[10\] " "Can't reserve pin SW\[10\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[11\] " "Can't reserve pin SW\[11\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[12\] " "Can't reserve pin SW\[12\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[13\] " "Can't reserve pin SW\[13\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[14\] " "Can't reserve pin SW\[14\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[15\] " "Can't reserve pin SW\[15\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[16\] " "Can't reserve pin SW\[16\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[17\] " "Can't reserve pin SW\[17\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[1\] " "Can't reserve pin SW\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[1\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[1\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[1] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 13 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[2\] " "Can't reserve pin SW\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[2\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[2\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[2] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 12 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[3\] " "Can't reserve pin SW\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[3\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[3\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[3] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 11 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[4\] " "Can't reserve pin SW\[4\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[4\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[4\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[4] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[5\] " "Can't reserve pin SW\[5\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[5\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[5\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[5] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 9 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[6\] " "Can't reserve pin SW\[6\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[6\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[6\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[6] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 8 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[7\] " "Can't reserve pin SW\[7\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[7\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[7\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[7] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 7 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[8\] " "Can't reserve pin SW\[8\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[9\] " "Can't reserve pin SW\[9\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_CLK27 " "Can't reserve pin TD_CLK27 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[0\] " "Can't reserve pin TD_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[1\] " "Can't reserve pin TD_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[2\] " "Can't reserve pin TD_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[3\] " "Can't reserve pin TD_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[4\] " "Can't reserve pin TD_DATA\[4\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[5\] " "Can't reserve pin TD_DATA\[5\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[6\] " "Can't reserve pin TD_DATA\[6\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[7\] " "Can't reserve pin TD_DATA\[7\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_HS " "Can't reserve pin TD_HS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_VS " "Can't reserve pin TD_VS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "UART_RTS " "Can't reserve pin UART_RTS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504899 ""}
-{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "UART_RXD " "Can't reserve pin UART_RXD -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504899 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 643 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678222504900 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 645 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678222504900 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 647 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678222504900 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 649 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678222504900 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 651 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678222504900 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678222504900 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678222504901 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "EqCmpDemo.sdc " "Synopsys Design Constraints File file not found: 'EqCmpDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678222505711 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678222505711 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678222505712 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678222505712 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678222505713 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678222505713 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678222505713 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678222505716 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678222505716 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678222505716 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678222505717 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678222505717 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678222505718 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678222505718 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678222505718 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678222505718 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678222505718 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678222505718 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678222505774 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678222505785 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678222505788 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678222508212 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678222508347 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678222508393 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678222508641 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678222508641 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678222508841 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y12 X115_Y23 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23"} { { 12 { 0 ""} 104 12 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678222511923 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678222511923 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678222512080 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678222512080 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678222512080 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678222512081 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678222512176 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678222512185 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678222512399 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678222512399 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678222512603 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678222512913 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678222513160 ""}
-{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "25 Cyclone IV E " "25 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D2 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 15 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK2_50 3.3-V LVTTL AG14 " "Pin CLOCK2_50 uses I/O standard 3.3-V LVTTL at AG14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { CLOCK2_50 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 21 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK3_50 3.3-V LVTTL AG15 " "Pin CLOCK3_50 uses I/O standard 3.3-V LVTTL at AG15" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { CLOCK3_50 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 22 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENET0_LINK100 3.3-V LVTTL C14 " "Pin ENET0_LINK100 uses I/O standard 3.3-V LVTTL at C14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENET0_LINK100 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 89 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENET1_LINK100 3.3-V LVTTL D13 " "Pin ENET1_LINK100 uses I/O standard 3.3-V LVTTL at D13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENET1_LINK100 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 113 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENETCLK_25 3.3-V LVTTL A14 " "Pin ENETCLK_25 uses I/O standard 3.3-V LVTTL at A14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENETCLK_25 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 135 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "FL_RY 3.3-V LVTTL Y1 " "Pin FL_RY uses I/O standard 3.3-V LVTTL at Y1" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { FL_RY } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 180 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "HSMC_CLKIN0 3.3-V LVTTL AH15 " "Pin HSMC_CLKIN0 uses I/O standard 3.3-V LVTTL at AH15" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { HSMC_CLKIN0 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 284 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "IRDA_RXD 3.3-V LVTTL Y15 " "Pin IRDA_RXD uses I/O standard 3.3-V LVTTL at Y15" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { IRDA_RXD } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 373 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "OTG_INT 3.3-V LVTTL D5 " "Pin OTG_INT uses I/O standard 3.3-V LVTTL at D5" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { OTG_INT } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 443 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SD_WP_N 3.3-V LVTTL AF14 " "Pin SD_WP_N uses I/O standard 3.3-V LVTTL at AF14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SD_WP_N } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 458 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SMA_CLKIN 3.3-V LVTTL AH14 " "Pin SMA_CLKIN uses I/O standard 3.3-V LVTTL at AH14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SMA_CLKIN } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 459 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_CLK27 3.3-V LVTTL B14 " "Pin TD_CLK27 uses I/O standard 3.3-V LVTTL at B14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_CLK27 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 514 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[0\] 3.3-V LVTTL E8 " "Pin TD_DATA\[0\] uses I/O standard 3.3-V LVTTL at E8" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[0] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 516 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[1\] 3.3-V LVTTL A7 " "Pin TD_DATA\[1\] uses I/O standard 3.3-V LVTTL at A7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[1] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 517 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[2\] 3.3-V LVTTL D8 " "Pin TD_DATA\[2\] uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[2] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 518 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[3\] 3.3-V LVTTL C7 " "Pin TD_DATA\[3\] uses I/O standard 3.3-V LVTTL at C7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[3] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 519 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[4\] 3.3-V LVTTL D7 " "Pin TD_DATA\[4\] uses I/O standard 3.3-V LVTTL at D7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[4] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 520 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[5\] 3.3-V LVTTL D6 " "Pin TD_DATA\[5\] uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[5] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 521 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[6\] 3.3-V LVTTL E7 " "Pin TD_DATA\[6\] uses I/O standard 3.3-V LVTTL at E7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[6] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 522 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[7\] 3.3-V LVTTL F7 " "Pin TD_DATA\[7\] uses I/O standard 3.3-V LVTTL at F7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[7] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 523 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_HS 3.3-V LVTTL E5 " "Pin TD_HS uses I/O standard 3.3-V LVTTL at E5" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_HS } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 524 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_VS 3.3-V LVTTL E4 " "Pin TD_VS uses I/O standard 3.3-V LVTTL at E4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_VS } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 526 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART_RTS 3.3-V LVTTL J13 " "Pin UART_RTS uses I/O standard 3.3-V LVTTL at J13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { UART_RTS } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 528 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART_RXD 3.3-V LVTTL G12 " "Pin UART_RXD uses I/O standard 3.3-V LVTTL at G12" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { UART_RXD } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 529 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1678222513165 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678222513214 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 534 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 534 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1157 " "Peak virtual memory: 1157 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678222513382 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:55:13 2023 " "Processing ended: Tue Mar 7 20:55:13 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678222513382 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678222513382 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678222513382 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678222513382 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.hier_info b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.hier_info
deleted file mode 100644
index e6791d5..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.hier_info
+++ /dev/null
@@ -1,24 +0,0 @@
-|EqCmpDemo
-LEDG[0] <= EqCmp4:inst1.cmpOut
-SW[0] => EqCmp4:inst1.input0[0]
-SW[1] => EqCmp4:inst1.input0[1]
-SW[2] => EqCmp4:inst1.input0[2]
-SW[3] => EqCmp4:inst1.input0[3]
-SW[4] => EqCmp4:inst1.input1[0]
-SW[5] => EqCmp4:inst1.input1[1]
-SW[6] => EqCmp4:inst1.input1[2]
-SW[7] => EqCmp4:inst1.input1[3]
-
-
-|EqCmpDemo|EqCmp4:inst1
-cmpOut <= inst.DB_MAX_OUTPUT_PORT_TYPE
-input0[0] => xnor_0.IN0
-input0[1] => xnor_1.IN0
-input0[2] => xnor_2.IN0
-input0[3] => xnor_3.IN0
-input1[0] => xnor_0.IN1
-input1[1] => xnor_1.IN1
-input1[2] => xnor_2.IN1
-input1[3] => xnor_3.IN1
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.hif b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.hif
deleted file mode 100644
index a91b9dd..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.html b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.html
deleted file mode 100644
index 5859494..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.html
+++ /dev/null
@@ -1,34 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| inst1 |
-8 |
-0 |
-0 |
-0 |
-1 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.rdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.rdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.txt b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.txt
deleted file mode 100644
index b4fb91f..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; inst1 ; 8 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.ammdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.ammdb
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.bpm b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.bpm
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.cdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.cdb
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.hdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.kpt b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.kpt
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.logdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.qmsg b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.qmsg
deleted file mode 100644
index 48ae82d..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.qmsg
+++ /dev/null
@@ -1,14 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678222495047 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222495052 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:54:54 2023 " "Processing started: Tue Mar 7 20:54:54 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678222495052 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678222495052 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678222495052 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678222495248 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678222495248 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EqCmp4.bdf 1 1 " "Found 1 design units, including 1 entities, in source file EqCmp4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 EqCmp4 " "Found entity 1: EqCmp4" { } { { "EqCmp4.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678222501791 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678222501791 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EqCmpDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file EqCmpDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 EqCmpDemo " "Found entity 1: EqCmpDemo" { } { { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678222501792 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678222501792 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EqCmp8.vhd 2 1 " "Found 2 design units, including 1 entities, in source file EqCmp8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 EqCmp8-Behavioral " "Found design unit 1: EqCmp8-Behavioral" { } { { "EqCmp8.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678222502146 ""} { "Info" "ISGN_ENTITY_NAME" "1 EqCmp8 " "Found entity 1: EqCmp8" { } { { "EqCmp8.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678222502146 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678222502146 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "EqCmpDemo " "Elaborating entity \"EqCmpDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678222502196 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "EqCmp4 EqCmp4:inst1 " "Elaborating entity \"EqCmp4\" for hierarchy \"EqCmp4:inst1\"" { } { { "EqCmpDemo.bdf" "inst1" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 176 472 640 272 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678222502199 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678222502763 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678222503335 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678222503335 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "12 " "Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678222503360 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678222503360 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3 " "Implemented 3 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678222503360 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678222503360 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678222503366 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:55:03 2023 " "Processing ended: Tue Mar 7 20:55:03 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678222503366 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678222503366 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678222503366 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678222503366 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.rdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.rdb
deleted file mode 100644
index 9afbbed..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.cdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.cdb
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.logdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.logdb
deleted file mode 100644
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--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.pre_map.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sld_design_entry.sci b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.smart_action.txt b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.smart_action.txt
deleted file mode 100644
index 11b531f..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-SOURCE
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sta.qmsg b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sta.qmsg
deleted file mode 100644
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--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678222517412 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222517412 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:55:17 2023 " "Processing started: Tue Mar 7 20:55:17 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678222517412 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678222517412 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta EqCmpDemo -c EqCmpDemo " "Command: quartus_sta EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678222517412 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678222517445 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678222517549 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678222517549 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678222517618 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678222517618 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "EqCmpDemo.sdc " "Synopsys Design Constraints File file not found: 'EqCmpDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678222518044 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678222518044 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678222518044 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678222518045 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678222518045 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678222518045 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678222518045 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678222518051 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678222518052 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518052 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518055 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518056 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518056 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518056 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518057 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678222518060 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678222518078 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678222518288 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678222518306 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678222518306 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678222518306 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678222518306 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518306 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518307 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518307 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518308 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518308 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518308 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678222518310 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678222518359 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678222518359 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678222518360 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678222518360 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518360 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518361 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518361 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518362 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518362 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678222518664 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678222518664 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "534 " "Peak virtual memory: 534 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678222518679 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:55:18 2023 " "Processing ended: Tue Mar 7 20:55:18 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678222518679 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678222518679 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678222518679 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678222518679 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sta.rdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sta.rdb
deleted file mode 100644
index bc2ce80..0000000
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diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sta_cmp.7_slow_1200mv_85c.tdb
deleted file mode 100644
index 09360cf..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sta_cmp.7_slow_1200mv_85c.tdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tis_db_list.ddb
deleted file mode 100644
index 73e5ec9..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tis_db_list.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index 7fe17c1..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.fast_1200mv_0c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index 29483f5..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_0c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index 046dbb0..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tmw_info b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tmw_info
deleted file mode 100644
index 6d8f47e..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tmw_info
+++ /dev/null
@@ -1,7 +0,0 @@
-start_full_compilation:s:00:00:25
-start_analysis_synthesis:s:00:00:09-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:10-start_full_compilation
-start_assembler:s:00:00:03-start_full_compilation
-start_timing_analyzer:s:00:00:02-start_full_compilation
-start_eda_netlist_writer:s:00:00:01-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.vpr.ammdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.vpr.ammdb
deleted file mode 100644
index ad0dcba..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo_partition_pins.json b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo_partition_pins.json
deleted file mode 100644
index 8a62544..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo_partition_pins.json
+++ /dev/null
@@ -1,45 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "LEDG[0]",
- "strict" : false
- },
- {
- "name" : "SW[4]",
- "strict" : false
- },
- {
- "name" : "SW[5]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- },
- {
- "name" : "SW[6]",
- "strict" : false
- },
- {
- "name" : "SW[7]",
- "strict" : false
- },
- {
- "name" : "SW[3]",
- "strict" : false
- },
- {
- "name" : "SW[2]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part4/db/prev_cmp_EqCmpDemo.qmsg b/1ano/2semestre/lsd/pratica01/part4/db/prev_cmp_EqCmpDemo.qmsg
deleted file mode 100644
index 0a466e3..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/db/prev_cmp_EqCmpDemo.qmsg
+++ /dev/null
@@ -1,4 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678220103838 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus Prime " "Running Quartus Prime Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678220103838 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:15:03 2023 " "Processing started: Tue Mar 7 20:15:03 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678220103838 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1678220103838 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd " "Command: quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1678220103838 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus Prime " "Quartus Prime Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "695 " "Peak virtual memory: 695 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678220104340 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:15:04 2023 " "Processing ended: Tue Mar 7 20:15:04 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678220104340 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678220104340 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678220104340 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1678220104340 ""}
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/README b/1ano/2semestre/lsd/pratica01/part4/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.db_info b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.db_info
deleted file mode 100644
index 0fe1b99..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Tue Mar 7 18:05:53 2023
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.ammdb
deleted file mode 100644
index a74a749..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.cdb
deleted file mode 100644
index 6fc9667..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.dfp and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.hdb
deleted file mode 100644
index 7667ce2..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.rcfdb
deleted file mode 100644
index c0bf5b7..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.rcfdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.cdb
deleted file mode 100644
index 9f9bce5..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.dpi
deleted file mode 100644
index b916213..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.dpi and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.cdb
deleted file mode 100644
index 4a76b64..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.hdb
deleted file mode 100644
index c233428..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hdb
deleted file mode 100644
index bfed99a..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.kpt
deleted file mode 100644
index ee9e60b..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.rrp.hdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.rrp.hdb
deleted file mode 100644
index b5da8e9..0000000
Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.asm.rpt b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.asm.rpt
deleted file mode 100644
index 4188696..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for EqCmpDemo
-Tue Mar 7 20:55:16 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: EqCmpDemo.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Tue Mar 7 20:55:16 2023 ;
-; Revision Name ; EqCmpDemo ;
-; Top-level Entity Name ; EqCmpDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+------------------------------------------------------------------------------------------------+
-; File Name ;
-+------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sof ;
-+------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------+
-; Assembler Device Options: EqCmpDemo.sof ;
-+----------------+------------------------+
-; Option ; Setting ;
-+----------------+------------------------+
-; JTAG usercode ; 0x0056272C ;
-; Checksum ; 0x0056272C ;
-+----------------+------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 20:55:13 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 366 megabytes
- Info: Processing ended: Tue Mar 7 20:55:16 2023
- Info: Elapsed time: 00:00:03
- Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.done b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.done
deleted file mode 100644
index 184a80f..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.done
+++ /dev/null
@@ -1 +0,0 @@
-Tue Mar 7 20:55:19 2023
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.eda.rpt b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.eda.rpt
deleted file mode 100644
index 0387fc4..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.eda.rpt
+++ /dev/null
@@ -1,108 +0,0 @@
-EDA Netlist Writer report for EqCmpDemo
-Tue Mar 7 20:57:58 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Tue Mar 7 20:57:58 2023 ;
-; Revision Name ; EqCmpDemo ;
-; Top-level Entity Name ; EqCmpDemo ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+----------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+----------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+----------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim//EqCmpDemo.vho ;
-+----------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
- Info: Your use of Intel Corporation's design tools, logic functions
- Info: and other software and tools, and any partner logic
- Info: functions, and any output files from any of the foregoing
- Info: (including device programming or simulation files), and any
- Info: associated documentation or information are expressly subject
- Info: to the terms and conditions of the Intel Program License
- Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
- Info: the Intel FPGA IP License Agreement, or other applicable license
- Info: agreement, including, without limitation, that your use is for
- Info: the sole purpose of programming logic devices manufactured by
- Info: Intel and sold by Intel or its authorized distributors. Please
- Info: refer to the applicable agreement for further details, at
- Info: https://fpgasoftware.intel.com/eula.
- Info: Processing started: Tue Mar 7 20:57:57 2023
-Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/ EqCmpDemo -c EqCmpDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file EqCmpDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim//" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 613 megabytes
- Info: Processing ended: Tue Mar 7 20:57:58 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.rpt b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.rpt
deleted file mode 100644
index 747b54c..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.rpt
+++ /dev/null
@@ -1,3102 +0,0 @@
-Fitter report for EqCmpDemo
-Tue Mar 7 20:55:13 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Tue Mar 7 20:55:13 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; EqCmpDemo ;
-; Top-level Entity Name ; EqCmpDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 3 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 3 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 73 / 529 ( 14 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+-------------------------+----------------+--------------+------------------+---------------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+-------------------------+----------------+--------------+------------------+---------------------+----------------+
-; Reserve Pin ; ; ; SW[0] ; AS INPUT TRI-STATED ; QSF Assignment ;
-; Reserve Pin ; ; ; SW[1] ; AS INPUT TRI-STATED ; QSF Assignment ;
-; Reserve Pin ; ; ; SW[2] ; AS INPUT TRI-STATED ; QSF Assignment ;
-; Reserve Pin ; ; ; SW[3] ; AS INPUT TRI-STATED ; QSF Assignment ;
-; Reserve Pin ; ; ; SW[4] ; AS INPUT TRI-STATED ; QSF Assignment ;
-; Reserve Pin ; ; ; SW[5] ; AS INPUT TRI-STATED ; QSF Assignment ;
-; Reserve Pin ; ; ; SW[6] ; AS INPUT TRI-STATED ; QSF Assignment ;
-; Reserve Pin ; ; ; SW[7] ; AS INPUT TRI-STATED ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
-; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
-; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
-; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
-; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
-; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
-; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
-; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
-; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[0] ; PIN_G19 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[1] ; PIN_F19 ; QSF Assignment ;
-; Location ; ; ; LEDR[2] ; PIN_E19 ; QSF Assignment ;
-; Location ; ; ; LEDR[3] ; PIN_F21 ; QSF Assignment ;
-; Location ; ; ; LEDR[4] ; PIN_F18 ; QSF Assignment ;
-; Location ; ; ; LEDR[5] ; PIN_E18 ; QSF Assignment ;
-; Location ; ; ; LEDR[6] ; PIN_J19 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_H19 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-; I/O Maximum Toggle Rate ; EqCmpDemo ; ; HEX0 ; 0 MHz ; QSF Assignment ;
-; I/O Maximum Toggle Rate ; EqCmpDemo ; ; HEX1 ; 0 MHz ; QSF Assignment ;
-; I/O Maximum Toggle Rate ; EqCmpDemo ; ; HEX2 ; 0 MHz ; QSF Assignment ;
-; I/O Maximum Toggle Rate ; EqCmpDemo ; ; HEX3[0] ; 0 MHz ; QSF Assignment ;
-; I/O Maximum Toggle Rate ; EqCmpDemo ; ; HEX3[1] ; 0 MHz ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; AUD_ADCLRCK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; AUD_BCLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; AUD_DACDAT ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; AUD_DACLRCK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; AUD_XCK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_BA[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_BA[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_CAS_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_CKE ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_CLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_CS_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQM[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQM[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQM[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQM[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[13] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[14] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[15] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[16] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[17] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[18] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[19] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[20] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[21] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[22] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[23] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[24] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[25] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[26] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[27] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[28] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[29] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[30] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[31] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_DQ[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_RAS_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; DRAM_WE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; EEP_I2C_SCLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; EEP_I2C_SDAT ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET0_GTX_CLK ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET0_MDC ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET0_RST_N ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET0_TX_DATA[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET0_TX_DATA[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET0_TX_DATA[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET0_TX_DATA[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET0_TX_EN ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET0_TX_ER ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET1_GTX_CLK ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET1_MDC ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET1_RST_N ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET1_TX_DATA[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET1_TX_DATA[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET1_TX_DATA[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET1_TX_DATA[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET1_TX_EN ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; ENET1_TX_ER ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; EX_IO[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; EX_IO[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; EX_IO[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; EX_IO[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; EX_IO[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; EX_IO[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; EX_IO[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[13] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[14] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[15] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[16] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[17] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[18] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[19] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[20] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[21] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[22] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_CE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_OE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_RST_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_WE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; FL_WP_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[13] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[14] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[15] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[16] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[17] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[18] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[19] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[20] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[21] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[22] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[23] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[24] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[25] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[26] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[27] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[28] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[29] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[30] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[31] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[32] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[33] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[34] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[35] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; GPIO[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX0[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX0[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX0[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX0[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX0[4] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX0[5] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX0[6] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX1[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX1[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX1[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX1[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX1[4] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX1[5] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX1[6] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX2[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX2[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX2[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX2[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX2[4] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX2[5] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX2[6] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX3[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX3[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX3[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX3[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX3[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX3[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX3[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX4[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX4[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX4[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX4[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX4[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX4[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX4[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX5[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX5[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX5[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX5[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX5[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX5[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX5[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX6[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX6[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX6[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX6[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX6[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX6[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX6[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX7[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX7[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX7[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX7[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX7[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX7[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HEX7[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_CLKIN_N1 ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_CLKIN_N2 ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_CLKIN_P1 ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_CLKIN_P2 ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_CLKOUT0 ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_CLKOUT_N1 ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_CLKOUT_N2 ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_CLKOUT_P1 ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_CLKOUT_P2 ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_D[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_D[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_D[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_D[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[0] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[10] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[11] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[12] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[13] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[14] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[15] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[16] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[1] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[2] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[3] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[4] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[5] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[6] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[7] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[8] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_N[9] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[0] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[10] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[11] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[12] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[13] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[14] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[15] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[16] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[1] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[2] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[3] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[4] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[5] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[6] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[7] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[8] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_RX_D_P[9] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[0] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[10] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[11] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[12] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[13] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[14] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[15] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[16] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[1] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[2] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[3] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[4] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[5] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[6] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[7] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[8] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_N[9] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[0] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[10] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[11] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[12] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[13] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[14] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[15] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[16] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[1] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[2] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[3] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[4] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[5] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[6] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[7] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[8] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; HSMC_TX_D_P[9] ; LVDS ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; I2C_SCLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; I2C_SDAT ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LCD_BLON ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LCD_DATA[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LCD_DATA[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LCD_DATA[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LCD_DATA[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LCD_DATA[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LCD_DATA[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LCD_DATA[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LCD_DATA[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LCD_EN ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LCD_ON ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LCD_RS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LCD_RW ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDG[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDG[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDG[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDG[4] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDG[5] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDG[6] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDG[7] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDG[8] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[0] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[10] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[11] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[12] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[13] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[14] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[15] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[16] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[17] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[1] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[2] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[3] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[4] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[5] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[6] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[7] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[8] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; LEDR[9] ; 2.5 V ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_CS_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[13] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[14] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[15] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DATA[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_DREQ[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_RD_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_RST_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; OTG_WR_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; PS2_CLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; PS2_CLK2 ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; PS2_DAT ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; PS2_DAT2 ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SD_CLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SD_CMD ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SD_DAT[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SD_DAT[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SD_DAT[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SD_DAT[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SMA_CLKOUT ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[13] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[14] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[15] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[16] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[17] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[18] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[19] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_CE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[10] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[11] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[12] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[13] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[14] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[15] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_DQ[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_LB_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_OE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_UB_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; SRAM_WE_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; TD_RESET_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; UART_CTS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; UART_TXD ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_BLANK_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_B[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_B[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_B[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_B[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_B[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_B[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_B[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_B[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_CLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_G[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_G[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_G[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_G[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_G[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_G[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_G[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_G[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_HS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_R[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_R[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_R[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_R[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_R[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_R[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_R[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_R[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_SYNC_N ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; EqCmpDemo ; ; VGA_VS ; 3.3-V LVTTL ; QSF Assignment ;
-+-------------------------+----------------+--------------+------------------+---------------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 160 ) ; 0.00 % ( 0 / 160 ) ; 0.00 % ( 0 / 160 ) ;
-; -- Achieved ; 0.00 % ( 0 / 160 ) ; 0.00 % ( 0 / 160 ) ; 0.00 % ( 0 / 160 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+--------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 22 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 138 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+-----------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-----------------------+
-; Total logic elements ; 3 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 3 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 2 ;
-; -- 3 input functions ; 0 ;
-; -- <=2 input functions ; 1 ;
-; -- Register only ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 3 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers* ; 0 / 117,053 ( 0 % ) ;
-; -- Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 1 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 73 / 529 ( 14 % ) ;
-; -- Clock pins ; 5 / 7 ( 71 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.1% / 0.0% / 0.3% ;
-; Maximum fan-out ; 1 ;
-; Highest non-global fan-out ; 1 ;
-; Total fan-out ; 89 ;
-; Average fan-out ; 0.56 ;
-+---------------------------------------------+-----------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 3 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 3 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 2 ; 0 ;
-; -- 3 input functions ; 0 ; 0 ;
-; -- <=2 input functions ; 1 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 3 ; 0 ;
-; -- arithmetic mode ; 0 ; 0 ;
-; ; ; ;
-; Total registers ; 0 ; 0 ;
-; -- Dedicated logic registers ; 0 / 114480 ( 0 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 1 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 9 ; 64 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 20 ; 69 ;
-; -- Registered Connections ; 0 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 8 ; 0 ;
-; -- Output Ports ; 1 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+----------------------+--------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; AUD_ADCDAT ; D2 ; 1 ; 0 ; 68 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; CLOCK2_50 ; AG14 ; 3 ; 58 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; CLOCK3_50 ; AG15 ; 4 ; 58 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; CLOCK_50 ; Y2 ; 2 ; 0 ; 36 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_INT_N ; A21 ; 7 ; 89 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_LINK100 ; C14 ; 8 ; 52 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; ENET0_MDIO ; B21 ; 7 ; 87 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_CLK ; A15 ; 7 ; 56 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_COL ; E15 ; 7 ; 58 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_CRS ; D15 ; 7 ; 58 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_DATA[0] ; C16 ; 7 ; 62 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_DATA[1] ; D16 ; 7 ; 62 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_DATA[2] ; D17 ; 7 ; 81 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_DATA[3] ; C15 ; 7 ; 58 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_DV ; C17 ; 7 ; 81 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_RX_ER ; D18 ; 7 ; 85 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET0_TX_CLK ; B17 ; 7 ; 60 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_INT_N ; D24 ; 7 ; 98 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_LINK100 ; D13 ; 8 ; 54 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; ENET1_MDIO ; D25 ; 7 ; 105 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_CLK ; B15 ; 7 ; 56 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_COL ; B22 ; 7 ; 89 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_CRS ; D20 ; 7 ; 85 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_DATA[0] ; B23 ; 7 ; 102 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_DATA[1] ; C21 ; 7 ; 91 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_DATA[2] ; A23 ; 7 ; 102 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_DATA[3] ; D21 ; 7 ; 96 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_DV ; A22 ; 7 ; 89 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_RX_ER ; C24 ; 7 ; 98 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENET1_TX_CLK ; C22 ; 7 ; 96 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; ENETCLK_25 ; A14 ; 8 ; 56 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; FL_RY ; Y1 ; 2 ; 0 ; 36 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; HSMC_CLKIN0 ; AH15 ; 4 ; 58 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; IRDA_RXD ; Y15 ; 3 ; 56 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; KEY[0] ; M23 ; 6 ; 115 ; 40 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; KEY[1] ; M21 ; 6 ; 115 ; 53 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; KEY[2] ; N21 ; 6 ; 115 ; 42 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; KEY[3] ; R24 ; 5 ; 115 ; 35 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; OTG_INT ; D5 ; 8 ; 3 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; SD_WP_N ; AF14 ; 3 ; 49 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; SMA_CLKIN ; AH14 ; 3 ; 58 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[10] ; AC24 ; 5 ; 115 ; 4 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[11] ; AB24 ; 5 ; 115 ; 5 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[12] ; AB23 ; 5 ; 115 ; 7 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[13] ; AA24 ; 5 ; 115 ; 9 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[14] ; AA23 ; 5 ; 115 ; 10 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[15] ; AA22 ; 5 ; 115 ; 6 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[16] ; Y24 ; 5 ; 115 ; 13 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[17] ; Y23 ; 5 ; 115 ; 14 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[3] ; AD27 ; 5 ; 115 ; 13 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[4] ; AB27 ; 5 ; 115 ; 18 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[5] ; AC26 ; 5 ; 115 ; 11 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[6] ; AD26 ; 5 ; 115 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[7] ; AB26 ; 5 ; 115 ; 15 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[8] ; AC25 ; 5 ; 115 ; 4 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[9] ; AB25 ; 5 ; 115 ; 16 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; TD_CLK27 ; B14 ; 8 ; 56 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[0] ; E8 ; 8 ; 11 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[1] ; A7 ; 8 ; 29 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[2] ; D8 ; 8 ; 16 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[3] ; C7 ; 8 ; 16 ; 73 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[4] ; D7 ; 8 ; 13 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[5] ; D6 ; 8 ; 13 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[6] ; E7 ; 8 ; 13 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_DATA[7] ; F7 ; 8 ; 9 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_HS ; E5 ; 8 ; 1 ; 73 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; TD_VS ; E4 ; 8 ; 1 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; UART_RTS ; J13 ; 8 ; 40 ; 73 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; UART_RXD ; G12 ; 8 ; 27 ; 73 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-+------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; LEDG[0] ; E21 ; 7 ; 107 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-; B22 ; DIFFIO_T53p, PADD0 ; Use as regular IO ; ENET1_RX_COL ; Dual Purpose Pin ;
-; D18 ; DIFFIO_T50p, PADD2 ; Use as regular IO ; ENET0_RX_ER ; Dual Purpose Pin ;
-; C17 ; DIFFIO_T46n, PADD3 ; Use as regular IO ; ENET0_RX_DV ; Dual Purpose Pin ;
-; D17 ; DIFFIO_T46p, PADD4, DQS2T/CQ3T,DPCLK8 ; Use as regular IO ; ENET0_RX_DATA[2] ; Dual Purpose Pin ;
-; C16 ; DIFFIO_T36n, PADD9 ; Use as regular IO ; ENET0_RX_DATA[0] ; Dual Purpose Pin ;
-; D16 ; DIFFIO_T36p, PADD10 ; Use as regular IO ; ENET0_RX_DATA[1] ; Dual Purpose Pin ;
-; B17 ; DIFFIO_T35p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO ; ENET0_TX_CLK ; Dual Purpose Pin ;
-; C15 ; DIFFIO_T32n, PADD13 ; Use as regular IO ; ENET0_RX_DATA[3] ; Dual Purpose Pin ;
-; D15 ; DIFFIO_T32p, PADD14 ; Use as regular IO ; ENET0_RX_CRS ; Dual Purpose Pin ;
-; C7 ; DIFFIO_T9n, DATA10 ; Use as regular IO ; TD_DATA[3] ; Dual Purpose Pin ;
-; D7 ; DIFFIO_T9p, DATA11 ; Use as regular IO ; TD_DATA[4] ; Dual Purpose Pin ;
-+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1 ; 5 / 56 ( 9 % ) ; 3.3V ; -- ;
-; 2 ; 2 / 63 ( 3 % ) ; 2.5V ; -- ;
-; 3 ; 4 / 73 ( 5 % ) ; 3.3V ; -- ;
-; 4 ; 2 / 71 ( 3 % ) ; 3.3V ; -- ;
-; 5 ; 19 / 65 ( 29 % ) ; 2.5V ; -- ;
-; 6 ; 4 / 58 ( 7 % ) ; 2.5V ; -- ;
-; 7 ; 25 / 72 ( 35 % ) ; 2.5V ; -- ;
-; 8 ; 17 / 71 ( 24 % ) ; 3.3V ; -- ;
-+----------+------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; TD_DATA[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; ENETCLK_25 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; A15 ; 470 ; 7 ; ENET0_RX_CLK ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; ENET0_INT_N ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; A22 ; 423 ; 7 ; ENET1_RX_DV ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; A23 ; 412 ; 7 ; ENET1_RX_DATA[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; SW[15] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA23 ; 280 ; 5 ; SW[14] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA24 ; 279 ; 5 ; SW[13] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; SW[12] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB24 ; 274 ; 5 ; SW[11] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB25 ; 292 ; 5 ; SW[9] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB26 ; 291 ; 5 ; SW[7] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB27 ; 296 ; 5 ; SW[4] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; SW[10] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC25 ; 272 ; 5 ; SW[8] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC26 ; 282 ; 5 ; SW[5] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; SW[6] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD27 ; 286 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; SD_WP_N ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; CLOCK2_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AG15 ; 201 ; 4 ; CLOCK3_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; SMA_CLKIN ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AH15 ; 202 ; 4 ; HSMC_CLKIN0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; TD_CLK27 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; B15 ; 471 ; 7 ; ENET1_RX_CLK ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; ENET0_TX_CLK ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; ENET0_MDIO ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; B22 ; 424 ; 7 ; ENET1_RX_COL ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; B23 ; 413 ; 7 ; ENET1_RX_DATA[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; TD_DATA[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; ENET0_LINK100 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; C15 ; 468 ; 7 ; ENET0_RX_DATA[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; C16 ; 460 ; 7 ; ENET0_RX_DATA[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; C17 ; 438 ; 7 ; ENET0_RX_DV ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; ENET1_RX_DATA[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; C22 ; 418 ; 7 ; ENET1_TX_CLK ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; ENET1_RX_ER ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; AUD_ADCDAT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; OTG_INT ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; D6 ; 524 ; 8 ; TD_DATA[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; D7 ; 522 ; 8 ; TD_DATA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; D8 ; 520 ; 8 ; TD_DATA[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; ENET1_LINK100 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; ENET0_RX_CRS ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D16 ; 461 ; 7 ; ENET0_RX_DATA[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D17 ; 439 ; 7 ; ENET0_RX_DATA[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D18 ; 430 ; 7 ; ENET0_RX_ER ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; ENET1_RX_CRS ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D21 ; 419 ; 7 ; ENET1_RX_DATA[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; ENET1_INT_N ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D25 ; 410 ; 7 ; ENET1_MDIO ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; TD_VS ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; E5 ; 542 ; 8 ; TD_HS ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; TD_DATA[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; E8 ; 526 ; 8 ; TD_DATA[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; ENET0_RX_COL ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; LEDG[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; TD_DATA[7] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; UART_RXD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; UART_RTS ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; KEY[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; KEY[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; KEY[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; FL_RY ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; Y2 ; 65 ; 2 ; CLOCK_50 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; IRDA_RXD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; SW[17] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y24 ; 287 ; 5 ; SW[16] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-------------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+--------------------------------------+
-; Pin Name ; Reason ;
-+----------+--------------------------------------+
-; LEDG[0] ; Missing drive strength and slew rate ;
-+----------+--------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+-------------+--------------+
-; |EqCmpDemo ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 73 ; 0 ; 3 (0) ; 0 (0) ; 0 (0) ; |EqCmpDemo ; EqCmpDemo ; work ;
-; |EqCmp4:inst1| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |EqCmpDemo|EqCmp4:inst1 ; EqCmp4 ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-----------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; LEDG[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[4] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[7] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[3] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+----------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+----------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+----------------------------+-------------------+---------+
-; SW[4] ; ; ;
-; - EqCmp4:inst1|inst~0 ; 0 ; 6 ;
-; SW[5] ; ; ;
-; - EqCmp4:inst1|inst~0 ; 0 ; 6 ;
-; SW[1] ; ; ;
-; - EqCmp4:inst1|inst~0 ; 0 ; 6 ;
-; SW[0] ; ; ;
-; - EqCmp4:inst1|inst~0 ; 0 ; 6 ;
-; SW[6] ; ; ;
-; - EqCmp4:inst1|inst~1 ; 0 ; 6 ;
-; SW[7] ; ; ;
-; - EqCmp4:inst1|inst~1 ; 1 ; 6 ;
-; SW[3] ; ; ;
-; - EqCmp4:inst1|inst~1 ; 0 ; 6 ;
-; SW[2] ; ; ;
-; - EqCmp4:inst1|inst~1 ; 0 ; 6 ;
-+----------------------------+-------------------+---------+
-
-
-+------------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+------------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+------------------------+
-; Block interconnects ; 9 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 0 / 10,120 ( 0 % ) ;
-; C4 interconnects ; 22 / 209,544 ( < 1 % ) ;
-; Direct links ; 0 / 342,891 ( 0 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 2 / 119,088 ( < 1 % ) ;
-; R24 interconnects ; 0 / 9,963 ( 0 % ) ;
-; R4 interconnects ; 2 / 289,782 ( < 1 % ) ;
-+-----------------------+------------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 3.00) ; Number of LABs (Total = 1) ;
-+--------------------------------------------+-----------------------------+
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-+--------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 3.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 1) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 1 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 8.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+---------------------------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+---------------------------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; 22 I/O(s) were assigned a toggle rate ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; 22 I/O(s) were assigned a toggle rate ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+---------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 9 ; 9 ; 0 ; 0 ; 73 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 72 ; 1 ; 0 ; 72 ; 0 ; 0 ; 1 ; 0 ; 73 ; 73 ; 73 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 73 ; 64 ; 64 ; 73 ; 73 ; 0 ; 64 ; 73 ; 73 ; 73 ; 73 ; 73 ; 73 ; 72 ; 73 ; 73 ; 73 ; 1 ; 72 ; 73 ; 1 ; 73 ; 73 ; 72 ; 73 ; 0 ; 0 ; 0 ; 73 ; 73 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; LEDG[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; AUD_ADCDAT ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; CLOCK2_50 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; CLOCK3_50 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; CLOCK_50 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_INT_N ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_LINK100 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_MDIO ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_CLK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_COL ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_CRS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_DATA[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_DATA[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_DATA[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_DATA[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_DV ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_RX_ER ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET0_TX_CLK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_INT_N ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_LINK100 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_MDIO ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_CLK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_COL ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_CRS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_DATA[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_DATA[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_DATA[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_DATA[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_DV ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_RX_ER ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENET1_TX_CLK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; ENETCLK_25 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; FL_RY ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HSMC_CLKIN0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; IRDA_RXD ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; OTG_INT ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SD_WP_N ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SMA_CLKIN ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[16] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[17] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_CLK27 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_DATA[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_HS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; TD_VS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; UART_RTS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; UART_RXD ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "EqCmpDemo"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Warning (169133): Can't reserve pin AUD_ADCDAT -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin CLOCK2_50 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin CLOCK3_50 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin CLOCK_50 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_INT_N -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_LINK100 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_MDIO -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_CLK -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_COL -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_CRS -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_DATA[0] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_DATA[1] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_DATA[2] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_DATA[3] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_DV -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_RX_ER -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET0_TX_CLK -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_INT_N -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_LINK100 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_MDIO -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_CLK -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_COL -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_CRS -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_DATA[0] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_DATA[1] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_DATA[2] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_DATA[3] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_DV -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_RX_ER -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENET1_TX_CLK -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin ENETCLK_25 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin FL_RY -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin HSMC_CLKIN0 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin IRDA_RXD -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin KEY[0] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin KEY[1] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin KEY[2] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin KEY[3] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin OTG_INT -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SD_WP_N -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SMA_CLKIN -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[0] -- pin name is an illegal or unsupported format
-Warning (169140): Reserve pin assignment ignored because of existing pin with name "SW[0]"
-Warning (169133): Can't reserve pin SW[10] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[11] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[12] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[13] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[14] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[15] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[16] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[17] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[1] -- pin name is an illegal or unsupported format
-Warning (169140): Reserve pin assignment ignored because of existing pin with name "SW[1]"
-Warning (169133): Can't reserve pin SW[2] -- pin name is an illegal or unsupported format
-Warning (169140): Reserve pin assignment ignored because of existing pin with name "SW[2]"
-Warning (169133): Can't reserve pin SW[3] -- pin name is an illegal or unsupported format
-Warning (169140): Reserve pin assignment ignored because of existing pin with name "SW[3]"
-Warning (169133): Can't reserve pin SW[4] -- pin name is an illegal or unsupported format
-Warning (169140): Reserve pin assignment ignored because of existing pin with name "SW[4]"
-Warning (169133): Can't reserve pin SW[5] -- pin name is an illegal or unsupported format
-Warning (169140): Reserve pin assignment ignored because of existing pin with name "SW[5]"
-Warning (169133): Can't reserve pin SW[6] -- pin name is an illegal or unsupported format
-Warning (169140): Reserve pin assignment ignored because of existing pin with name "SW[6]"
-Warning (169133): Can't reserve pin SW[7] -- pin name is an illegal or unsupported format
-Warning (169140): Reserve pin assignment ignored because of existing pin with name "SW[7]"
-Warning (169133): Can't reserve pin SW[8] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin SW[9] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_CLK27 -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[0] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[1] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[2] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[3] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[4] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[5] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[6] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_DATA[7] -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_HS -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin TD_VS -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin UART_RTS -- pin name is an illegal or unsupported format
-Warning (169133): Can't reserve pin UART_RXD -- pin name is an illegal or unsupported format
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'EqCmpDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Warning (169177): 25 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
- Info (169178): Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D2
- Info (169178): Pin CLOCK2_50 uses I/O standard 3.3-V LVTTL at AG14
- Info (169178): Pin CLOCK3_50 uses I/O standard 3.3-V LVTTL at AG15
- Info (169178): Pin ENET0_LINK100 uses I/O standard 3.3-V LVTTL at C14
- Info (169178): Pin ENET1_LINK100 uses I/O standard 3.3-V LVTTL at D13
- Info (169178): Pin ENETCLK_25 uses I/O standard 3.3-V LVTTL at A14
- Info (169178): Pin FL_RY uses I/O standard 3.3-V LVTTL at Y1
- Info (169178): Pin HSMC_CLKIN0 uses I/O standard 3.3-V LVTTL at AH15
- Info (169178): Pin IRDA_RXD uses I/O standard 3.3-V LVTTL at Y15
- Info (169178): Pin OTG_INT uses I/O standard 3.3-V LVTTL at D5
- Info (169178): Pin SD_WP_N uses I/O standard 3.3-V LVTTL at AF14
- Info (169178): Pin SMA_CLKIN uses I/O standard 3.3-V LVTTL at AH14
- Info (169178): Pin TD_CLK27 uses I/O standard 3.3-V LVTTL at B14
- Info (169178): Pin TD_DATA[0] uses I/O standard 3.3-V LVTTL at E8
- Info (169178): Pin TD_DATA[1] uses I/O standard 3.3-V LVTTL at A7
- Info (169178): Pin TD_DATA[2] uses I/O standard 3.3-V LVTTL at D8
- Info (169178): Pin TD_DATA[3] uses I/O standard 3.3-V LVTTL at C7
- Info (169178): Pin TD_DATA[4] uses I/O standard 3.3-V LVTTL at D7
- Info (169178): Pin TD_DATA[5] uses I/O standard 3.3-V LVTTL at D6
- Info (169178): Pin TD_DATA[6] uses I/O standard 3.3-V LVTTL at E7
- Info (169178): Pin TD_DATA[7] uses I/O standard 3.3-V LVTTL at F7
- Info (169178): Pin TD_HS uses I/O standard 3.3-V LVTTL at E5
- Info (169178): Pin TD_VS uses I/O standard 3.3-V LVTTL at E4
- Info (169178): Pin UART_RTS uses I/O standard 3.3-V LVTTL at J13
- Info (169178): Pin UART_RXD uses I/O standard 3.3-V LVTTL at G12
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 534 warnings
- Info: Peak virtual memory: 1157 megabytes
- Info: Processing ended: Tue Mar 7 20:55:13 2023
- Info: Elapsed time: 00:00:10
- Info: Total CPU time (on all processors): 00:00:15
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.summary b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.summary
deleted file mode 100644
index 49dc7e3..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Tue Mar 7 20:55:13 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : EqCmpDemo
-Top-level Entity Name : EqCmpDemo
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 3 / 114,480 ( < 1 % )
- Total combinational functions : 3 / 114,480 ( < 1 % )
- Dedicated logic registers : 0 / 114,480 ( 0 % )
-Total registers : 0
-Total pins : 73 / 529 ( 14 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.flow.rpt b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.flow.rpt
deleted file mode 100644
index 2c4a393..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.flow.rpt
+++ /dev/null
@@ -1,142 +0,0 @@
-Flow report for EqCmpDemo
-Tue Mar 7 20:57:58 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Tue Mar 7 20:57:58 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; EqCmpDemo ;
-; Top-level Entity Name ; EqCmpDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 3 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 3 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 73 / 529 ( 14 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/07/2023 20:54:55 ;
-; Main task ; Compilation ;
-; Revision Name ; EqCmpDemo ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 2690080394329.167822249510628 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 433 MB ; 00:00:20 ;
-; Fitter ; 00:00:10 ; 1.0 ; 1157 MB ; 00:00:15 ;
-; Assembler ; 00:00:03 ; 1.0 ; 366 MB ; 00:00:03 ;
-; Timing Analyzer ; 00:00:01 ; 1.0 ; 534 MB ; 00:00:01 ;
-; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 612 MB ; 00:00:00 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 609 MB ; 00:00:00 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 613 MB ; 00:00:00 ;
-; Total ; 00:00:25 ; -- ; -- ; 00:00:39 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo
-quartus_fit --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo
-quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo
-quartus_sta EqCmpDemo -c EqCmpDemo
-quartus_eda --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht
-quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/ EqCmpDemo -c EqCmpDemo
-
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.jdi b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.jdi
deleted file mode 100644
index f6e5b11..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.rpt b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.rpt
deleted file mode 100644
index e7e75bd..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.rpt
+++ /dev/null
@@ -1,290 +0,0 @@
-Analysis & Synthesis report for EqCmpDemo
-Tue Mar 7 20:55:03 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Post-Synthesis Netlist Statistics for Top Partition
- 10. Elapsed Time Per Partition
- 11. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Tue Mar 7 20:55:03 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; EqCmpDemo ;
-; Top-level Entity Name ; EqCmpDemo ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 3 ;
-; Total combinational functions ; 3 ;
-; Dedicated logic registers ; 0 ;
-; Total registers ; 0 ;
-; Total pins ; 9 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; EqCmpDemo ; EqCmpDemo ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
-; EqCmp4.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.bdf ; ;
-; EqCmpDemo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf ; ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
-
-
-+-------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+---------------------+
-; Resource ; Usage ;
-+---------------------------------------------+---------------------+
-; Estimated Total logic elements ; 3 ;
-; ; ;
-; Total combinational functions ; 3 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 2 ;
-; -- 3 input functions ; 0 ;
-; -- <=2 input functions ; 1 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 3 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers ; 0 ;
-; -- Dedicated logic registers ; 0 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 9 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; EqCmp4:inst1|inst~0 ;
-; Maximum fan-out ; 1 ;
-; Total fan-out ; 20 ;
-; Average fan-out ; 0.95 ;
-+---------------------------------------------+---------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+-------------+--------------+
-; |EqCmpDemo ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 9 ; 0 ; |EqCmpDemo ; EqCmpDemo ; work ;
-; |EqCmp4:inst1| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |EqCmpDemo|EqCmp4:inst1 ; EqCmp4 ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 0 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 9 ;
-; cycloneiii_lcell_comb ; 3 ;
-; normal ; 3 ;
-; 2 data inputs ; 1 ;
-; 4 data inputs ; 2 ;
-; ; ;
-; Max LUT depth ; 2.00 ;
-; Average LUT depth ; 2.00 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 20:54:54 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file EqCmp4.bdf
- Info (12023): Found entity 1: EqCmp4
-Info (12021): Found 1 design units, including 1 entities, in source file EqCmpDemo.bdf
- Info (12023): Found entity 1: EqCmpDemo
-Info (12021): Found 2 design units, including 1 entities, in source file EqCmp8.vhd
- Info (12022): Found design unit 1: EqCmp8-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd Line: 13
- Info (12023): Found entity 1: EqCmp8 File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd Line: 4
-Info (12127): Elaborating entity "EqCmpDemo" for the top level hierarchy
-Info (12128): Elaborating entity "EqCmp4" for hierarchy "EqCmp4:inst1"
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 12 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 8 input pins
- Info (21059): Implemented 1 output pins
- Info (21061): Implemented 3 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 433 megabytes
- Info: Processing ended: Tue Mar 7 20:55:03 2023
- Info: Elapsed time: 00:00:09
- Info: Total CPU time (on all processors): 00:00:20
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.summary b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.summary
deleted file mode 100644
index c58dcd9..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Tue Mar 7 20:55:03 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : EqCmpDemo
-Top-level Entity Name : EqCmpDemo
-Family : Cyclone IV E
-Total logic elements : 3
- Total combinational functions : 3
- Dedicated logic registers : 0
-Total registers : 0
-Total pins : 9
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.pin b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.pin
deleted file mode 100644
index 5d0558b..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 3.3V
- -- Bank 2: 2.5V
- -- Bank 3: 3.3V
- -- Bank 4: 3.3V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 3.3V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "EqCmpDemo" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 3.3V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 3.3V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-TD_DATA[1] : A7 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 3.3V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 3.3V : 8 :
-ENETCLK_25 : A14 : input : 3.3-V LVTTL : : 8 : Y
-ENET0_RX_CLK : A15 : input : 2.5 V : : 7 : Y
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-ENET0_INT_N : A21 : input : 2.5 V : : 7 : Y
-ENET1_RX_DV : A22 : input : 2.5 V : : 7 : Y
-ENET1_RX_DATA[2] : A23 : input : 2.5 V : : 7 : Y
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-SW[15] : AA22 : input : 2.5 V : : 5 : Y
-SW[14] : AA23 : input : 2.5 V : : 5 : Y
-SW[13] : AA24 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-SW[12] : AB23 : input : 2.5 V : : 5 : Y
-SW[11] : AB24 : input : 2.5 V : : 5 : Y
-SW[9] : AB25 : input : 2.5 V : : 5 : Y
-SW[7] : AB26 : input : 2.5 V : : 5 : Y
-SW[4] : AB27 : input : 2.5 V : : 5 : Y
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-SW[10] : AC24 : input : 2.5 V : : 5 : Y
-SW[8] : AC25 : input : 2.5 V : : 5 : Y
-SW[5] : AC26 : input : 2.5 V : : 5 : Y
-SW[2] : AC27 : input : 2.5 V : : 5 : Y
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-SW[6] : AD26 : input : 2.5 V : : 5 : Y
-SW[3] : AD27 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-SD_WP_N : AF14 : input : 3.3-V LVTTL : : 3 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-CLOCK2_50 : AG14 : input : 3.3-V LVTTL : : 3 : Y
-CLOCK3_50 : AG15 : input : 3.3-V LVTTL : : 4 : Y
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 3.3V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 3.3V : 3 :
-SMA_CLKIN : AH14 : input : 3.3-V LVTTL : : 3 : Y
-HSMC_CLKIN0 : AH15 : input : 3.3-V LVTTL : : 4 : Y
-VCCIO4 : AH16 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 3.3V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 3.3V : 4 :
-VCCIO1 : B1 : power : : 3.3V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-TD_CLK27 : B14 : input : 3.3-V LVTTL : : 8 : Y
-ENET1_RX_CLK : B15 : input : 2.5 V : : 7 : Y
-GND : B16 : gnd : : : :
-ENET0_TX_CLK : B17 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-ENET0_MDIO : B21 : input : 2.5 V : : 7 : Y
-ENET1_RX_COL : B22 : input : 2.5 V : : 7 : Y
-ENET1_RX_DATA[0] : B23 : input : 2.5 V : : 7 : Y
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-TD_DATA[3] : C7 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-ENET0_LINK100 : C14 : input : 3.3-V LVTTL : : 8 : Y
-ENET0_RX_DATA[3] : C15 : input : 2.5 V : : 7 : Y
-ENET0_RX_DATA[0] : C16 : input : 2.5 V : : 7 : Y
-ENET0_RX_DV : C17 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-ENET1_RX_DATA[1] : C21 : input : 2.5 V : : 7 : Y
-ENET1_TX_CLK : C22 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-ENET1_RX_ER : C24 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-AUD_ADCDAT : D2 : input : 3.3-V LVTTL : : 1 : Y
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-OTG_INT : D5 : input : 3.3-V LVTTL : : 8 : Y
-TD_DATA[5] : D6 : input : 3.3-V LVTTL : : 8 : Y
-TD_DATA[4] : D7 : input : 3.3-V LVTTL : : 8 : Y
-TD_DATA[2] : D8 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-ENET1_LINK100 : D13 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-ENET0_RX_CRS : D15 : input : 2.5 V : : 7 : Y
-ENET0_RX_DATA[1] : D16 : input : 2.5 V : : 7 : Y
-ENET0_RX_DATA[2] : D17 : input : 2.5 V : : 7 : Y
-ENET0_RX_ER : D18 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-ENET1_RX_CRS : D20 : input : 2.5 V : : 7 : Y
-ENET1_RX_DATA[3] : D21 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-ENET1_INT_N : D24 : input : 2.5 V : : 7 : Y
-ENET1_MDIO : D25 : input : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 3.3-V LVTTL : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-TD_VS : E4 : input : 3.3-V LVTTL : : 8 : Y
-TD_HS : E5 : input : 3.3-V LVTTL : : 8 : Y
-VCCIO8 : E6 : power : : 3.3V : 8 :
-TD_DATA[6] : E7 : input : 3.3-V LVTTL : : 8 : Y
-TD_DATA[0] : E8 : input : 3.3-V LVTTL : : 8 : Y
-VCCIO8 : E9 : power : : 3.3V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 3.3V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-ENET0_RX_COL : E15 : input : 2.5 V : : 7 : Y
-VCCIO7 : E16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7 :
-VCCIO7 : E20 : power : : 2.5V : 7 :
-LEDG[0] : E21 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
-VCCIO7 : E23 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 3.3-V LVTTL : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-TD_DATA[7] : F7 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7 :
-GND : F20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-UART_RXD : G12 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 3.3V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 3.3V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
-VCCIO7 : H18 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-UART_RTS : J13 : input : 3.3-V LVTTL : : 8 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7 :
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 3.3V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-KEY[1] : M21 : input : 2.5 V : : 6 : Y
-MSEL2 : M22 : : : : 6 :
-KEY[0] : M23 : input : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 3.3V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 3.3V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 3.3-V LVTTL : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-KEY[2] : N21 : input : 2.5 V : : 6 : Y
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 3.3-V LVTTL : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-KEY[3] : R24 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-FL_RY : Y1 : input : 3.3-V LVTTL : : 2 : Y
-CLOCK_50 : Y2 : input : 2.5 V : : 2 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-IRDA_RXD : Y15 : input : 3.3-V LVTTL : : 3 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-SW[17] : Y23 : input : 2.5 V : : 5 : Y
-SW[16] : Y24 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sld b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sta.rpt b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sta.rpt
deleted file mode 100644
index 4f64170..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sta.rpt
+++ /dev/null
@@ -1,513 +0,0 @@
-Timing Analyzer report for EqCmpDemo
-Tue Mar 7 20:55:18 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Unconstrained Input Ports
- 37. Unconstrained Output Ports
- 38. Unconstrained Input Ports
- 39. Unconstrained Output Ports
- 40. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; EqCmpDemo ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.2% ;
-+----------------------------+-------------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; AUD_ADCDAT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; CLOCK2_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; CLOCK3_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; CLOCK_50 ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_INT_N ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_LINK100 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; ENET0_MDIO ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_CLK ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_COL ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_CRS ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_DATA[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_DATA[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_DATA[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_DATA[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_DV ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_RX_ER ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET0_TX_CLK ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_INT_N ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_LINK100 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; ENET1_MDIO ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_CLK ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_COL ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_CRS ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_DATA[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_DATA[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_DATA[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_DATA[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_DV ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_RX_ER ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENET1_TX_CLK ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ENETCLK_25 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; FL_RY ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; HSMC_CLKIN0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; IRDA_RXD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; OTG_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; SD_WP_N ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; SMA_CLKIN ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; SW[10] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[11] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[12] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[13] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[14] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[15] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[16] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[17] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; TD_CLK27 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_DATA[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_HS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; TD_VS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; UART_RTS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; UART_RXD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.73e-09 V ; 3.19 V ; -0.173 V ; 0.151 V ; 0.259 V ; 2.79e-10 s ; 2.42e-10 s ; Yes ; Yes ; 3.08 V ; 5.73e-09 V ; 3.19 V ; -0.173 V ; 0.151 V ; 0.259 V ; 2.79e-10 s ; 2.42e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 8 ; 8 ;
-; Unconstrained Input Port Paths ; 8 ; 8 ;
-; Unconstrained Output Ports ; 1 ; 1 ;
-; Unconstrained Output Port Paths ; 8 ; 8 ;
-+---------------------------------+-------+------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 20:55:17 2023
-Info: Command: quartus_sta EqCmpDemo -c EqCmpDemo
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'EqCmpDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 534 megabytes
- Info: Processing ended: Tue Mar 7 20:55:18 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sta.summary b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sta.summary
deleted file mode 100644
index aa5b327..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo.sft b/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo.vho b/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo.vho
deleted file mode 100644
index 0d06772..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo.vho
+++ /dev/null
@@ -1,477 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/07/2023 20:55:19"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- AUD_ADCDAT => Location: PIN_D2, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- CLOCK2_50 => Location: PIN_AG14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- CLOCK3_50 => Location: PIN_AG15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- CLOCK_50 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_INT_N => Location: PIN_A21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_LINK100 => Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ENET0_MDIO => Location: PIN_B21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_CLK => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_COL => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_CRS => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[0] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[1] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[2] => Location: PIN_D17, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[3] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DV => Location: PIN_C17, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_ER => Location: PIN_D18, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_TX_CLK => Location: PIN_B17, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_INT_N => Location: PIN_D24, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_LINK100 => Location: PIN_D13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ENET1_MDIO => Location: PIN_D25, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_CLK => Location: PIN_B15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_COL => Location: PIN_B22, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_CRS => Location: PIN_D20, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[0] => Location: PIN_B23, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[1] => Location: PIN_C21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[2] => Location: PIN_A23, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[3] => Location: PIN_D21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DV => Location: PIN_A22, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_ER => Location: PIN_C24, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_TX_CLK => Location: PIN_C22, I/O Standard: 2.5 V, Current Strength: Default
--- ENETCLK_25 => Location: PIN_A14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- FL_RY => Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- HSMC_CLKIN0 => Location: PIN_AH15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- IRDA_RXD => Location: PIN_Y15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[2] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[3] => Location: PIN_R24, I/O Standard: 2.5 V, Current Strength: Default
--- OTG_INT => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- SD_WP_N => Location: PIN_AF14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- SMA_CLKIN => Location: PIN_AH14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- SW[10] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[11] => Location: PIN_AB24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[12] => Location: PIN_AB23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[13] => Location: PIN_AA24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[14] => Location: PIN_AA23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[15] => Location: PIN_AA22, I/O Standard: 2.5 V, Current Strength: Default
--- SW[16] => Location: PIN_Y24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[17] => Location: PIN_Y23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default
--- SW[9] => Location: PIN_AB25, I/O Standard: 2.5 V, Current Strength: Default
--- TD_CLK27 => Location: PIN_B14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[0] => Location: PIN_E8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[1] => Location: PIN_A7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[2] => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[3] => Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[4] => Location: PIN_D7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[5] => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[6] => Location: PIN_E7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[7] => Location: PIN_F7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_HS => Location: PIN_E5, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_VS => Location: PIN_E4, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- UART_RTS => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- UART_RXD => Location: PIN_G12, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \AUD_ADCDAT~padout\ : std_logic;
-SIGNAL \CLOCK2_50~padout\ : std_logic;
-SIGNAL \CLOCK3_50~padout\ : std_logic;
-SIGNAL \CLOCK_50~padout\ : std_logic;
-SIGNAL \ENET0_INT_N~padout\ : std_logic;
-SIGNAL \ENET0_LINK100~padout\ : std_logic;
-SIGNAL \ENET0_MDIO~padout\ : std_logic;
-SIGNAL \ENET0_RX_CLK~padout\ : std_logic;
-SIGNAL \ENET0_RX_COL~padout\ : std_logic;
-SIGNAL \ENET0_RX_CRS~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[0]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[1]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[2]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[3]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DV~padout\ : std_logic;
-SIGNAL \ENET0_RX_ER~padout\ : std_logic;
-SIGNAL \ENET0_TX_CLK~padout\ : std_logic;
-SIGNAL \ENET1_INT_N~padout\ : std_logic;
-SIGNAL \ENET1_LINK100~padout\ : std_logic;
-SIGNAL \ENET1_MDIO~padout\ : std_logic;
-SIGNAL \ENET1_RX_CLK~padout\ : std_logic;
-SIGNAL \ENET1_RX_COL~padout\ : std_logic;
-SIGNAL \ENET1_RX_CRS~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[0]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[1]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[2]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[3]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DV~padout\ : std_logic;
-SIGNAL \ENET1_RX_ER~padout\ : std_logic;
-SIGNAL \ENET1_TX_CLK~padout\ : std_logic;
-SIGNAL \ENETCLK_25~padout\ : std_logic;
-SIGNAL \FL_RY~padout\ : std_logic;
-SIGNAL \HSMC_CLKIN0~padout\ : std_logic;
-SIGNAL \IRDA_RXD~padout\ : std_logic;
-SIGNAL \KEY[0]~padout\ : std_logic;
-SIGNAL \KEY[1]~padout\ : std_logic;
-SIGNAL \KEY[2]~padout\ : std_logic;
-SIGNAL \KEY[3]~padout\ : std_logic;
-SIGNAL \OTG_INT~padout\ : std_logic;
-SIGNAL \SD_WP_N~padout\ : std_logic;
-SIGNAL \SMA_CLKIN~padout\ : std_logic;
-SIGNAL \TD_CLK27~padout\ : std_logic;
-SIGNAL \TD_DATA[0]~padout\ : std_logic;
-SIGNAL \TD_DATA[1]~padout\ : std_logic;
-SIGNAL \TD_DATA[2]~padout\ : std_logic;
-SIGNAL \TD_DATA[3]~padout\ : std_logic;
-SIGNAL \TD_DATA[4]~padout\ : std_logic;
-SIGNAL \TD_DATA[5]~padout\ : std_logic;
-SIGNAL \TD_DATA[6]~padout\ : std_logic;
-SIGNAL \TD_DATA[7]~padout\ : std_logic;
-SIGNAL \TD_HS~padout\ : std_logic;
-SIGNAL \TD_VS~padout\ : std_logic;
-SIGNAL \UART_RTS~padout\ : std_logic;
-SIGNAL \UART_RXD~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \AUD_ADCDAT~ibuf_o\ : std_logic;
-SIGNAL \CLOCK2_50~ibuf_o\ : std_logic;
-SIGNAL \CLOCK3_50~ibuf_o\ : std_logic;
-SIGNAL \CLOCK_50~ibuf_o\ : std_logic;
-SIGNAL \ENET0_INT_N~ibuf_o\ : std_logic;
-SIGNAL \ENET0_LINK100~ibuf_o\ : std_logic;
-SIGNAL \ENET0_MDIO~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_COL~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_CRS~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[0]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[1]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[2]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[3]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DV~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_ER~ibuf_o\ : std_logic;
-SIGNAL \ENET0_TX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENET1_INT_N~ibuf_o\ : std_logic;
-SIGNAL \ENET1_LINK100~ibuf_o\ : std_logic;
-SIGNAL \ENET1_MDIO~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_COL~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_CRS~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[0]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[1]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[2]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[3]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DV~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_ER~ibuf_o\ : std_logic;
-SIGNAL \ENET1_TX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENETCLK_25~ibuf_o\ : std_logic;
-SIGNAL \FL_RY~ibuf_o\ : std_logic;
-SIGNAL \HSMC_CLKIN0~ibuf_o\ : std_logic;
-SIGNAL \IRDA_RXD~ibuf_o\ : std_logic;
-SIGNAL \KEY[0]~ibuf_o\ : std_logic;
-SIGNAL \KEY[1]~ibuf_o\ : std_logic;
-SIGNAL \KEY[2]~ibuf_o\ : std_logic;
-SIGNAL \KEY[3]~ibuf_o\ : std_logic;
-SIGNAL \OTG_INT~ibuf_o\ : std_logic;
-SIGNAL \SD_WP_N~ibuf_o\ : std_logic;
-SIGNAL \SMA_CLKIN~ibuf_o\ : std_logic;
-SIGNAL \SW[10]~ibuf_o\ : std_logic;
-SIGNAL \SW[11]~ibuf_o\ : std_logic;
-SIGNAL \SW[12]~ibuf_o\ : std_logic;
-SIGNAL \SW[13]~ibuf_o\ : std_logic;
-SIGNAL \SW[14]~ibuf_o\ : std_logic;
-SIGNAL \SW[15]~ibuf_o\ : std_logic;
-SIGNAL \SW[16]~ibuf_o\ : std_logic;
-SIGNAL \SW[17]~ibuf_o\ : std_logic;
-SIGNAL \SW[8]~ibuf_o\ : std_logic;
-SIGNAL \SW[9]~ibuf_o\ : std_logic;
-SIGNAL \TD_CLK27~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[0]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[1]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[2]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[3]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[4]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[5]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[6]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[7]~ibuf_o\ : std_logic;
-SIGNAL \TD_HS~ibuf_o\ : std_logic;
-SIGNAL \TD_VS~ibuf_o\ : std_logic;
-SIGNAL \UART_RTS~ibuf_o\ : std_logic;
-SIGNAL \UART_RXD~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-SIGNAL SW : std_logic_vector(7 DOWNTO 0);
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY EqCmpDemo IS
- PORT (
- LEDG : OUT std_logic_vector(0 DOWNTO 0);
- SW : IN std_logic_vector(7 DOWNTO 0)
- );
-END EqCmpDemo;
-
--- Design Ports Information
--- LEDG[0] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default
--- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF EqCmpDemo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDG : std_logic_vector(0 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(7 DOWNTO 0);
-SIGNAL \LEDG[0]~output_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \SW[5]~input_o\ : std_logic;
-SIGNAL \SW[4]~input_o\ : std_logic;
-SIGNAL \inst1|inst~0_combout\ : std_logic;
-SIGNAL \SW[7]~input_o\ : std_logic;
-SIGNAL \SW[6]~input_o\ : std_logic;
-SIGNAL \SW[3]~input_o\ : std_logic;
-SIGNAL \SW[2]~input_o\ : std_logic;
-SIGNAL \inst1|inst~1_combout\ : std_logic;
-SIGNAL \inst1|inst~combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-LEDG <= ww_LEDG;
-ww_SW <= SW;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X107_Y73_N9
-\LEDG[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst1|inst~combout\,
- devoe => ww_devoe,
- o => \LEDG[0]~output_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: IOIBUF_X115_Y11_N8
-\SW[5]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(5),
- o => \SW[5]~input_o\);
-
--- Location: IOIBUF_X115_Y18_N8
-\SW[4]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(4),
- o => \SW[4]~input_o\);
-
--- Location: LCCOMB_X114_Y15_N24
-\inst1|inst~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|inst~0_combout\ = (\SW[1]~input_o\ & (\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\)))) # (!\SW[1]~input_o\ & (!\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000010000100001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[1]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[5]~input_o\,
- datad => \SW[4]~input_o\,
- combout => \inst1|inst~0_combout\);
-
--- Location: IOIBUF_X115_Y15_N1
-\SW[7]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(7),
- o => \SW[7]~input_o\);
-
--- Location: IOIBUF_X115_Y10_N1
-\SW[6]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(6),
- o => \SW[6]~input_o\);
-
--- Location: IOIBUF_X115_Y13_N8
-\SW[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(3),
- o => \SW[3]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N8
-\SW[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(2),
- o => \SW[2]~input_o\);
-
--- Location: LCCOMB_X114_Y15_N10
-\inst1|inst~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|inst~1_combout\ = (\SW[7]~input_o\ & (\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\)))) # (!\SW[7]~input_o\ & (!\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000010000100001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[7]~input_o\,
- datab => \SW[6]~input_o\,
- datac => \SW[3]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \inst1|inst~1_combout\);
-
--- Location: LCCOMB_X114_Y15_N28
-\inst1|inst\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|inst~combout\ = (\inst1|inst~0_combout\ & \inst1|inst~1_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100110000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|inst~0_combout\,
- datad => \inst1|inst~1_combout\,
- combout => \inst1|inst~combout\);
-
-ww_LEDG(0) <= \LEDG[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo_modelsim.xrf
deleted file mode 100644
index c16151c..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo_modelsim.xrf
+++ /dev/null
@@ -1,24 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.bdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vwf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cbx.xml
-design_name = hard_block
-design_name = EqCmpDemo
-instance = comp, \LEDG[0]~output\, LEDG[0]~output, EqCmpDemo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, EqCmpDemo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, EqCmpDemo, 1
-instance = comp, \SW[5]~input\, SW[5]~input, EqCmpDemo, 1
-instance = comp, \SW[4]~input\, SW[4]~input, EqCmpDemo, 1
-instance = comp, \inst1|inst~0\, inst1|inst~0, EqCmpDemo, 1
-instance = comp, \SW[7]~input\, SW[7]~input, EqCmpDemo, 1
-instance = comp, \SW[6]~input\, SW[6]~input, EqCmpDemo, 1
-instance = comp, \SW[3]~input\, SW[3]~input, EqCmpDemo, 1
-instance = comp, \SW[2]~input\, SW[2]~input, EqCmpDemo, 1
-instance = comp, \inst1|inst~1\, inst1|inst~1, EqCmpDemo, 1
-instance = comp, \inst1|inst\, inst1|inst, EqCmpDemo, 1
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht
deleted file mode 100644
index 904ac82..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht
+++ /dev/null
@@ -1,143 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- *****************************************************************************
--- This file contains a Vhdl test bench with test vectors .The test vectors
--- are exported from a vector file in the Quartus Waveform Editor and apply to
--- the top level entity of the current Quartus project .The user can use this
--- testbench to simulate his design using a third-party simulation tool .
--- *****************************************************************************
--- Generated on "03/07/2023 20:57:57"
-
--- Vhdl Test Bench(with test vectors) for design : EqCmpDemo
---
--- Simulation tool : 3rd Party
---
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY EqCmpDemo_vhd_vec_tst IS
-END EqCmpDemo_vhd_vec_tst;
-ARCHITECTURE EqCmpDemo_arch OF EqCmpDemo_vhd_vec_tst IS
--- constants
--- signals
-SIGNAL LEDG : STD_LOGIC_VECTOR(0 DOWNTO 0);
-SIGNAL SW : STD_LOGIC_VECTOR(7 DOWNTO 0);
-COMPONENT EqCmpDemo
- PORT (
- LEDG : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- SW : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
- );
-END COMPONENT;
-BEGIN
- i1 : EqCmpDemo
- PORT MAP (
--- list connections between master ports and signals
- LEDG => LEDG,
- SW => SW
- );
--- SW[7]
-t_prcs_SW_7: PROCESS
-BEGIN
- SW(7) <= '0';
- WAIT FOR 400000 ps;
- SW(7) <= '1';
- WAIT FOR 400000 ps;
- SW(7) <= '0';
-WAIT;
-END PROCESS t_prcs_SW_7;
--- SW[6]
-t_prcs_SW_6: PROCESS
-BEGIN
- FOR i IN 1 TO 2
- LOOP
- SW(6) <= '0';
- WAIT FOR 200000 ps;
- SW(6) <= '1';
- WAIT FOR 200000 ps;
- END LOOP;
- SW(6) <= '0';
-WAIT;
-END PROCESS t_prcs_SW_6;
--- SW[5]
-t_prcs_SW_5: PROCESS
-BEGIN
-LOOP
- SW(5) <= '0';
- WAIT FOR 100000 ps;
- SW(5) <= '1';
- WAIT FOR 100000 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_SW_5;
--- SW[4]
-t_prcs_SW_4: PROCESS
-BEGIN
-LOOP
- SW(4) <= '0';
- WAIT FOR 50000 ps;
- SW(4) <= '1';
- WAIT FOR 50000 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_SW_4;
--- SW[3]
-t_prcs_SW_3: PROCESS
-BEGIN
-LOOP
- SW(3) <= '0';
- WAIT FOR 25000 ps;
- SW(3) <= '1';
- WAIT FOR 25000 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_SW_3;
--- SW[2]
-t_prcs_SW_2: PROCESS
-BEGIN
-LOOP
- SW(2) <= '0';
- WAIT FOR 12500 ps;
- SW(2) <= '1';
- WAIT FOR 12500 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_SW_2;
--- SW[1]
-t_prcs_SW_1: PROCESS
-BEGIN
-LOOP
- SW(1) <= '0';
- WAIT FOR 6250 ps;
- SW(1) <= '1';
- WAIT FOR 6250 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_SW_1;
--- SW[0]
-t_prcs_SW_0: PROCESS
-BEGIN
- FOR i IN 1 TO 148
- LOOP
- SW(0) <= '0';
- WAIT FOR 3375 ps;
- SW(0) <= '1';
- WAIT FOR 3375 ps;
- END LOOP;
- SW(0) <= '0';
-WAIT;
-END PROCESS t_prcs_SW_0;
-END EqCmpDemo_arch;
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp8.vwf.vht b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp8.vwf.vht
deleted file mode 100644
index 26a6fbf..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp8.vwf.vht
+++ /dev/null
@@ -1,3346 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- *****************************************************************************
--- This file contains a Vhdl test bench with test vectors .The test vectors
--- are exported from a vector file in the Quartus Waveform Editor and apply to
--- the top level entity of the current Quartus project .The user can use this
--- testbench to simulate his design using a third-party simulation tool .
--- *****************************************************************************
--- Generated on "03/07/2023 20:53:51"
-
--- Vhdl Test Bench(with test vectors) for design : EqCmpDemo
---
--- Simulation tool : 3rd Party
---
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY EqCmpDemo_vhd_vec_tst IS
-END EqCmpDemo_vhd_vec_tst;
-ARCHITECTURE EqCmpDemo_arch OF EqCmpDemo_vhd_vec_tst IS
--- constants
--- signals
-SIGNAL LEDG : STD_LOGIC_VECTOR(0 DOWNTO 0);
-SIGNAL SW : STD_LOGIC_VECTOR(15 DOWNTO 0);
-COMPONENT EqCmpDemo
- PORT (
- LEDG : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- SW : IN STD_LOGIC_VECTOR(15 DOWNTO 0)
- );
-END COMPONENT;
-BEGIN
- i1 : EqCmpDemo
- PORT MAP (
--- list connections between master ports and signals
- LEDG => LEDG,
- SW => SW
- );
--- SW[15]
-t_prcs_SW_15: PROCESS
-BEGIN
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 10000 ps;
- SW(15) <= '0';
- WAIT FOR 10000 ps;
- SW(15) <= '1';
- WAIT FOR 10000 ps;
- SW(15) <= '0';
- WAIT FOR 15000 ps;
- SW(15) <= '1';
- WAIT FOR 10000 ps;
- SW(15) <= '0';
- WAIT FOR 30000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 25000 ps;
- SW(15) <= '1';
- WAIT FOR 50000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 10000 ps;
- SW(15) <= '0';
- WAIT FOR 10000 ps;
- SW(15) <= '1';
- WAIT FOR 10000 ps;
- SW(15) <= '0';
- WAIT FOR 10000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 35000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 15000 ps;
- SW(15) <= '1';
- WAIT FOR 10000 ps;
- SW(15) <= '0';
- WAIT FOR 10000 ps;
- SW(15) <= '1';
- WAIT FOR 10000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 15000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 50000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 10000 ps;
- SW(15) <= '0';
- WAIT FOR 25000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 10000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 15000 ps;
- SW(15) <= '1';
- WAIT FOR 15000 ps;
- SW(15) <= '0';
- WAIT FOR 10000 ps;
- SW(15) <= '1';
- WAIT FOR 10000 ps;
- SW(15) <= '0';
- WAIT FOR 10000 ps;
- SW(15) <= '1';
- WAIT FOR 15000 ps;
- SW(15) <= '0';
- WAIT FOR 20000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 20000 ps;
- SW(15) <= '1';
- WAIT FOR 20000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 25000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 20000 ps;
- SW(15) <= '0';
- WAIT FOR 10000 ps;
- SW(15) <= '1';
- WAIT FOR 15000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 10000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 30000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 15000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 10000 ps;
- SW(15) <= '0';
- WAIT FOR 35000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 10000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 15000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 10000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 20000 ps;
- SW(15) <= '0';
- WAIT FOR 5000 ps;
- SW(15) <= '1';
- WAIT FOR 10000 ps;
- SW(15) <= '0';
- WAIT FOR 20000 ps;
- SW(15) <= '1';
- WAIT FOR 5000 ps;
- SW(15) <= '0';
-WAIT;
-END PROCESS t_prcs_SW_15;
--- SW[14]
-t_prcs_SW_14: PROCESS
-BEGIN
- SW(14) <= '1';
- WAIT FOR 25000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 15000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 15000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 25000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 15000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 20000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 10000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 20000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 10000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 10000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 10000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 15000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 20000 ps;
- SW(14) <= '1';
- WAIT FOR 10000 ps;
- SW(14) <= '0';
- WAIT FOR 25000 ps;
- SW(14) <= '1';
- WAIT FOR 10000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 10000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 30000 ps;
- SW(14) <= '1';
- WAIT FOR 25000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 15000 ps;
- SW(14) <= '1';
- WAIT FOR 15000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 30000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 10000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 20000 ps;
- SW(14) <= '0';
- WAIT FOR 15000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 15000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 10000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 20000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 20000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 25000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 5000 ps;
- SW(14) <= '0';
- WAIT FOR 10000 ps;
- SW(14) <= '1';
- WAIT FOR 10000 ps;
- SW(14) <= '0';
- WAIT FOR 5000 ps;
- SW(14) <= '1';
- WAIT FOR 10000 ps;
- SW(14) <= '0';
- WAIT FOR 15000 ps;
- SW(14) <= '1';
-WAIT;
-END PROCESS t_prcs_SW_14;
--- SW[13]
-t_prcs_SW_13: PROCESS
-BEGIN
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 25000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 30000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 20000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 20000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 15000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 20000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 15000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 15000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 10000 ps;
- SW(13) <= '0';
- WAIT FOR 15000 ps;
- SW(13) <= '1';
- WAIT FOR 10000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 10000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 10000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 20000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 20000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 10000 ps;
- SW(13) <= '0';
- WAIT FOR 15000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 10000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 15000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 15000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 10000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 10000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 15000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 10000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 30000 ps;
- SW(13) <= '0';
- WAIT FOR 20000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 10000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 20000 ps;
- SW(13) <= '0';
- WAIT FOR 15000 ps;
- SW(13) <= '1';
- WAIT FOR 40000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
- WAIT FOR 30000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 10000 ps;
- SW(13) <= '1';
- WAIT FOR 5000 ps;
- SW(13) <= '0';
- WAIT FOR 5000 ps;
- SW(13) <= '1';
-WAIT;
-END PROCESS t_prcs_SW_13;
--- SW[12]
-t_prcs_SW_12: PROCESS
-BEGIN
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 25000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 10000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 10000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 15000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 15000 ps;
- SW(12) <= '1';
- WAIT FOR 30000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 20000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 10000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 10000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 15000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 10000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 10000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 15000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 10000 ps;
- SW(12) <= '0';
- WAIT FOR 15000 ps;
- SW(12) <= '1';
- WAIT FOR 15000 ps;
- SW(12) <= '0';
- WAIT FOR 15000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 15000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 20000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 10000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 15000 ps;
- SW(12) <= '0';
- WAIT FOR 25000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 20000 ps;
- SW(12) <= '1';
- WAIT FOR 40000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 10000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 15000 ps;
- SW(12) <= '0';
- WAIT FOR 25000 ps;
- SW(12) <= '1';
- WAIT FOR 15000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 10000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 25000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 10000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 10000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 15000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 15000 ps;
- SW(12) <= '0';
- WAIT FOR 5000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
- WAIT FOR 5000 ps;
- SW(12) <= '0';
- WAIT FOR 10000 ps;
- SW(12) <= '1';
-WAIT;
-END PROCESS t_prcs_SW_12;
--- SW[11]
-t_prcs_SW_11: PROCESS
-BEGIN
- SW(11) <= '1';
- WAIT FOR 20000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 20000 ps;
- SW(11) <= '0';
- WAIT FOR 15000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 15000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 25000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 10000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 15000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 15000 ps;
- SW(11) <= '0';
- WAIT FOR 15000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 10000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 10000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 15000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 35000 ps;
- SW(11) <= '0';
- WAIT FOR 10000 ps;
- SW(11) <= '1';
- WAIT FOR 30000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 30000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 20000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 15000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 10000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 15000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 30000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 10000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 10000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 40000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 10000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 20000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 15000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 10000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 10000 ps;
- SW(11) <= '0';
- WAIT FOR 15000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 20000 ps;
- SW(11) <= '0';
- WAIT FOR 10000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 10000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
- WAIT FOR 5000 ps;
- SW(11) <= '1';
- WAIT FOR 5000 ps;
- SW(11) <= '0';
-WAIT;
-END PROCESS t_prcs_SW_11;
--- SW[10]
-t_prcs_SW_10: PROCESS
-BEGIN
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 15000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 15000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 15000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 15000 ps;
- SW(10) <= '0';
- WAIT FOR 10000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 10000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 20000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 10000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 10000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 50000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 10000 ps;
- SW(10) <= '1';
- WAIT FOR 20000 ps;
- SW(10) <= '0';
- WAIT FOR 15000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 10000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 10000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 15000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 15000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 10000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 15000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 15000 ps;
- SW(10) <= '1';
- WAIT FOR 25000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 15000 ps;
- SW(10) <= '0';
- WAIT FOR 10000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 10000 ps;
- SW(10) <= '1';
- WAIT FOR 20000 ps;
- SW(10) <= '0';
- WAIT FOR 15000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 20000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 20000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 15000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 25000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 15000 ps;
- SW(10) <= '0';
- WAIT FOR 20000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 10000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 20000 ps;
- SW(10) <= '0';
- WAIT FOR 20000 ps;
- SW(10) <= '1';
- WAIT FOR 10000 ps;
- SW(10) <= '0';
- WAIT FOR 5000 ps;
- SW(10) <= '1';
- WAIT FOR 5000 ps;
- SW(10) <= '0';
- WAIT FOR 15000 ps;
- SW(10) <= '1';
-WAIT;
-END PROCESS t_prcs_SW_10;
--- SW[9]
-t_prcs_SW_9: PROCESS
-BEGIN
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 10000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 30000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 15000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 10000 ps;
- SW(9) <= '0';
- WAIT FOR 15000 ps;
- SW(9) <= '1';
- WAIT FOR 45000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 10000 ps;
- SW(9) <= '1';
- WAIT FOR 10000 ps;
- SW(9) <= '0';
- WAIT FOR 10000 ps;
- SW(9) <= '1';
- WAIT FOR 20000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 20000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 25000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 15000 ps;
- SW(9) <= '1';
- WAIT FOR 25000 ps;
- SW(9) <= '0';
- WAIT FOR 25000 ps;
- SW(9) <= '1';
- WAIT FOR 25000 ps;
- SW(9) <= '0';
- WAIT FOR 25000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 25000 ps;
- SW(9) <= '1';
- WAIT FOR 15000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 10000 ps;
- SW(9) <= '0';
- WAIT FOR 10000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 10000 ps;
- SW(9) <= '1';
- WAIT FOR 10000 ps;
- SW(9) <= '0';
- WAIT FOR 10000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 15000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 10000 ps;
- SW(9) <= '0';
- WAIT FOR 45000 ps;
- SW(9) <= '1';
- WAIT FOR 10000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 20000 ps;
- SW(9) <= '0';
- WAIT FOR 10000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 10000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 15000 ps;
- SW(9) <= '1';
- WAIT FOR 10000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 10000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 10000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 20000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 15000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 10000 ps;
- SW(9) <= '1';
- WAIT FOR 10000 ps;
- SW(9) <= '0';
- WAIT FOR 10000 ps;
- SW(9) <= '1';
- WAIT FOR 10000 ps;
- SW(9) <= '0';
- WAIT FOR 10000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 10000 ps;
- SW(9) <= '1';
- WAIT FOR 25000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 10000 ps;
- SW(9) <= '1';
- WAIT FOR 5000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 10000 ps;
- SW(9) <= '0';
- WAIT FOR 5000 ps;
- SW(9) <= '1';
- WAIT FOR 10000 ps;
- SW(9) <= '0';
- WAIT FOR 15000 ps;
- SW(9) <= '1';
- WAIT FOR 15000 ps;
- SW(9) <= '0';
-WAIT;
-END PROCESS t_prcs_SW_9;
--- SW[8]
-t_prcs_SW_8: PROCESS
-BEGIN
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 15000 ps;
- SW(8) <= '0';
- WAIT FOR 15000 ps;
- SW(8) <= '1';
- WAIT FOR 15000 ps;
- SW(8) <= '0';
- WAIT FOR 10000 ps;
- SW(8) <= '1';
- WAIT FOR 20000 ps;
- SW(8) <= '0';
- WAIT FOR 20000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 15000 ps;
- SW(8) <= '1';
- WAIT FOR 20000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 15000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 10000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 20000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 15000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 20000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 15000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 20000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 15000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 10000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 10000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 10000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 15000 ps;
- SW(8) <= '1';
- WAIT FOR 15000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 10000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 20000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 25000 ps;
- SW(8) <= '1';
- WAIT FOR 20000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 25000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 10000 ps;
- SW(8) <= '1';
- WAIT FOR 20000 ps;
- SW(8) <= '0';
- WAIT FOR 10000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 10000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 10000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 15000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 5000 ps;
- SW(8) <= '1';
- WAIT FOR 5000 ps;
- SW(8) <= '0';
- WAIT FOR 10000 ps;
- SW(8) <= '1';
- WAIT FOR 25000 ps;
- SW(8) <= '0';
- WAIT FOR 10000 ps;
- SW(8) <= '1';
-WAIT;
-END PROCESS t_prcs_SW_8;
--- SW[7]
-t_prcs_SW_7: PROCESS
-BEGIN
- SW(7) <= '0';
- WAIT FOR 20000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 10000 ps;
- SW(7) <= '1';
- WAIT FOR 15000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 15000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 35000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 20000 ps;
- SW(7) <= '1';
- WAIT FOR 20000 ps;
- SW(7) <= '0';
- WAIT FOR 15000 ps;
- SW(7) <= '1';
- WAIT FOR 10000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 10000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 10000 ps;
- SW(7) <= '0';
- WAIT FOR 15000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 15000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 10000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 25000 ps;
- SW(7) <= '0';
- WAIT FOR 10000 ps;
- SW(7) <= '1';
- WAIT FOR 15000 ps;
- SW(7) <= '0';
- WAIT FOR 15000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 10000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 10000 ps;
- SW(7) <= '0';
- WAIT FOR 20000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 20000 ps;
- SW(7) <= '1';
- WAIT FOR 10000 ps;
- SW(7) <= '0';
- WAIT FOR 10000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 15000 ps;
- SW(7) <= '1';
- WAIT FOR 20000 ps;
- SW(7) <= '0';
- WAIT FOR 15000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 10000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 15000 ps;
- SW(7) <= '0';
- WAIT FOR 25000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 10000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 20000 ps;
- SW(7) <= '1';
- WAIT FOR 15000 ps;
- SW(7) <= '0';
- WAIT FOR 25000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 15000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 10000 ps;
- SW(7) <= '0';
- WAIT FOR 10000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 15000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 10000 ps;
- SW(7) <= '1';
- WAIT FOR 10000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 20000 ps;
- SW(7) <= '0';
- WAIT FOR 30000 ps;
- SW(7) <= '1';
- WAIT FOR 10000 ps;
- SW(7) <= '0';
- WAIT FOR 15000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 15000 ps;
- SW(7) <= '0';
- WAIT FOR 5000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 15000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 10000 ps;
- SW(7) <= '1';
- WAIT FOR 5000 ps;
- SW(7) <= '0';
- WAIT FOR 10000 ps;
- SW(7) <= '1';
-WAIT;
-END PROCESS t_prcs_SW_7;
--- SW[6]
-t_prcs_SW_6: PROCESS
-BEGIN
- SW(6) <= '0';
- WAIT FOR 20000 ps;
- SW(6) <= '1';
- WAIT FOR 20000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 15000 ps;
- SW(6) <= '0';
- WAIT FOR 20000 ps;
- SW(6) <= '1';
- WAIT FOR 20000 ps;
- SW(6) <= '0';
- WAIT FOR 10000 ps;
- SW(6) <= '1';
- WAIT FOR 10000 ps;
- SW(6) <= '0';
- WAIT FOR 15000 ps;
- SW(6) <= '1';
- WAIT FOR 35000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 10000 ps;
- SW(6) <= '0';
- WAIT FOR 10000 ps;
- SW(6) <= '1';
- WAIT FOR 10000 ps;
- SW(6) <= '0';
- WAIT FOR 20000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 10000 ps;
- SW(6) <= '0';
- WAIT FOR 20000 ps;
- SW(6) <= '1';
- WAIT FOR 10000 ps;
- SW(6) <= '0';
- WAIT FOR 35000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 10000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 10000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 25000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 10000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 15000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 10000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 10000 ps;
- SW(6) <= '1';
- WAIT FOR 20000 ps;
- SW(6) <= '0';
- WAIT FOR 15000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 25000 ps;
- SW(6) <= '1';
- WAIT FOR 10000 ps;
- SW(6) <= '0';
- WAIT FOR 10000 ps;
- SW(6) <= '1';
- WAIT FOR 10000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 20000 ps;
- SW(6) <= '0';
- WAIT FOR 10000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 10000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 10000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 25000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 15000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 15000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 30000 ps;
- SW(6) <= '1';
- WAIT FOR 15000 ps;
- SW(6) <= '0';
- WAIT FOR 15000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 15000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 10000 ps;
- SW(6) <= '1';
- WAIT FOR 10000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 25000 ps;
- SW(6) <= '0';
- WAIT FOR 10000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 10000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 15000 ps;
- SW(6) <= '1';
- WAIT FOR 5000 ps;
- SW(6) <= '0';
- WAIT FOR 10000 ps;
- SW(6) <= '1';
- WAIT FOR 10000 ps;
- SW(6) <= '0';
- WAIT FOR 5000 ps;
- SW(6) <= '1';
-WAIT;
-END PROCESS t_prcs_SW_6;
--- SW[5]
-t_prcs_SW_5: PROCESS
-BEGIN
- SW(5) <= '1';
- WAIT FOR 20000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 10000 ps;
- SW(5) <= '0';
- WAIT FOR 15000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 10000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 10000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 40000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 15000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 10000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 15000 ps;
- SW(5) <= '1';
- WAIT FOR 10000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 25000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 10000 ps;
- SW(5) <= '0';
- WAIT FOR 15000 ps;
- SW(5) <= '1';
- WAIT FOR 20000 ps;
- SW(5) <= '0';
- WAIT FOR 30000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 20000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 15000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 15000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 10000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 15000 ps;
- SW(5) <= '0';
- WAIT FOR 15000 ps;
- SW(5) <= '1';
- WAIT FOR 10000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 15000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 10000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 10000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 10000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 15000 ps;
- SW(5) <= '1';
- WAIT FOR 15000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 20000 ps;
- SW(5) <= '1';
- WAIT FOR 15000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 10000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 20000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 20000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 15000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 15000 ps;
- SW(5) <= '1';
- WAIT FOR 10000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 15000 ps;
- SW(5) <= '0';
- WAIT FOR 15000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 5000 ps;
- SW(5) <= '1';
- WAIT FOR 5000 ps;
- SW(5) <= '0';
- WAIT FOR 10000 ps;
- SW(5) <= '1';
-WAIT;
-END PROCESS t_prcs_SW_5;
--- SW[4]
-t_prcs_SW_4: PROCESS
-BEGIN
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 25000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 25000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 15000 ps;
- SW(4) <= '1';
- WAIT FOR 20000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 30000 ps;
- SW(4) <= '0';
- WAIT FOR 40000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 15000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 15000 ps;
- SW(4) <= '0';
- WAIT FOR 25000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 15000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 25000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 20000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 30000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 15000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 30000 ps;
- SW(4) <= '0';
- WAIT FOR 20000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 15000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 15000 ps;
- SW(4) <= '1';
- WAIT FOR 15000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 15000 ps;
- SW(4) <= '1';
- WAIT FOR 10000 ps;
- SW(4) <= '0';
- WAIT FOR 10000 ps;
- SW(4) <= '1';
- WAIT FOR 30000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 15000 ps;
- SW(4) <= '1';
- WAIT FOR 5000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
- WAIT FOR 15000 ps;
- SW(4) <= '0';
- WAIT FOR 5000 ps;
- SW(4) <= '1';
-WAIT;
-END PROCESS t_prcs_SW_4;
--- SW[3]
-t_prcs_SW_3: PROCESS
-BEGIN
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 10000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 10000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 10000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 15000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 10000 ps;
- SW(3) <= '1';
- WAIT FOR 15000 ps;
- SW(3) <= '0';
- WAIT FOR 20000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 10000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 15000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 25000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 15000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 15000 ps;
- SW(3) <= '0';
- WAIT FOR 10000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 20000 ps;
- SW(3) <= '1';
- WAIT FOR 15000 ps;
- SW(3) <= '0';
- WAIT FOR 20000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 15000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 30000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 15000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 20000 ps;
- SW(3) <= '0';
- WAIT FOR 25000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 20000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 10000 ps;
- SW(3) <= '1';
- WAIT FOR 15000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 40000 ps;
- SW(3) <= '0';
- WAIT FOR 15000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 10000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 20000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 10000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 15000 ps;
- SW(3) <= '1';
- WAIT FOR 15000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 15000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 5000 ps;
- SW(3) <= '0';
- WAIT FOR 35000 ps;
- SW(3) <= '1';
- WAIT FOR 15000 ps;
- SW(3) <= '0';
- WAIT FOR 5000 ps;
- SW(3) <= '1';
- WAIT FOR 10000 ps;
- SW(3) <= '0';
-WAIT;
-END PROCESS t_prcs_SW_3;
--- SW[2]
-t_prcs_SW_2: PROCESS
-BEGIN
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 20000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 10000 ps;
- SW(2) <= '1';
- WAIT FOR 25000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 10000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 10000 ps;
- SW(2) <= '0';
- WAIT FOR 15000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 10000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 10000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 25000 ps;
- SW(2) <= '1';
- WAIT FOR 10000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 25000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 15000 ps;
- SW(2) <= '0';
- WAIT FOR 10000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 10000 ps;
- SW(2) <= '1';
- WAIT FOR 20000 ps;
- SW(2) <= '0';
- WAIT FOR 10000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 20000 ps;
- SW(2) <= '1';
- WAIT FOR 20000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 10000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 20000 ps;
- SW(2) <= '0';
- WAIT FOR 15000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 35000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 10000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 10000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 10000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 10000 ps;
- SW(2) <= '0';
- WAIT FOR 20000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 15000 ps;
- SW(2) <= '0';
- WAIT FOR 15000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 20000 ps;
- SW(2) <= '1';
- WAIT FOR 30000 ps;
- SW(2) <= '0';
- WAIT FOR 10000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 10000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 20000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 10000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 15000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 10000 ps;
- SW(2) <= '0';
- WAIT FOR 10000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 20000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 15000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 15000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 15000 ps;
- SW(2) <= '0';
- WAIT FOR 10000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 15000 ps;
- SW(2) <= '0';
- WAIT FOR 10000 ps;
- SW(2) <= '1';
- WAIT FOR 30000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
- WAIT FOR 5000 ps;
- SW(2) <= '1';
- WAIT FOR 5000 ps;
- SW(2) <= '0';
-WAIT;
-END PROCESS t_prcs_SW_2;
--- SW[1]
-t_prcs_SW_1: PROCESS
-BEGIN
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 15000 ps;
- SW(1) <= '0';
- WAIT FOR 10000 ps;
- SW(1) <= '1';
- WAIT FOR 10000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 10000 ps;
- SW(1) <= '0';
- WAIT FOR 15000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 10000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 15000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 10000 ps;
- SW(1) <= '1';
- WAIT FOR 15000 ps;
- SW(1) <= '0';
- WAIT FOR 15000 ps;
- SW(1) <= '1';
- WAIT FOR 10000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 10000 ps;
- SW(1) <= '0';
- WAIT FOR 10000 ps;
- SW(1) <= '1';
- WAIT FOR 45000 ps;
- SW(1) <= '0';
- WAIT FOR 10000 ps;
- SW(1) <= '1';
- WAIT FOR 10000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 10000 ps;
- SW(1) <= '1';
- WAIT FOR 15000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 15000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 15000 ps;
- SW(1) <= '1';
- WAIT FOR 15000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 10000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 10000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 15000 ps;
- SW(1) <= '1';
- WAIT FOR 25000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 15000 ps;
- SW(1) <= '0';
- WAIT FOR 15000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 25000 ps;
- SW(1) <= '0';
- WAIT FOR 10000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 25000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 10000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 35000 ps;
- SW(1) <= '1';
- WAIT FOR 25000 ps;
- SW(1) <= '0';
- WAIT FOR 15000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 10000 ps;
- SW(1) <= '1';
- WAIT FOR 10000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 10000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 10000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 10000 ps;
- SW(1) <= '0';
- WAIT FOR 15000 ps;
- SW(1) <= '1';
- WAIT FOR 10000 ps;
- SW(1) <= '0';
- WAIT FOR 20000 ps;
- SW(1) <= '1';
- WAIT FOR 20000 ps;
- SW(1) <= '0';
- WAIT FOR 10000 ps;
- SW(1) <= '1';
- WAIT FOR 30000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 15000 ps;
- SW(1) <= '0';
- WAIT FOR 10000 ps;
- SW(1) <= '1';
- WAIT FOR 10000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 5000 ps;
- SW(1) <= '0';
- WAIT FOR 5000 ps;
- SW(1) <= '1';
- WAIT FOR 30000 ps;
- SW(1) <= '0';
-WAIT;
-END PROCESS t_prcs_SW_1;
--- SW[0]
-t_prcs_SW_0: PROCESS
-BEGIN
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 25000 ps;
- SW(0) <= '1';
- WAIT FOR 20000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 15000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 25000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 25000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 15000 ps;
- SW(0) <= '1';
- WAIT FOR 30000 ps;
- SW(0) <= '0';
- WAIT FOR 15000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 35000 ps;
- SW(0) <= '1';
- WAIT FOR 35000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 25000 ps;
- SW(0) <= '1';
- WAIT FOR 35000 ps;
- SW(0) <= '0';
- WAIT FOR 15000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 15000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 15000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 15000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 15000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 25000 ps;
- SW(0) <= '1';
- WAIT FOR 15000 ps;
- SW(0) <= '0';
- WAIT FOR 20000 ps;
- SW(0) <= '1';
- WAIT FOR 15000 ps;
- SW(0) <= '0';
- WAIT FOR 15000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 5000 ps;
- SW(0) <= '0';
- WAIT FOR 10000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 15000 ps;
- SW(0) <= '1';
- WAIT FOR 10000 ps;
- SW(0) <= '0';
- WAIT FOR 5000 ps;
- SW(0) <= '1';
-WAIT;
-END PROCESS t_prcs_SW_0;
-END EqCmpDemo_arch;
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.do b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.do
deleted file mode 100644
index d3c3e9b..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.do
+++ /dev/null
@@ -1,17 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vcom -work work EqCmpDemo.vho
-vcom -work work EqCmp4.vwf.vht
-vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst
-vcd file -direction EqCmpDemo.msim.vcd
-vcd add -internal EqCmpDemo_vhd_vec_tst/*
-vcd add -internal EqCmpDemo_vhd_vec_tst/i1/*
-proc simTimestamp {} {
- echo "Simulation time: $::now ps"
- if { [string equal running [runStatus]] } {
- after 2500 simTimestamp
- }
-}
-after 2500 simTimestamp
-run -all
-quit -f
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.msim.vcd b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.msim.vcd
deleted file mode 100644
index 5253dce..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.msim.vcd
+++ /dev/null
@@ -1,2883 +0,0 @@
-$comment
- File created using the following command:
- vcd file EqCmpDemo.msim.vcd -direction
-$end
-$date
- Tue Mar 7 20:57:58 2023
-$end
-$version
- ModelSim Version 2020.1
-$end
-$timescale
- 1ps
-$end
-
-$scope module eqcmpdemo_vhd_vec_tst $end
-$var wire 1 ! LEDG [0] $end
-$var wire 1 " SW [7] $end
-$var wire 1 # SW [6] $end
-$var wire 1 $ SW [5] $end
-$var wire 1 % SW [4] $end
-$var wire 1 & SW [3] $end
-$var wire 1 ' SW [2] $end
-$var wire 1 ( SW [1] $end
-$var wire 1 ) SW [0] $end
-
-$scope module i1 $end
-$var wire 1 * gnd $end
-$var wire 1 + vcc $end
-$var wire 1 , unknown $end
-$var wire 1 - devoe $end
-$var wire 1 . devclrn $end
-$var wire 1 / devpor $end
-$var wire 1 0 ww_devoe $end
-$var wire 1 1 ww_devclrn $end
-$var wire 1 2 ww_devpor $end
-$var wire 1 3 ww_LEDG [0] $end
-$var wire 1 4 ww_SW [7] $end
-$var wire 1 5 ww_SW [6] $end
-$var wire 1 6 ww_SW [5] $end
-$var wire 1 7 ww_SW [4] $end
-$var wire 1 8 ww_SW [3] $end
-$var wire 1 9 ww_SW [2] $end
-$var wire 1 : ww_SW [1] $end
-$var wire 1 ; ww_SW [0] $end
-$var wire 1 < \LEDG[0]~output_o\ $end
-$var wire 1 = \SW[1]~input_o\ $end
-$var wire 1 > \SW[0]~input_o\ $end
-$var wire 1 ? \SW[5]~input_o\ $end
-$var wire 1 @ \SW[4]~input_o\ $end
-$var wire 1 A \inst1|inst~0_combout\ $end
-$var wire 1 B \SW[7]~input_o\ $end
-$var wire 1 C \SW[6]~input_o\ $end
-$var wire 1 D \SW[3]~input_o\ $end
-$var wire 1 E \SW[2]~input_o\ $end
-$var wire 1 F \inst1|inst~1_combout\ $end
-$var wire 1 G \inst1|inst~combout\ $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0*
-1+
-x,
-1-
-1.
-1/
-10
-11
-12
-1<
-0=
-0>
-0?
-0@
-1A
-0B
-0C
-0D
-0E
-1F
-1G
-0"
-0#
-0$
-0%
-0&
-0'
-0(
-0)
-13
-04
-05
-06
-07
-08
-09
-0:
-0;
-1!
-$end
-#3375
-1)
-1;
-1>
-0A
-0G
-0<
-03
-0!
-#6250
-1(
-1:
-1=
-#6750
-0)
-0;
-0>
-#10125
-1)
-1;
-1>
-#12500
-0(
-1'
-0:
-19
-1E
-0=
-0F
-#13500
-0)
-0;
-0>
-1A
-#16875
-1)
-1;
-1>
-0A
-#18750
-1(
-1:
-1=
-#20250
-0)
-0;
-0>
-#23625
-1)
-1;
-1>
-#25000
-0(
-0'
-1&
-0:
-09
-18
-1D
-0E
-0=
-#27000
-0)
-0;
-0>
-1A
-#30375
-1)
-1;
-1>
-0A
-#31250
-1(
-1:
-1=
-#33750
-0)
-0;
-0>
-#37125
-1)
-1;
-1>
-#37500
-0(
-1'
-0:
-19
-1E
-0=
-#40500
-0)
-0;
-0>
-1A
-#43750
-1(
-1:
-1=
-0A
-#43875
-1)
-1;
-1>
-#47250
-0)
-0;
-0>
-#50000
-0(
-0'
-0&
-1%
-0:
-09
-08
-17
-1@
-0D
-0E
-0=
-1F
-#50625
-1)
-1;
-1>
-1A
-1G
-1<
-13
-1!
-#54000
-0)
-0;
-0>
-0A
-0G
-0<
-03
-0!
-#56250
-1(
-1:
-1=
-#57375
-1)
-1;
-1>
-#60750
-0)
-0;
-0>
-#62500
-0(
-1'
-0:
-19
-1E
-0=
-0F
-#64125
-1)
-1;
-1>
-1A
-#67500
-0)
-0;
-0>
-0A
-#68750
-1(
-1:
-1=
-#70875
-1)
-1;
-1>
-#74250
-0)
-0;
-0>
-#75000
-0(
-0'
-1&
-0:
-09
-18
-1D
-0E
-0=
-#77625
-1)
-1;
-1>
-1A
-#81000
-0)
-0;
-0>
-0A
-#81250
-1(
-1:
-1=
-#84375
-1)
-1;
-1>
-#87500
-0(
-1'
-0:
-19
-1E
-0=
-1A
-#87750
-0)
-0;
-0>
-0A
-#91125
-1)
-1;
-1>
-1A
-#93750
-1(
-1:
-1=
-0A
-#94500
-0)
-0;
-0>
-#97875
-1)
-1;
-1>
-#100000
-0(
-0'
-0&
-0%
-1$
-0:
-09
-08
-07
-16
-1?
-0@
-0D
-0E
-0=
-1F
-#101250
-0)
-0;
-0>
-#104625
-1)
-1;
-1>
-#106250
-1(
-1:
-1=
-#108000
-0)
-0;
-0>
-1A
-1G
-1<
-13
-1!
-#111375
-1)
-1;
-1>
-0A
-0G
-0<
-03
-0!
-#112500
-0(
-1'
-0:
-19
-1E
-0=
-0F
-#114750
-0)
-0;
-0>
-#118125
-1)
-1;
-1>
-#118750
-1(
-1:
-1=
-#121500
-0)
-0;
-0>
-1A
-#124875
-1)
-1;
-1>
-0A
-#125000
-0(
-0'
-1&
-0:
-09
-18
-1D
-0E
-0=
-#128250
-0)
-0;
-0>
-#131250
-1(
-1:
-1=
-1A
-#131625
-1)
-1;
-1>
-0A
-#135000
-0)
-0;
-0>
-1A
-#137500
-0(
-1'
-0:
-19
-1E
-0=
-0A
-#138375
-1)
-1;
-1>
-#141750
-0)
-0;
-0>
-#143750
-1(
-1:
-1=
-1A
-#145125
-1)
-1;
-1>
-0A
-#148500
-0)
-0;
-0>
-1A
-#150000
-0(
-0'
-0&
-1%
-0:
-09
-08
-17
-1@
-0D
-0E
-0=
-1F
-0A
-#151875
-1)
-1;
-1>
-#155250
-0)
-0;
-0>
-#156250
-1(
-1:
-1=
-#158625
-1)
-1;
-1>
-1A
-1G
-1<
-13
-1!
-#162000
-0)
-0;
-0>
-0A
-0G
-0<
-03
-0!
-#162500
-0(
-1'
-0:
-19
-1E
-0=
-0F
-#165375
-1)
-1;
-1>
-#168750
-0)
-1(
-0;
-1:
-1=
-0>
-#172125
-1)
-1;
-1>
-1A
-#175000
-0(
-0'
-1&
-0:
-09
-18
-1D
-0E
-0=
-0A
-#175500
-0)
-0;
-0>
-#178875
-1)
-1;
-1>
-#181250
-1(
-1:
-1=
-1A
-#182250
-0)
-0;
-0>
-0A
-#185625
-1)
-1;
-1>
-1A
-#187500
-0(
-1'
-0:
-19
-1E
-0=
-0A
-#189000
-0)
-0;
-0>
-#192375
-1)
-1;
-1>
-#193750
-1(
-1:
-1=
-1A
-#195750
-0)
-0;
-0>
-0A
-#199125
-1)
-1;
-1>
-1A
-#200000
-0(
-0'
-0&
-0%
-0$
-1#
-0:
-09
-08
-07
-06
-15
-1C
-0?
-0@
-0D
-0E
-0=
-0A
-#202500
-0)
-0;
-0>
-1A
-#205875
-1)
-1;
-1>
-0A
-#206250
-1(
-1:
-1=
-#209250
-0)
-0;
-0>
-#212500
-0(
-1'
-0:
-19
-1E
-0=
-1A
-1F
-1G
-1<
-13
-1!
-#212625
-1)
-1;
-1>
-0A
-0G
-0<
-03
-0!
-#216000
-0)
-0;
-0>
-1A
-1G
-1<
-13
-1!
-#218750
-1(
-1:
-1=
-0A
-0G
-0<
-03
-0!
-#219375
-1)
-1;
-1>
-#222750
-0)
-0;
-0>
-#225000
-0(
-0'
-1&
-0:
-09
-18
-1D
-0E
-0=
-1A
-0F
-#226125
-1)
-1;
-1>
-0A
-#229500
-0)
-0;
-0>
-1A
-#231250
-1(
-1:
-1=
-0A
-#232875
-1)
-1;
-1>
-#236250
-0)
-0;
-0>
-#237500
-0(
-1'
-0:
-19
-1E
-0=
-1A
-#239625
-1)
-1;
-1>
-0A
-#243000
-0)
-0;
-0>
-1A
-#243750
-1(
-1:
-1=
-0A
-#246375
-1)
-1;
-1>
-#249750
-0)
-0;
-0>
-#250000
-0(
-0'
-0&
-1%
-0:
-09
-08
-17
-1@
-0D
-0E
-0=
-#253125
-1)
-1;
-1>
-1A
-#256250
-1(
-1:
-1=
-0A
-#256500
-0)
-0;
-0>
-#259875
-1)
-1;
-1>
-#262500
-0(
-1'
-0:
-19
-1E
-0=
-1A
-1F
-1G
-1<
-13
-1!
-#263250
-0)
-0;
-0>
-0A
-0G
-0<
-03
-0!
-#266625
-1)
-1;
-1>
-1A
-1G
-1<
-13
-1!
-#268750
-1(
-1:
-1=
-0A
-0G
-0<
-03
-0!
-#270000
-0)
-0;
-0>
-#273375
-1)
-1;
-1>
-#275000
-0(
-0'
-1&
-0:
-09
-18
-1D
-0E
-0=
-1A
-0F
-#276750
-0)
-0;
-0>
-0A
-#280125
-1)
-1;
-1>
-1A
-#281250
-1(
-1:
-1=
-0A
-#283500
-0)
-0;
-0>
-#286875
-1)
-1;
-1>
-#287500
-0(
-1'
-0:
-19
-1E
-0=
-1A
-#290250
-0)
-0;
-0>
-0A
-#293625
-1)
-1;
-1>
-1A
-#293750
-1(
-1:
-1=
-0A
-#297000
-0)
-0;
-0>
-#300000
-0(
-0'
-0&
-0%
-1$
-0:
-09
-08
-07
-16
-1?
-0@
-0D
-0E
-0=
-#300375
-1)
-1;
-1>
-#303750
-0)
-0;
-0>
-#306250
-1(
-1:
-1=
-1A
-#307125
-1)
-1;
-1>
-0A
-#310500
-0)
-0;
-0>
-1A
-#312500
-0(
-1'
-0:
-19
-1E
-0=
-0A
-1F
-#313875
-1)
-1;
-1>
-#317250
-0)
-0;
-0>
-#318750
-1(
-1:
-1=
-1A
-1G
-1<
-13
-1!
-#320625
-1)
-1;
-1>
-0A
-0G
-0<
-03
-0!
-#324000
-0)
-0;
-0>
-1A
-1G
-1<
-13
-1!
-#325000
-0(
-0'
-1&
-0:
-09
-18
-1D
-0E
-0=
-0A
-0F
-0G
-0<
-03
-0!
-#327375
-1)
-1;
-1>
-#330750
-0)
-0;
-0>
-#331250
-1(
-1:
-1=
-1A
-#334125
-1)
-1;
-1>
-0A
-#337500
-0)
-0(
-1'
-0;
-0:
-19
-1E
-0=
-0>
-#340875
-1)
-1;
-1>
-#343750
-1(
-1:
-1=
-#344250
-0)
-0;
-0>
-1A
-#347625
-1)
-1;
-1>
-0A
-#350000
-0(
-0'
-0&
-1%
-0:
-09
-08
-17
-1@
-0D
-0E
-0=
-#351000
-0)
-0;
-0>
-#354375
-1)
-1;
-1>
-#356250
-1(
-1:
-1=
-1A
-#357750
-0)
-0;
-0>
-0A
-#361125
-1)
-1;
-1>
-1A
-#362500
-0(
-1'
-0:
-19
-1E
-0=
-0A
-1F
-#364500
-0)
-0;
-0>
-#367875
-1)
-1;
-1>
-#368750
-1(
-1:
-1=
-1A
-1G
-1<
-13
-1!
-#371250
-0)
-0;
-0>
-0A
-0G
-0<
-03
-0!
-#374625
-1)
-1;
-1>
-1A
-1G
-1<
-13
-1!
-#375000
-0(
-0'
-1&
-0:
-09
-18
-1D
-0E
-0=
-0A
-0F
-0G
-0<
-03
-0!
-#378000
-0)
-0;
-0>
-#381250
-1(
-1:
-1=
-#381375
-1)
-1;
-1>
-1A
-#384750
-0)
-0;
-0>
-0A
-#387500
-0(
-1'
-0:
-19
-1E
-0=
-#388125
-1)
-1;
-1>
-#391500
-0)
-0;
-0>
-#393750
-1(
-1:
-1=
-#394875
-1)
-1;
-1>
-1A
-#398250
-0)
-0;
-0>
-0A
-#400000
-0(
-0'
-0&
-0%
-0$
-0#
-1"
-0:
-09
-08
-07
-06
-05
-14
-1B
-0C
-0?
-0@
-0D
-0E
-0=
-1A
-#401625
-1)
-1;
-1>
-0A
-#405000
-0)
-0;
-0>
-1A
-#406250
-1(
-1:
-1=
-0A
-#408375
-1)
-1;
-1>
-#411750
-0)
-0;
-0>
-#412500
-0(
-1'
-0:
-19
-1E
-0=
-1A
-#415125
-1)
-1;
-1>
-0A
-#418500
-0)
-0;
-0>
-1A
-#418750
-1(
-1:
-1=
-0A
-#421875
-1)
-1;
-1>
-#425000
-0(
-0'
-1&
-0:
-09
-18
-1D
-0E
-0=
-1F
-#425250
-0)
-0;
-0>
-1A
-1G
-1<
-13
-1!
-#428625
-1)
-1;
-1>
-0A
-0G
-0<
-03
-0!
-#431250
-1(
-1:
-1=
-#432000
-0)
-0;
-0>
-#435375
-1)
-1;
-1>
-#437500
-0(
-1'
-0:
-19
-1E
-0=
-0F
-#438750
-0)
-0;
-0>
-1A
-#442125
-1)
-1;
-1>
-0A
-#443750
-1(
-1:
-1=
-#445500
-0)
-0;
-0>
-#448875
-1)
-1;
-1>
-#450000
-0(
-0'
-0&
-1%
-0:
-09
-08
-17
-1@
-0D
-0E
-0=
-1A
-#452250
-0)
-0;
-0>
-0A
-#455625
-1)
-1;
-1>
-1A
-#456250
-1(
-1:
-1=
-0A
-#459000
-0)
-0;
-0>
-#462375
-1)
-1;
-1>
-#462500
-0(
-1'
-0:
-19
-1E
-0=
-1A
-#465750
-0)
-0;
-0>
-0A
-#468750
-1(
-1:
-1=
-#469125
-1)
-1;
-1>
-#472500
-0)
-0;
-0>
-#475000
-0(
-0'
-1&
-0:
-09
-18
-1D
-0E
-0=
-1F
-#475875
-1)
-1;
-1>
-1A
-1G
-1<
-13
-1!
-#479250
-0)
-0;
-0>
-0A
-0G
-0<
-03
-0!
-#481250
-1(
-1:
-1=
-#482625
-1)
-1;
-1>
-#486000
-0)
-0;
-0>
-#487500
-0(
-1'
-0:
-19
-1E
-0=
-0F
-#489375
-1)
-1;
-1>
-1A
-#492750
-0)
-0;
-0>
-0A
-#493750
-1(
-1:
-1=
-#496125
-1)
-1;
-1>
-#499500
-0)
-0;
-0>
-#500000
-0(
-0'
-0&
-0%
-1$
-0:
-09
-08
-07
-16
-1?
-0@
-0D
-0E
-0=
-#502875
-1)
-1;
-1>
-#506250
-0)
-1(
-0;
-1:
-1=
-0>
-1A
-#509625
-1)
-1;
-1>
-0A
-#512500
-0(
-1'
-0:
-19
-1E
-0=
-#513000
-0)
-0;
-0>
-#516375
-1)
-1;
-1>
-#518750
-1(
-1:
-1=
-#519750
-0)
-0;
-0>
-1A
-#523125
-1)
-1;
-1>
-0A
-#525000
-0(
-0'
-1&
-0:
-09
-18
-1D
-0E
-0=
-1F
-#526500
-0)
-0;
-0>
-#529875
-1)
-1;
-1>
-#531250
-1(
-1:
-1=
-#533250
-0)
-0;
-0>
-1A
-1G
-1<
-13
-1!
-#536625
-1)
-1;
-1>
-0A
-0G
-0<
-03
-0!
-#537500
-0(
-1'
-0:
-19
-1E
-0=
-0F
-#540000
-0)
-0;
-0>
-#543375
-1)
-1;
-1>
-#543750
-1(
-1:
-1=
-#546750
-0)
-0;
-0>
-1A
-#550000
-0(
-0'
-0&
-1%
-0:
-09
-08
-17
-1@
-0D
-0E
-0=
-0A
-#550125
-1)
-1;
-1>
-#553500
-0)
-0;
-0>
-#556250
-1(
-1:
-1=
-#556875
-1)
-1;
-1>
-1A
-#560250
-0)
-0;
-0>
-0A
-#562500
-0(
-1'
-0:
-19
-1E
-0=
-#563625
-1)
-1;
-1>
-#567000
-0)
-0;
-0>
-#568750
-1(
-1:
-1=
-#570375
-1)
-1;
-1>
-1A
-#573750
-0)
-0;
-0>
-0A
-#575000
-0(
-0'
-1&
-0:
-09
-18
-1D
-0E
-0=
-1F
-#577125
-1)
-1;
-1>
-#580500
-0)
-0;
-0>
-#581250
-1(
-1:
-1=
-#583875
-1)
-1;
-1>
-1A
-1G
-1<
-13
-1!
-#587250
-0)
-0;
-0>
-0A
-0G
-0<
-03
-0!
-#587500
-0(
-1'
-0:
-19
-1E
-0=
-0F
-#590625
-1)
-1;
-1>
-#593750
-1(
-1:
-1=
-1A
-#594000
-0)
-0;
-0>
-0A
-#597375
-1)
-1;
-1>
-1A
-#600000
-0(
-0'
-0&
-0%
-0$
-1#
-0:
-09
-08
-07
-06
-15
-1C
-0?
-0@
-0D
-0E
-0=
-0A
-#600750
-0)
-0;
-0>
-1A
-#604125
-1)
-1;
-1>
-0A
-#606250
-1(
-1:
-1=
-#607500
-0)
-0;
-0>
-#610875
-1)
-1;
-1>
-#612500
-0(
-1'
-0:
-19
-1E
-0=
-#614250
-0)
-0;
-0>
-1A
-#617625
-1)
-1;
-1>
-0A
-#618750
-1(
-1:
-1=
-#621000
-0)
-0;
-0>
-#624375
-1)
-1;
-1>
-#625000
-0(
-0'
-1&
-0:
-09
-18
-1D
-0E
-0=
-#627750
-0)
-0;
-0>
-1A
-#631125
-1)
-1;
-1>
-0A
-#631250
-1(
-1:
-1=
-#634500
-0)
-0;
-0>
-#637500
-0(
-1'
-0:
-19
-1E
-0=
-1A
-1F
-1G
-1<
-13
-1!
-#637875
-1)
-1;
-1>
-0A
-0G
-0<
-03
-0!
-#641250
-0)
-0;
-0>
-1A
-1G
-1<
-13
-1!
-#643750
-1(
-1:
-1=
-0A
-0G
-0<
-03
-0!
-#644625
-1)
-1;
-1>
-#648000
-0)
-0;
-0>
-#650000
-0(
-0'
-0&
-1%
-0:
-09
-08
-17
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-0D
-0E
-0=
-0F
-#651375
-1)
-1;
-1>
-1A
-#654750
-0)
-0;
-0>
-0A
-#656250
-1(
-1:
-1=
-#658125
-1)
-1;
-1>
-#661500
-0)
-0;
-0>
-#662500
-0(
-1'
-0:
-19
-1E
-0=
-#664875
-1)
-1;
-1>
-1A
-#668250
-0)
-0;
-0>
-0A
-#668750
-1(
-1:
-1=
-#671625
-1)
-1;
-1>
-#675000
-0)
-0(
-0'
-1&
-0;
-0:
-09
-18
-1D
-0E
-0=
-0>
-#678375
-1)
-1;
-1>
-1A
-#681250
-1(
-1:
-1=
-0A
-#681750
-0)
-0;
-0>
-#685125
-1)
-1;
-1>
-#687500
-0(
-1'
-0:
-19
-1E
-0=
-1A
-1F
-1G
-1<
-13
-1!
-#688500
-0)
-0;
-0>
-0A
-0G
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-03
-0!
-#691875
-1)
-1;
-1>
-1A
-1G
-1<
-13
-1!
-#693750
-1(
-1:
-1=
-0A
-0G
-0<
-03
-0!
-#695250
-0)
-0;
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diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.sft b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.vho b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.vho
deleted file mode 100644
index e93df62..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.vho
+++ /dev/null
@@ -1,477 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/07/2023 20:57:58"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- AUD_ADCDAT => Location: PIN_D2, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- CLOCK2_50 => Location: PIN_AG14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- CLOCK3_50 => Location: PIN_AG15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- CLOCK_50 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_INT_N => Location: PIN_A21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_LINK100 => Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ENET0_MDIO => Location: PIN_B21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_CLK => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_COL => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_CRS => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[0] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[1] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[2] => Location: PIN_D17, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DATA[3] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_DV => Location: PIN_C17, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_RX_ER => Location: PIN_D18, I/O Standard: 2.5 V, Current Strength: Default
--- ENET0_TX_CLK => Location: PIN_B17, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_INT_N => Location: PIN_D24, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_LINK100 => Location: PIN_D13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ENET1_MDIO => Location: PIN_D25, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_CLK => Location: PIN_B15, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_COL => Location: PIN_B22, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_CRS => Location: PIN_D20, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[0] => Location: PIN_B23, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[1] => Location: PIN_C21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[2] => Location: PIN_A23, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DATA[3] => Location: PIN_D21, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_DV => Location: PIN_A22, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_RX_ER => Location: PIN_C24, I/O Standard: 2.5 V, Current Strength: Default
--- ENET1_TX_CLK => Location: PIN_C22, I/O Standard: 2.5 V, Current Strength: Default
--- ENETCLK_25 => Location: PIN_A14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- FL_RY => Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- HSMC_CLKIN0 => Location: PIN_AH15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- IRDA_RXD => Location: PIN_Y15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[2] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[3] => Location: PIN_R24, I/O Standard: 2.5 V, Current Strength: Default
--- OTG_INT => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- SD_WP_N => Location: PIN_AF14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- SMA_CLKIN => Location: PIN_AH14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- SW[10] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[11] => Location: PIN_AB24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[12] => Location: PIN_AB23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[13] => Location: PIN_AA24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[14] => Location: PIN_AA23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[15] => Location: PIN_AA22, I/O Standard: 2.5 V, Current Strength: Default
--- SW[16] => Location: PIN_Y24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[17] => Location: PIN_Y23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default
--- SW[9] => Location: PIN_AB25, I/O Standard: 2.5 V, Current Strength: Default
--- TD_CLK27 => Location: PIN_B14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[0] => Location: PIN_E8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[1] => Location: PIN_A7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[2] => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[3] => Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[4] => Location: PIN_D7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[5] => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[6] => Location: PIN_E7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_DATA[7] => Location: PIN_F7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_HS => Location: PIN_E5, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- TD_VS => Location: PIN_E4, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- UART_RTS => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- UART_RXD => Location: PIN_G12, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \AUD_ADCDAT~padout\ : std_logic;
-SIGNAL \CLOCK2_50~padout\ : std_logic;
-SIGNAL \CLOCK3_50~padout\ : std_logic;
-SIGNAL \CLOCK_50~padout\ : std_logic;
-SIGNAL \ENET0_INT_N~padout\ : std_logic;
-SIGNAL \ENET0_LINK100~padout\ : std_logic;
-SIGNAL \ENET0_MDIO~padout\ : std_logic;
-SIGNAL \ENET0_RX_CLK~padout\ : std_logic;
-SIGNAL \ENET0_RX_COL~padout\ : std_logic;
-SIGNAL \ENET0_RX_CRS~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[0]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[1]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[2]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DATA[3]~padout\ : std_logic;
-SIGNAL \ENET0_RX_DV~padout\ : std_logic;
-SIGNAL \ENET0_RX_ER~padout\ : std_logic;
-SIGNAL \ENET0_TX_CLK~padout\ : std_logic;
-SIGNAL \ENET1_INT_N~padout\ : std_logic;
-SIGNAL \ENET1_LINK100~padout\ : std_logic;
-SIGNAL \ENET1_MDIO~padout\ : std_logic;
-SIGNAL \ENET1_RX_CLK~padout\ : std_logic;
-SIGNAL \ENET1_RX_COL~padout\ : std_logic;
-SIGNAL \ENET1_RX_CRS~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[0]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[1]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[2]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DATA[3]~padout\ : std_logic;
-SIGNAL \ENET1_RX_DV~padout\ : std_logic;
-SIGNAL \ENET1_RX_ER~padout\ : std_logic;
-SIGNAL \ENET1_TX_CLK~padout\ : std_logic;
-SIGNAL \ENETCLK_25~padout\ : std_logic;
-SIGNAL \FL_RY~padout\ : std_logic;
-SIGNAL \HSMC_CLKIN0~padout\ : std_logic;
-SIGNAL \IRDA_RXD~padout\ : std_logic;
-SIGNAL \KEY[0]~padout\ : std_logic;
-SIGNAL \KEY[1]~padout\ : std_logic;
-SIGNAL \KEY[2]~padout\ : std_logic;
-SIGNAL \KEY[3]~padout\ : std_logic;
-SIGNAL \OTG_INT~padout\ : std_logic;
-SIGNAL \SD_WP_N~padout\ : std_logic;
-SIGNAL \SMA_CLKIN~padout\ : std_logic;
-SIGNAL \TD_CLK27~padout\ : std_logic;
-SIGNAL \TD_DATA[0]~padout\ : std_logic;
-SIGNAL \TD_DATA[1]~padout\ : std_logic;
-SIGNAL \TD_DATA[2]~padout\ : std_logic;
-SIGNAL \TD_DATA[3]~padout\ : std_logic;
-SIGNAL \TD_DATA[4]~padout\ : std_logic;
-SIGNAL \TD_DATA[5]~padout\ : std_logic;
-SIGNAL \TD_DATA[6]~padout\ : std_logic;
-SIGNAL \TD_DATA[7]~padout\ : std_logic;
-SIGNAL \TD_HS~padout\ : std_logic;
-SIGNAL \TD_VS~padout\ : std_logic;
-SIGNAL \UART_RTS~padout\ : std_logic;
-SIGNAL \UART_RXD~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \AUD_ADCDAT~ibuf_o\ : std_logic;
-SIGNAL \CLOCK2_50~ibuf_o\ : std_logic;
-SIGNAL \CLOCK3_50~ibuf_o\ : std_logic;
-SIGNAL \CLOCK_50~ibuf_o\ : std_logic;
-SIGNAL \ENET0_INT_N~ibuf_o\ : std_logic;
-SIGNAL \ENET0_LINK100~ibuf_o\ : std_logic;
-SIGNAL \ENET0_MDIO~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_COL~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_CRS~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[0]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[1]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[2]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DATA[3]~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_DV~ibuf_o\ : std_logic;
-SIGNAL \ENET0_RX_ER~ibuf_o\ : std_logic;
-SIGNAL \ENET0_TX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENET1_INT_N~ibuf_o\ : std_logic;
-SIGNAL \ENET1_LINK100~ibuf_o\ : std_logic;
-SIGNAL \ENET1_MDIO~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_COL~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_CRS~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[0]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[1]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[2]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DATA[3]~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_DV~ibuf_o\ : std_logic;
-SIGNAL \ENET1_RX_ER~ibuf_o\ : std_logic;
-SIGNAL \ENET1_TX_CLK~ibuf_o\ : std_logic;
-SIGNAL \ENETCLK_25~ibuf_o\ : std_logic;
-SIGNAL \FL_RY~ibuf_o\ : std_logic;
-SIGNAL \HSMC_CLKIN0~ibuf_o\ : std_logic;
-SIGNAL \IRDA_RXD~ibuf_o\ : std_logic;
-SIGNAL \KEY[0]~ibuf_o\ : std_logic;
-SIGNAL \KEY[1]~ibuf_o\ : std_logic;
-SIGNAL \KEY[2]~ibuf_o\ : std_logic;
-SIGNAL \KEY[3]~ibuf_o\ : std_logic;
-SIGNAL \OTG_INT~ibuf_o\ : std_logic;
-SIGNAL \SD_WP_N~ibuf_o\ : std_logic;
-SIGNAL \SMA_CLKIN~ibuf_o\ : std_logic;
-SIGNAL \SW[10]~ibuf_o\ : std_logic;
-SIGNAL \SW[11]~ibuf_o\ : std_logic;
-SIGNAL \SW[12]~ibuf_o\ : std_logic;
-SIGNAL \SW[13]~ibuf_o\ : std_logic;
-SIGNAL \SW[14]~ibuf_o\ : std_logic;
-SIGNAL \SW[15]~ibuf_o\ : std_logic;
-SIGNAL \SW[16]~ibuf_o\ : std_logic;
-SIGNAL \SW[17]~ibuf_o\ : std_logic;
-SIGNAL \SW[8]~ibuf_o\ : std_logic;
-SIGNAL \SW[9]~ibuf_o\ : std_logic;
-SIGNAL \TD_CLK27~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[0]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[1]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[2]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[3]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[4]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[5]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[6]~ibuf_o\ : std_logic;
-SIGNAL \TD_DATA[7]~ibuf_o\ : std_logic;
-SIGNAL \TD_HS~ibuf_o\ : std_logic;
-SIGNAL \TD_VS~ibuf_o\ : std_logic;
-SIGNAL \UART_RTS~ibuf_o\ : std_logic;
-SIGNAL \UART_RXD~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-SIGNAL SW : std_logic_vector(7 DOWNTO 0);
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY EqCmpDemo IS
- PORT (
- LEDG : OUT std_logic_vector(0 DOWNTO 0);
- SW : IN std_logic_vector(7 DOWNTO 0)
- );
-END EqCmpDemo;
-
--- Design Ports Information
--- LEDG[0] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default
--- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF EqCmpDemo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDG : std_logic_vector(0 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(7 DOWNTO 0);
-SIGNAL \LEDG[0]~output_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \SW[5]~input_o\ : std_logic;
-SIGNAL \SW[4]~input_o\ : std_logic;
-SIGNAL \inst1|inst~0_combout\ : std_logic;
-SIGNAL \SW[7]~input_o\ : std_logic;
-SIGNAL \SW[6]~input_o\ : std_logic;
-SIGNAL \SW[3]~input_o\ : std_logic;
-SIGNAL \SW[2]~input_o\ : std_logic;
-SIGNAL \inst1|inst~1_combout\ : std_logic;
-SIGNAL \inst1|inst~combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-LEDG <= ww_LEDG;
-ww_SW <= SW;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X107_Y73_N9
-\LEDG[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst1|inst~combout\,
- devoe => ww_devoe,
- o => \LEDG[0]~output_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: IOIBUF_X115_Y11_N8
-\SW[5]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(5),
- o => \SW[5]~input_o\);
-
--- Location: IOIBUF_X115_Y18_N8
-\SW[4]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(4),
- o => \SW[4]~input_o\);
-
--- Location: LCCOMB_X114_Y15_N24
-\inst1|inst~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|inst~0_combout\ = (\SW[1]~input_o\ & (\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\)))) # (!\SW[1]~input_o\ & (!\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000010000100001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[1]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[5]~input_o\,
- datad => \SW[4]~input_o\,
- combout => \inst1|inst~0_combout\);
-
--- Location: IOIBUF_X115_Y15_N1
-\SW[7]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(7),
- o => \SW[7]~input_o\);
-
--- Location: IOIBUF_X115_Y10_N1
-\SW[6]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(6),
- o => \SW[6]~input_o\);
-
--- Location: IOIBUF_X115_Y13_N8
-\SW[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(3),
- o => \SW[3]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N8
-\SW[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(2),
- o => \SW[2]~input_o\);
-
--- Location: LCCOMB_X114_Y15_N10
-\inst1|inst~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|inst~1_combout\ = (\SW[7]~input_o\ & (\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\)))) # (!\SW[7]~input_o\ & (!\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000010000100001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[7]~input_o\,
- datab => \SW[6]~input_o\,
- datac => \SW[3]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \inst1|inst~1_combout\);
-
--- Location: LCCOMB_X114_Y15_N28
-\inst1|inst\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|inst~combout\ = (\inst1|inst~0_combout\ & \inst1|inst~1_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100110000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|inst~0_combout\,
- datad => \inst1|inst~1_combout\,
- combout => \inst1|inst~combout\);
-
-ww_LEDG(0) <= \LEDG[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205001.sim.vwf b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205001.sim.vwf
deleted file mode 100644
index 955b9f3..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205001.sim.vwf
+++ /dev/null
@@ -1,1863 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("LEDG")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("LEDG[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("SW")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 16;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("SW[15]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[14]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[13]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[12]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[11]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[10]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[9]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[8]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[7]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[6]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[5]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[4]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-TRANSITION_LIST("LEDG")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL X FOR 1000.0;
- }
-}
-
-TRANSITION_LIST("LEDG[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 1000.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[15]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 400.0;
- LEVEL 1 FOR 400.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[14]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[13]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[12]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[11]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[10]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- }
- }
-}
-
-TRANSITION_LIST("SW[9]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- }
- }
-}
-
-TRANSITION_LIST("SW[8]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 1.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[7]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 400.0;
- LEVEL 1 FOR 400.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[6]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[5]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[4]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- }
- }
-}
-
-TRANSITION_LIST("SW[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- }
- }
-}
-
-TRANSITION_LIST("SW[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 1.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
- CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[15]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[14]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[13]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[12]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[11]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 5;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[10]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 6;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[9]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 7;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[8]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 8;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[7]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 9;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[6]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 10;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[5]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 11;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[4]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 12;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 13;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 14;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 15;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 16;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDG";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 17;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDG[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 18;
- TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205136.sim.vwf b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205136.sim.vwf
deleted file mode 100644
index 955b9f3..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205136.sim.vwf
+++ /dev/null
@@ -1,1863 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("LEDG")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("LEDG[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("SW")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 16;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("SW[15]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[14]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[13]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[12]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[11]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[10]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[9]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[8]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[7]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[6]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[5]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[4]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-TRANSITION_LIST("LEDG")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL X FOR 1000.0;
- }
-}
-
-TRANSITION_LIST("LEDG[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 1000.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[15]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 400.0;
- LEVEL 1 FOR 400.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[14]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[13]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[12]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[11]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[10]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- }
- }
-}
-
-TRANSITION_LIST("SW[9]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- }
- }
-}
-
-TRANSITION_LIST("SW[8]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 1.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[7]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 400.0;
- LEVEL 1 FOR 400.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[6]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[5]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[4]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- }
- }
-}
-
-TRANSITION_LIST("SW[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- }
- }
-}
-
-TRANSITION_LIST("SW[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 1.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
- CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[15]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[14]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[13]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[12]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[11]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 5;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[10]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 6;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[9]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 7;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[8]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 8;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[7]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 9;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[6]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 10;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[5]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 11;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[4]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 12;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 13;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 14;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 15;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 16;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDG";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 17;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDG[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 18;
- TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205353.sim.vwf b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205353.sim.vwf
deleted file mode 100644
index fdfad9c..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205353.sim.vwf
+++ /dev/null
@@ -1,2252 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("LEDG")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("LEDG[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("SW")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 16;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("SW[15]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[14]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[13]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[12]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[11]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[10]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[9]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[8]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[7]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[6]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[5]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[4]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-TRANSITION_LIST("LEDG")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL X FOR 1000.0;
- }
-}
-
-TRANSITION_LIST("LEDG[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 525.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 395.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 70.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[15]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 30.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 35.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 35.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[14]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 30.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[13]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 25.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[12]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[11]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 35.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[10]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[9]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 30.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 45.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 45.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[8]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[7]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 35.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 30.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[6]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 35.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 35.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 30.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[5]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 30.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 25.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[4]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 30.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 30.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 35.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 35.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 45.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 35.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 10.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 35.0;
- LEVEL 1 FOR 35.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 35.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
- CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[15]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[14]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[13]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[12]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[11]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 5;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[10]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 6;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[9]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 7;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[8]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 8;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[7]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 9;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[6]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 10;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[5]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 11;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[4]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 12;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 13;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 14;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 15;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 16;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDG";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 17;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDG[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 18;
- TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205759.sim.vwf b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205759.sim.vwf
deleted file mode 100644
index 54f277d..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205759.sim.vwf
+++ /dev/null
@@ -1,1053 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("LEDG")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("LEDG[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("SW")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 8;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("SW[7]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[6]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[5]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[4]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-SIGNAL("SW[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "SW";
-}
-
-TRANSITION_LIST("LEDG")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL X FOR 1000.0;
- }
-}
-
-TRANSITION_LIST("LEDG[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 47.25;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 54.0;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 47.25;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 50.5;
- LEVEL 1 FOR 0.125;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 2.75;
- LEVEL 0 FOR 43.75;
- LEVEL 1 FOR 0.75;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 2.125;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 1.875;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 1.0;
- LEVEL 0 FOR 43.75;
- LEVEL 1 FOR 2.5;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 0.375;
- LEVEL 0 FOR 50.25;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 47.25;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 54.0;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 47.25;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 50.25;
- LEVEL 1 FOR 0.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 2.5;
- LEVEL 0 FOR 43.75;
- LEVEL 1 FOR 1.0;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 1.875;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 2.125;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 0.75;
- LEVEL 0 FOR 43.75;
- LEVEL 1 FOR 2.75;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 0.125;
- LEVEL 0 FOR 3.25;
- LEVEL 1 FOR 3.0;
- LEVEL 0 FOR 43.75;
- LEVEL 1 FOR 0.5;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 2.375;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 1.625;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 1.25;
- LEVEL 0 FOR 43.75;
- LEVEL 1 FOR 2.25;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 0.625;
- LEVEL 0 FOR 37.5;
- }
- }
-}
-
-TRANSITION_LIST("SW[7]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 400.0;
- LEVEL 1 FOR 400.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[6]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[5]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[4]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- }
- }
-}
-
-TRANSITION_LIST("SW[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- }
- }
-}
-
-TRANSITION_LIST("SW[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- LEVEL 0 FOR 6.25;
- LEVEL 1 FOR 6.25;
- }
- }
-}
-
-TRANSITION_LIST("SW[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 3.375;
- LEVEL 1 FOR 3.375;
- LEVEL 0 FOR 1.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
- CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[7]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[6]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[5]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[4]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 5;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 6;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 7;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "SW[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 8;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDG";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 9;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "LEDG[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 10;
- TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_modelsim.xrf
deleted file mode 100644
index c16151c..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_modelsim.xrf
+++ /dev/null
@@ -1,24 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.bdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vwf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cbx.xml
-design_name = hard_block
-design_name = EqCmpDemo
-instance = comp, \LEDG[0]~output\, LEDG[0]~output, EqCmpDemo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, EqCmpDemo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, EqCmpDemo, 1
-instance = comp, \SW[5]~input\, SW[5]~input, EqCmpDemo, 1
-instance = comp, \SW[4]~input\, SW[4]~input, EqCmpDemo, 1
-instance = comp, \inst1|inst~0\, inst1|inst~0, EqCmpDemo, 1
-instance = comp, \SW[7]~input\, SW[7]~input, EqCmpDemo, 1
-instance = comp, \SW[6]~input\, SW[6]~input, EqCmpDemo, 1
-instance = comp, \SW[3]~input\, SW[3]~input, EqCmpDemo, 1
-instance = comp, \SW[2]~input\, SW[2]~input, EqCmpDemo, 1
-instance = comp, \inst1|inst~1\, inst1|inst~1, EqCmpDemo, 1
-instance = comp, \inst1|inst\, inst1|inst, EqCmpDemo, 1
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/transcript
deleted file mode 100644
index 3de5311..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/transcript
+++ /dev/null
@@ -1,47 +0,0 @@
-# do EqCmpDemo.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 20:57:58 on Mar 07,2023
-# vcom -work work EqCmpDemo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity hard_block
-# -- Compiling architecture structure of hard_block
-# -- Compiling entity EqCmpDemo
-# -- Compiling architecture structure of EqCmpDemo
-# End time: 20:57:58 on Mar 07,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 20:57:58 on Mar 07,2023
-# vcom -work work EqCmp4.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity EqCmpDemo_vhd_vec_tst
-# -- Compiling architecture EqCmpDemo_arch of EqCmpDemo_vhd_vec_tst
-# End time: 20:57:58 on Mar 07,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst
-# Start time: 20:57:58 on Mar 07,2023
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading work.eqcmpdemo_vhd_vec_tst(eqcmpdemo_arch)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading cycloneive.cycloneive_atom_pack(body)
-# Loading cycloneive.cycloneive_components
-# Loading work.eqcmpdemo(structure)
-# Loading work.hard_block(structure)
-# Loading ieee.std_logic_arith(body)
-# Loading cycloneive.cycloneive_io_obuf(arch)
-# Loading cycloneive.cycloneive_io_ibuf(arch)
-# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#33
-# End time: 20:57:58 on Mar 07,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/vwf_sim_transcript
deleted file mode 100644
index ba96e97..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/vwf_sim_transcript
+++ /dev/null
@@ -1,60 +0,0 @@
-Determining the location of the ModelSim executable...
-
-Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
-
-To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
-Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
-
-**** Generating the ModelSim Testbench ****
-
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht"
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Mar 7 20:57:56 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vhtWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Completed successfully.
-
-**** Generating the functional simulation netlist ****
-
-quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/" EqCmpDemo -c EqCmpDemo
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Mar 7 20:57:57 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/ EqCmpDemo -c EqCmpDemoWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file EqCmpDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 613 megabytes Info: Processing ended: Tue Mar 7 20:57:58 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00
-Completed successfully.
-
-**** Generating the ModelSim .do script ****
-
-/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.do generated.
-
-Completed successfully.
-
-**** Running the ModelSim simulation ****
-
-/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do EqCmpDemo.do
-
-Reading pref.tcl
-# 2020.1
-# do EqCmpDemo.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 20:57:58 on Mar 07,2023# vcom -work work EqCmpDemo.vho # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Loading package VITAL_Timing# -- Loading package VITAL_Primitives# -- Loading package cycloneive_atom_pack# -- Loading package cycloneive_components# -- Compiling entity hard_block# -- Compiling architecture structure of hard_block# -- Compiling entity EqCmpDemo# -- Compiling architecture structure of EqCmpDemo# End time: 20:57:58 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020# Start time: 20:57:58 on Mar 07,2023# vcom -work work EqCmp4.vwf.vht # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Compiling entity EqCmpDemo_vhd_vec_tst# -- Compiling architecture EqCmpDemo_arch of EqCmpDemo_vhd_vec_tst
-# End time: 20:57:58 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst # Start time: 20:57:58 on Mar 07,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.eqcmpdemo_vhd_vec_tst(eqcmpdemo_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.eqcmpdemo(structure)# Loading work.hard_block(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#33
-# End time: 20:57:58 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-Completed successfully.
-
-**** Converting ModelSim VCD to vector waveform ****
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf...
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.msim.vcd...
-
-Processing channel transitions...
-
-Warning: LEDG - signal not found in VCD.
-
-Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205759.sim.vwf
-
-Finished VCD to VWF conversion.
-
-Completed successfully.
-
-All completed.
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_info
deleted file mode 100644
index bb7ec70..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_info
+++ /dev/null
@@ -1,150 +0,0 @@
-m255
-K4
-z2
-!s11e vcom 2020.1 2020.02, Feb 28 2020
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-Z0 d/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim
-Eeqcmpdemo
-Z1 w1678222678
-Z2 DPx4 ieee 16 vital_primitives 0 22 G>kiXP8Q9dRClKfK1Zn7j1
-Z3 DPx10 cycloneive 20 cycloneive_atom_pack 0 22 WOh:M[al;oVzG5c`D0
-Z4 DPx4 ieee 12 vital_timing 0 22 J>EBealN09f8GzldA[z2>3
-Z5 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
-Z6 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
-Z7 DPx10 cycloneive 21 cycloneive_components 0 22 zGMDhP>8e@2k@f0e0
-!s100 EAzGZnge^cK[[`MOG6]P?1
-R10
-32
-R11
-!i10b 1
-R12
-Z20 !s90 -work|work|EqCmp4.vwf.vht|
-!s107 EqCmp4.vwf.vht|
-!i113 1
-R15
-R16
-Aeqcmpdemo_arch
-R5
-R6
-Z21 DEx4 work 21 eqcmpdemo_vhd_vec_tst 0 22 b:JYio=d0EkMR9d]fR]j>0
-!i122 7
-l45
-L34 110
-VjJYZm]EZdnJY9lR<;VGY63
-!s100 aKZFbkF_ioJomXi5[`cD`bFC`UBKAVK81oX[5d;^2
-!s100 iaEzY@oUOcmJQf1
-R10
-32
-R11
-!i10b 1
-R12
-R13
-R14
-!i113 1
-R15
-R16
diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_lib.qdb b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_lib.qdb
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diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_lib1_1.qdb b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_lib1_1.qdb
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diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_lib1_1.qpg b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_lib1_1.qpg
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diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_lib1_1.qtl b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_lib1_1.qtl
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diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_vmake b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_vmake
deleted file mode 100644
index 37aa36a..0000000
--- a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/work/_vmake
+++ /dev/null
@@ -1,4 +0,0 @@
-m255
-K4
-z0
-cModel Technology
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.vhd.bak b/1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.vhd.bak
deleted file mode 100644
index f3e8536..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.vhd.bak
+++ /dev/null
@@ -1,30 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity Bin7SegDecoder is
- port
- (
- binInput : in std_logic_vector(3 downto 0);
- decOut_n : out std_logic_vector(6 downto 0)
- );
-end Bin7SegDecoder;
-
-architecture Behavioral of Bin7SegDecoder is
-begin
- decOut_n <= "1111001" when (binInput = "0001") else --1
- "0100100" when (binInput = "0010") else --2
- "0110000" when (binInput = "0011") else --3
- "0011001" when (binInput = "0100") else --4
- "0010010" when (binInput = "0101") else --5
- "0000010" when (binInput = "0110") else --6
- "1111000" when (binInput = "0111") else --7
- "0000000" when (binInput = "1000") else --8
- "0010000" when (binInput = "1001") else --9
- "0001000" when (binInput = "1010") else --A
- "0000011" when (binInput = "1011") else --b
- "1000110" when (binInput = "1100") else --C
- "0100001" when (binInput = "1101") else --d
- "0000110" when (binInput = "1110") else --E
- "0001110" when (binInput = "1111") else --F
- "1000000"; --0
-end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.qpf b/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.qpf
deleted file mode 100644
index b08aef1..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 17:38:03 March 08, 2023
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "20.1"
-DATE = "17:38:03 March 08, 2023"
-
-# Revisions
-
-PROJECT_REVISION = "DisplayDemo"
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.qsf b/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.qsf
deleted file mode 100644
index 0748dfd..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.qsf
+++ /dev/null
@@ -1,584 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 17:38:03 March 08, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# DisplayDemo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY DisplayDemo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:38:03 MARCH 08, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VHDL_FILE Bin7SegDecoder.vhd
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name BDF_FILE DisplayDemo.bdf
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.qsf.bak b/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.qsf.bak
deleted file mode 100644
index 6bf4ea0..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.qsf.bak
+++ /dev/null
@@ -1,584 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 17:38:03 March 08, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# DisplayDemo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY Bin7SegDecoder
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:38:03 MARCH 08, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VHDL_FILE Bin7SegDecoder.vhd
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name BDF_FILE DisplayDemo.bdf
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.qws b/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.qws
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.vhd.bak b/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.vhd.bak
deleted file mode 100644
index e69de29..0000000
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.(0).cnf.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.(0).cnf.cdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.(0).cnf.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.(0).cnf.hdb
deleted file mode 100644
index 25a6cc2..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.(1).cnf.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.(1).cnf.cdb
deleted file mode 100644
index 4bdea98..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.(1).cnf.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.(1).cnf.hdb
deleted file mode 100644
index 20d7c36..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.(2).cnf.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.(2).cnf.cdb
deleted file mode 100644
index e5feb19..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.(2).cnf.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.(2).cnf.hdb
deleted file mode 100644
index f1671ae..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.asm.qmsg b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.asm.qmsg
deleted file mode 100644
index 55877df..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.asm.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678356757953 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678356757953 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 10:12:37 2023 " "Processing started: Thu Mar 9 10:12:37 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678356757953 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678356757953 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678356757953 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678356758125 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678356760271 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678356760408 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "365 " "Peak virtual memory: 365 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678356760669 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 10:12:40 2023 " "Processing ended: Thu Mar 9 10:12:40 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678356760669 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678356760669 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678356760669 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678356760669 ""}
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.asm.rdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.asm.rdb
deleted file mode 100644
index 3164359..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.asm.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.asm_labs.ddb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.asm_labs.ddb
deleted file mode 100644
index c18481a..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.asm_labs.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cbx.xml b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cbx.xml
deleted file mode 100644
index 2672780..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.bpm b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.bpm
deleted file mode 100644
index 1b401d8..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.bpm and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.cdb
deleted file mode 100644
index 24d5d94..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.hdb
deleted file mode 100644
index ea90003..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.idb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.idb
deleted file mode 100644
index 9834e48..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.idb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.logdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.logdb
deleted file mode 100644
index 46f99c7..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.logdb
+++ /dev/null
@@ -1,65 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;23;23;0;0;23;23;0;0;0;0;0;0;18;0;0;0;5;18;0;5;0;0;18;0;23;23;23;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,23;0;0;23;23;0;0;23;23;23;23;23;23;5;23;23;23;18;5;23;18;23;23;5;23;0;0;0;23;23,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDG[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDG[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDG[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDG[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.rdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.rdb
deleted file mode 100644
index d91159d..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp_merge.kpt b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp_merge.kpt
deleted file mode 100644
index 515d5a3..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cmp_merge.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index 12d57d7..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
deleted file mode 100644
index 218eca7..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
deleted file mode 100644
index bea9e20..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.db_info b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.db_info
deleted file mode 100644
index 4bbc36d..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Thu Mar 9 10:12:12 2023
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.eda.qmsg b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.eda.qmsg
deleted file mode 100644
index 184e906..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678356763905 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678356763905 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 10:12:43 2023 " "Processing started: Thu Mar 9 10:12:43 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678356763905 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678356763905 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678356763905 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678356764100 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "DisplayDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/ simulation " "Generated file DisplayDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678356764143 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "611 " "Peak virtual memory: 611 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678356764165 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 10:12:44 2023 " "Processing ended: Thu Mar 9 10:12:44 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678356764165 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678356764165 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678356764165 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678356764165 ""}
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.fit.qmsg b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.fit.qmsg
deleted file mode 100644
index 42e50cf..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.fit.qmsg
+++ /dev/null
@@ -1,48 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678356749428 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678356749428 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "DisplayDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"DisplayDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678356749431 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678356749478 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678356749478 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678356749775 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678356749792 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678356749927 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678356749927 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678356749927 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678356749927 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678356749927 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678356749927 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678356749927 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678356749927 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678356749927 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678356749927 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/" { { 0 { 0 ""} 0 607 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678356749933 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/" { { 0 { 0 ""} 0 609 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678356749933 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/" { { 0 { 0 ""} 0 611 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678356749933 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/" { { 0 { 0 ""} 0 613 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678356749933 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/" { { 0 { 0 ""} 0 615 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678356749933 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678356749933 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678356749941 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DisplayDemo.sdc " "Synopsys Design Constraints File file not found: 'DisplayDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678356750613 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678356750614 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678356750614 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678356750614 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678356750615 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678356750615 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678356750616 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678356750619 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678356750619 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678356750620 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678356750620 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678356750620 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678356750620 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678356750620 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678356750621 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678356750621 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678356750621 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678356750621 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678356750644 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678356750644 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678356750651 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678356750657 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678356752384 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678356752488 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678356752519 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678356752698 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678356752698 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678356752890 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y61 X115_Y73 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y61 to location X115_Y73" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y61 to location X115_Y73"} { { 12 { 0 ""} 104 61 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678356755730 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678356755730 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678356755896 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678356755896 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678356755896 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678356755897 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678356756005 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678356756011 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678356756263 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678356756263 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678356756448 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678356756765 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678356756979 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678356757032 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 503 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 503 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1149 " "Peak virtual memory: 1149 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678356757221 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 10:12:37 2023 " "Processing ended: Thu Mar 9 10:12:37 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678356757221 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678356757221 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678356757221 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678356757221 ""}
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.hier_info b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.hier_info
deleted file mode 100644
index 8716b69..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.hier_info
+++ /dev/null
@@ -1,107 +0,0 @@
-|DisplayDemo
-HEX0[0] <= Bin7SegDecoder:inst.decOut_n[0]
-HEX0[1] <= Bin7SegDecoder:inst.decOut_n[1]
-HEX0[2] <= Bin7SegDecoder:inst.decOut_n[2]
-HEX0[3] <= Bin7SegDecoder:inst.decOut_n[3]
-HEX0[4] <= Bin7SegDecoder:inst.decOut_n[4]
-HEX0[5] <= Bin7SegDecoder:inst.decOut_n[5]
-HEX0[6] <= Bin7SegDecoder:inst.decOut_n[6]
-KEY[0] => Bin7SegDecoder:inst.enable
-SW[0] => Bin7SegDecoder:inst.binInput[0]
-SW[0] => LEDG[0].DATAIN
-SW[1] => Bin7SegDecoder:inst.binInput[1]
-SW[1] => LEDG[1].DATAIN
-SW[2] => Bin7SegDecoder:inst.binInput[2]
-SW[2] => LEDG[2].DATAIN
-SW[3] => Bin7SegDecoder:inst.binInput[3]
-SW[3] => LEDG[3].DATAIN
-LEDG[0] <= SW[0].DB_MAX_OUTPUT_PORT_TYPE
-LEDG[1] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE
-LEDG[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE
-LEDG[3] <= SW[3].DB_MAX_OUTPUT_PORT_TYPE
-LEDR[0] <= Bin7SegDecoder:inst.decOut_n[0]
-LEDR[1] <= Bin7SegDecoder:inst.decOut_n[1]
-LEDR[2] <= Bin7SegDecoder:inst.decOut_n[2]
-LEDR[3] <= Bin7SegDecoder:inst.decOut_n[3]
-LEDR[4] <= Bin7SegDecoder:inst.decOut_n[4]
-LEDR[5] <= Bin7SegDecoder:inst.decOut_n[5]
-LEDR[6] <= Bin7SegDecoder:inst.decOut_n[6]
-
-
-|DisplayDemo|Bin7SegDecoder:inst
-binInput[0] => Equal0.IN3
-binInput[0] => Equal1.IN0
-binInput[0] => Equal2.IN3
-binInput[0] => Equal3.IN1
-binInput[0] => Equal4.IN3
-binInput[0] => Equal5.IN1
-binInput[0] => Equal6.IN3
-binInput[0] => Equal7.IN2
-binInput[0] => Equal8.IN3
-binInput[0] => Equal9.IN1
-binInput[0] => Equal10.IN3
-binInput[0] => Equal11.IN2
-binInput[0] => Equal12.IN3
-binInput[0] => Equal13.IN2
-binInput[0] => Equal14.IN3
-binInput[1] => Equal0.IN2
-binInput[1] => Equal1.IN3
-binInput[1] => Equal2.IN0
-binInput[1] => Equal3.IN0
-binInput[1] => Equal4.IN2
-binInput[1] => Equal5.IN3
-binInput[1] => Equal6.IN1
-binInput[1] => Equal7.IN1
-binInput[1] => Equal8.IN2
-binInput[1] => Equal9.IN3
-binInput[1] => Equal10.IN1
-binInput[1] => Equal11.IN1
-binInput[1] => Equal12.IN2
-binInput[1] => Equal13.IN3
-binInput[1] => Equal14.IN2
-binInput[2] => Equal0.IN1
-binInput[2] => Equal1.IN2
-binInput[2] => Equal2.IN2
-binInput[2] => Equal3.IN3
-binInput[2] => Equal4.IN0
-binInput[2] => Equal5.IN0
-binInput[2] => Equal6.IN0
-binInput[2] => Equal7.IN0
-binInput[2] => Equal8.IN1
-binInput[2] => Equal9.IN2
-binInput[2] => Equal10.IN2
-binInput[2] => Equal11.IN3
-binInput[2] => Equal12.IN1
-binInput[2] => Equal13.IN1
-binInput[2] => Equal14.IN1
-binInput[3] => Equal0.IN0
-binInput[3] => Equal1.IN1
-binInput[3] => Equal2.IN1
-binInput[3] => Equal3.IN2
-binInput[3] => Equal4.IN1
-binInput[3] => Equal5.IN2
-binInput[3] => Equal6.IN2
-binInput[3] => Equal7.IN3
-binInput[3] => Equal8.IN0
-binInput[3] => Equal9.IN0
-binInput[3] => Equal10.IN0
-binInput[3] => Equal11.IN0
-binInput[3] => Equal12.IN0
-binInput[3] => Equal13.IN0
-binInput[3] => Equal14.IN0
-enable => decOut_n.OUTPUTSELECT
-enable => decOut_n.OUTPUTSELECT
-enable => decOut_n.OUTPUTSELECT
-enable => decOut_n.OUTPUTSELECT
-enable => decOut_n.OUTPUTSELECT
-enable => decOut_n.OUTPUTSELECT
-enable => decOut_n.OUTPUTSELECT
-decOut_n[0] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[1] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[2] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[3] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[4] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[5] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[6] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.hif b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.hif
deleted file mode 100644
index 2dc4fa5..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.hif and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.lpc.html b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.lpc.html
deleted file mode 100644
index f5dc641..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.lpc.html
+++ /dev/null
@@ -1,34 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| inst |
-5 |
-0 |
-0 |
-0 |
-7 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.lpc.rdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.lpc.rdb
deleted file mode 100644
index f88028b..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.lpc.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.lpc.txt b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.lpc.txt
deleted file mode 100644
index a16c069..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.lpc.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; inst ; 5 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map.ammdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map.ammdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map.kpt b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map.kpt
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index d1f69a2..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map.logdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map.qmsg b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map.qmsg
deleted file mode 100644
index 5d84066..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map.qmsg
+++ /dev/null
@@ -1,13 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678356741147 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678356741147 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 10:12:21 2023 " "Processing started: Thu Mar 9 10:12:21 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678356741147 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678356741147 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DisplayDemo -c DisplayDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678356741147 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678356741296 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678356741296 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Bin7SegDecoder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Bin7SegDecoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Bin7SegDecoder-Behavioral " "Found design unit 1: Bin7SegDecoder-Behavioral" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678356746968 ""} { "Info" "ISGN_ENTITY_NAME" "1 Bin7SegDecoder " "Found entity 1: Bin7SegDecoder" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678356746968 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678356746968 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DisplayDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file DisplayDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DisplayDemo " "Found entity 1: DisplayDemo" { } { { "DisplayDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678356746968 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678356746968 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "DisplayDemo " "Elaborating entity \"DisplayDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678356747026 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Bin7SegDecoder Bin7SegDecoder:inst " "Elaborating entity \"Bin7SegDecoder\" for hierarchy \"Bin7SegDecoder:inst\"" { } { { "DisplayDemo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.bdf" { { 280 544 752 360 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678356747028 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678356747527 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678356747881 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678356747881 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "37 " "Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678356748079 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678356748079 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678356748079 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678356748079 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "434 " "Peak virtual memory: 434 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678356748085 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 10:12:28 2023 " "Processing ended: Thu Mar 9 10:12:28 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678356748085 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678356748085 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678356748085 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678356748085 ""}
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map.rdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map.rdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map_bb.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map_bb.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map_bb.logdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.pre_map.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.root_partition.map.reg_db.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.routing.rdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.rtlv.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.rtlv_sg.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.rtlv_sg.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.rtlv_sg_swap.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.rtlv_sg_swap.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.sld_design_entry.sci b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.smart_action.txt b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.smart_action.txt
deleted file mode 100644
index c8e8a13..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.sta.qmsg b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.sta.qmsg
deleted file mode 100644
index eb8f93b..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678356761336 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678356761337 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 10:12:41 2023 " "Processing started: Thu Mar 9 10:12:41 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678356761337 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678356761337 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DisplayDemo -c DisplayDemo " "Command: quartus_sta DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678356761337 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678356761368 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678356761470 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678356761470 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678356761530 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678356761530 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DisplayDemo.sdc " "Synopsys Design Constraints File file not found: 'DisplayDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678356761973 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678356761973 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678356761973 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678356761974 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678356761974 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678356761974 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678356761975 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678356761980 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678356761980 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356761982 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356761984 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356761985 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356761985 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356761986 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356761986 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678356761988 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678356762009 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678356762282 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678356762301 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678356762301 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678356762302 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678356762302 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356762302 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356762303 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356762304 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356762304 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356762305 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356762305 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678356762308 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678356762359 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678356762359 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678356762359 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678356762360 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356762360 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356762361 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356762362 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356762362 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678356762362 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678356762646 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678356762646 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "536 " "Peak virtual memory: 536 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678356762659 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 10:12:42 2023 " "Processing ended: Thu Mar 9 10:12:42 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678356762659 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678356762659 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678356762659 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678356762659 ""}
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.sta.rdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.sta.rdb
deleted file mode 100644
index 4903e55..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.sta_cmp.7_slow_1200mv_85c.tdb
deleted file mode 100644
index 9cdb6c9..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.sta_cmp.7_slow_1200mv_85c.tdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tis_db_list.ddb
deleted file mode 100644
index 73e5ec9..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tis_db_list.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index 2c21837..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index 2104588..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tiscmp.slow_1200mv_0c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index 0abee68..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tmw_info b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tmw_info
deleted file mode 100644
index 0488171..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tmw_info
+++ /dev/null
@@ -1,7 +0,0 @@
-start_full_compilation:s:00:00:24
-start_analysis_synthesis:s:00:00:08-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:09-start_full_compilation
-start_assembler:s:00:00:03-start_full_compilation
-start_timing_analyzer:s:00:00:03-start_full_compilation
-start_eda_netlist_writer:s:00:00:01-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.vpr.ammdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.vpr.ammdb
deleted file mode 100644
index 2c90126..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo_partition_pins.json b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo_partition_pins.json
deleted file mode 100644
index b6f9f13..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo_partition_pins.json
+++ /dev/null
@@ -1,101 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "HEX0[6]",
- "strict" : false
- },
- {
- "name" : "HEX0[5]",
- "strict" : false
- },
- {
- "name" : "HEX0[4]",
- "strict" : false
- },
- {
- "name" : "HEX0[3]",
- "strict" : false
- },
- {
- "name" : "HEX0[2]",
- "strict" : false
- },
- {
- "name" : "HEX0[1]",
- "strict" : false
- },
- {
- "name" : "HEX0[0]",
- "strict" : false
- },
- {
- "name" : "LEDG[3]",
- "strict" : false
- },
- {
- "name" : "LEDG[2]",
- "strict" : false
- },
- {
- "name" : "LEDG[1]",
- "strict" : false
- },
- {
- "name" : "LEDG[0]",
- "strict" : false
- },
- {
- "name" : "LEDR[6]",
- "strict" : false
- },
- {
- "name" : "LEDR[5]",
- "strict" : false
- },
- {
- "name" : "LEDR[4]",
- "strict" : false
- },
- {
- "name" : "LEDR[3]",
- "strict" : false
- },
- {
- "name" : "LEDR[2]",
- "strict" : false
- },
- {
- "name" : "LEDR[1]",
- "strict" : false
- },
- {
- "name" : "LEDR[0]",
- "strict" : false
- },
- {
- "name" : "KEY[0]",
- "strict" : false
- },
- {
- "name" : "SW[2]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- },
- {
- "name" : "SW[3]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/prev_cmp_DisplayDemo.qmsg b/1ano/2semestre/lsd/pratica02/DisplayDemo/db/prev_cmp_DisplayDemo.qmsg
deleted file mode 100644
index f2435f6..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/db/prev_cmp_DisplayDemo.qmsg
+++ /dev/null
@@ -1,133 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678297615321 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678297615321 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 17:46:55 2023 " "Processing started: Wed Mar 8 17:46:55 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678297615321 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678297615321 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DisplayDemo -c DisplayDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678297615322 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678297615490 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678297615490 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Bin7SegDecoder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Bin7SegDecoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Bin7SegDecoder-Behavioral " "Found design unit 1: Bin7SegDecoder-Behavioral" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678297622257 ""} { "Info" "ISGN_ENTITY_NAME" "1 Bin7SegDecoder " "Found entity 1: Bin7SegDecoder" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678297622257 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678297622257 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DisplayDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file DisplayDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DisplayDemo " "Found entity 1: DisplayDemo" { } { { "DisplayDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678297622258 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678297622258 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "DisplayDemo " "Elaborating entity \"DisplayDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678297622301 ""}
-{ "Warning" "WGDFX_PIN_IGNORED" "KEY " "Pin \"KEY\" not connected" { } { { "DisplayDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.bdf" { { 320 360 528 336 "KEY\[0\]" "" } } } } } 0 275009 "Pin \"%1!s!\" not connected" 0 0 "Analysis & Synthesis" 0 -1 1678297622303 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Bin7SegDecoder Bin7SegDecoder:inst " "Elaborating entity \"Bin7SegDecoder\" for hierarchy \"Bin7SegDecoder:inst\"" { } { { "DisplayDemo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.bdf" { { 280 544 752 360 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678297622305 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678297623058 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678297623622 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678297623622 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" { } { { "DisplayDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.bdf" { { 320 360 528 336 "KEY" "" } } } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1678297623651 "|DisplayDemo|KEY[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1678297623651 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "30 " "Implemented 30 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678297623651 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678297623651 ""} { "Info" "ICUT_CUT_TM_LCELLS" "7 " "Implemented 7 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678297623651 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678297623651 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "430 " "Peak virtual memory: 430 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678297623657 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 17:47:03 2023 " "Processing ended: Wed Mar 8 17:47:03 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678297623657 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678297623657 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678297623657 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678297623657 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1678297624529 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678297624530 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 17:47:04 2023 " "Processing started: Wed Mar 8 17:47:04 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678297624530 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1678297624530 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo " "Command: quartus_fit --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1678297624530 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1678297624562 ""}
-{ "Info" "0" "" "Project = DisplayDemo" { } { } 0 0 "Project = DisplayDemo" 0 0 "Fitter" 0 0 1678297624563 ""}
-{ "Info" "0" "" "Revision = DisplayDemo" { } { } 0 0 "Revision = DisplayDemo" 0 0 "Fitter" 0 0 1678297624563 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678297624626 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678297624626 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "DisplayDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"DisplayDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678297624630 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678297624696 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678297624696 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678297625091 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678297625100 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678297625168 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678297625168 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678297625168 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678297625168 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678297625168 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678297625168 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678297625168 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678297625168 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678297625168 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678297625168 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/" { { 0 { 0 ""} 0 598 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678297625171 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/" { { 0 { 0 ""} 0 600 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678297625171 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/" { { 0 { 0 ""} 0 602 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678297625171 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/" { { 0 { 0 ""} 0 604 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678297625171 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/" { { 0 { 0 ""} 0 606 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678297625171 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678297625171 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678297625173 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DisplayDemo.sdc " "Synopsys Design Constraints File file not found: 'DisplayDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678297625888 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678297625889 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678297625889 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678297625889 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678297625890 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678297625890 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678297625891 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678297625893 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678297625893 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678297625894 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678297625894 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678297625895 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678297625895 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678297625895 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678297625895 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678297625895 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678297625895 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678297625895 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678297625920 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678297625920 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678297625933 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678297625935 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678297628136 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678297628243 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678297628286 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678297628503 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678297628503 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678297628684 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y61 X115_Y73 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y61 to location X115_Y73" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y61 to location X115_Y73"} { { 12 { 0 ""} 104 61 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678297631406 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678297631406 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678297631624 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678297631624 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678297631624 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678297631625 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678297631730 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678297631736 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678297631930 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678297631931 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678297632110 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678297632419 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678297632615 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678297632658 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 503 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 503 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1148 " "Peak virtual memory: 1148 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678297632833 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 17:47:12 2023 " "Processing ended: Wed Mar 8 17:47:12 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678297632833 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678297632833 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678297632833 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678297632833 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1678297633514 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678297633514 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 17:47:13 2023 " "Processing started: Wed Mar 8 17:47:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678297633514 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678297633514 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678297633514 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678297633741 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678297636465 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678297636601 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "364 " "Peak virtual memory: 364 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678297636921 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 17:47:16 2023 " "Processing ended: Wed Mar 8 17:47:16 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678297636921 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678297636921 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678297636921 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678297636921 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1678297637029 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1678297637677 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678297637677 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 17:47:17 2023 " "Processing started: Wed Mar 8 17:47:17 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678297637677 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678297637677 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DisplayDemo -c DisplayDemo " "Command: quartus_sta DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678297637677 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678297637721 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678297637820 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678297637820 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678297637895 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678297637895 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DisplayDemo.sdc " "Synopsys Design Constraints File file not found: 'DisplayDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678297638460 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678297638460 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678297638461 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678297638461 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678297638461 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678297638461 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678297638462 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678297638468 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678297638469 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638470 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638472 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638473 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638473 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638474 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638474 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678297638477 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678297638502 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678297638827 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678297638852 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678297638853 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678297638853 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678297638853 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638854 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638855 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638855 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638856 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638857 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638857 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678297638859 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678297638920 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678297638920 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678297638920 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678297638920 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638921 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638922 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638922 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638923 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297638923 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678297639284 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678297639284 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "536 " "Peak virtual memory: 536 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678297639300 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 17:47:19 2023 " "Processing ended: Wed Mar 8 17:47:19 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678297639300 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678297639300 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678297639300 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678297639300 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1678297640036 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678297640036 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 17:47:19 2023 " "Processing started: Wed Mar 8 17:47:19 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678297640036 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678297640036 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678297640036 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678297640270 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "DisplayDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/ simulation " "Generated file DisplayDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678297640306 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678297640327 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 17:47:20 2023 " "Processing ended: Wed Mar 8 17:47:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678297640327 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678297640327 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678297640327 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678297640327 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 514 s " "Quartus Prime Full Compilation was successful. 0 errors, 514 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678297640439 ""}
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/README b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.db_info b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.db_info
deleted file mode 100644
index e46e5ad..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Wed Mar 8 17:38:54 2023
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.ammdb
deleted file mode 100644
index ed16440..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.cdb
deleted file mode 100644
index dbc7092..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.dfp and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.hdb
deleted file mode 100644
index ffc6943..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.rcfdb
deleted file mode 100644
index f345bf1..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.cmp.rcfdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.cdb
deleted file mode 100644
index 066d06e..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.dpi
deleted file mode 100644
index 276fc67..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.dpi and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hbdb.cdb
deleted file mode 100644
index 406da40..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hbdb.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hbdb.hdb
deleted file mode 100644
index af73a2b..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hdb
deleted file mode 100644
index f145cae..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.kpt
deleted file mode 100644
index 17eb9cf..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.root_partition.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.rrp.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.rrp.hdb
deleted file mode 100644
index 491c311..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemo/incremental_db/compiled_partitions/DisplayDemo.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.asm.rpt b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.asm.rpt
deleted file mode 100644
index 2bdce23..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for DisplayDemo
-Thu Mar 9 10:12:40 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: DisplayDemo.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Thu Mar 9 10:12:40 2023 ;
-; Revision Name ; DisplayDemo ;
-; Top-level Entity Name ; DisplayDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+--------------------------------------------------------------------------------------------------------+
-; File Name ;
-+--------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.sof ;
-+--------------------------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------+
-; Assembler Device Options: DisplayDemo.sof ;
-+----------------+--------------------------+
-; Option ; Setting ;
-+----------------+--------------------------+
-; JTAG usercode ; 0x0056707A ;
-; Checksum ; 0x0056707A ;
-+----------------+--------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Thu Mar 9 10:12:37 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 365 megabytes
- Info: Processing ended: Thu Mar 9 10:12:40 2023
- Info: Elapsed time: 00:00:03
- Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.done b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.done
deleted file mode 100644
index 314eab2..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.done
+++ /dev/null
@@ -1 +0,0 @@
-Thu Mar 9 10:12:44 2023
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.eda.rpt b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.eda.rpt
deleted file mode 100644
index 879294f..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.eda.rpt
+++ /dev/null
@@ -1,94 +0,0 @@
-EDA Netlist Writer report for DisplayDemo
-Thu Mar 9 10:12:44 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Thu Mar 9 10:12:44 2023 ;
-; Revision Name ; DisplayDemo ;
-; Top-level Entity Name ; DisplayDemo ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+---------------------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+---------------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/DisplayDemo.vho ;
-+---------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Thu Mar 9 10:12:43 2023
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file DisplayDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 611 megabytes
- Info: Processing ended: Thu Mar 9 10:12:44 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.rpt b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.rpt
deleted file mode 100644
index f30e571..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.rpt
+++ /dev/null
@@ -1,2606 +0,0 @@
-Fitter report for DisplayDemo
-Thu Mar 9 10:12:37 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Thu Mar 9 10:12:37 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; DisplayDemo ;
-; Top-level Entity Name ; DisplayDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 14 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 14 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 23 / 529 ( 4 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.1% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; CLOCK_50 ; PIN_Y2 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[1] ; PIN_M21 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_H19 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; SW[10] ; PIN_AC24 ; QSF Assignment ;
-; Location ; ; ; SW[11] ; PIN_AB24 ; QSF Assignment ;
-; Location ; ; ; SW[12] ; PIN_AB23 ; QSF Assignment ;
-; Location ; ; ; SW[13] ; PIN_AA24 ; QSF Assignment ;
-; Location ; ; ; SW[14] ; PIN_AA23 ; QSF Assignment ;
-; Location ; ; ; SW[15] ; PIN_AA22 ; QSF Assignment ;
-; Location ; ; ; SW[16] ; PIN_Y24 ; QSF Assignment ;
-; Location ; ; ; SW[17] ; PIN_Y23 ; QSF Assignment ;
-; Location ; ; ; SW[4] ; PIN_AB27 ; QSF Assignment ;
-; Location ; ; ; SW[5] ; PIN_AC26 ; QSF Assignment ;
-; Location ; ; ; SW[6] ; PIN_AD26 ; QSF Assignment ;
-; Location ; ; ; SW[7] ; PIN_AB26 ; QSF Assignment ;
-; Location ; ; ; SW[8] ; PIN_AC25 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AB25 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 71 ) ; 0.00 % ( 0 / 71 ) ; 0.00 % ( 0 / 71 ) ;
-; -- Achieved ; 0.00 % ( 0 / 71 ) ; 0.00 % ( 0 / 71 ) ; 0.00 % ( 0 / 71 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 61 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.pin.
-
-
-+----------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+------------------------+
-; Total logic elements ; 14 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 14 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 7 ;
-; -- 3 input functions ; 2 ;
-; -- <=2 input functions ; 5 ;
-; -- Register only ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 14 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers* ; 0 / 117,053 ( 0 % ) ;
-; -- Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 1 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 23 / 529 ( 4 % ) ;
-; -- Clock pins ; 0 / 7 ( 0 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.5% / 0.4% / 0.7% ;
-; Maximum fan-out ; 9 ;
-; Highest non-global fan-out ; 9 ;
-; Total fan-out ; 90 ;
-; Average fan-out ; 1.29 ;
-+---------------------------------------------+------------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 14 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 14 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 7 ; 0 ;
-; -- 3 input functions ; 2 ; 0 ;
-; -- <=2 input functions ; 5 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 14 ; 0 ;
-; -- arithmetic mode ; 0 ; 0 ;
-; ; ; ;
-; Total registers ; 0 ; 0 ;
-; -- Dedicated logic registers ; 0 / 114480 ( 0 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 1 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 23 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 85 ; 5 ;
-; -- Registered Connections ; 0 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 5 ; 0 ;
-; -- Output Ports ; 18 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+-----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; KEY[0] ; M23 ; 6 ; 115 ; 40 ; 7 ; 7 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 9 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 8 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 9 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[3] ; AD27 ; 5 ; 115 ; 13 ; 7 ; 8 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; HEX0[0] ; G18 ; 7 ; 69 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[1] ; F22 ; 7 ; 107 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[2] ; E17 ; 7 ; 67 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[3] ; L26 ; 6 ; 115 ; 50 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[4] ; L25 ; 6 ; 115 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[5] ; J22 ; 6 ; 115 ; 67 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[6] ; H22 ; 6 ; 115 ; 69 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDG[0] ; E21 ; 7 ; 107 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDG[1] ; E22 ; 7 ; 111 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDG[2] ; E25 ; 7 ; 83 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDG[3] ; E24 ; 7 ; 85 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[2] ; E19 ; 7 ; 94 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[3] ; F21 ; 7 ; 107 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[4] ; F18 ; 7 ; 87 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[5] ; E18 ; 7 ; 87 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[6] ; J19 ; 7 ; 72 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 0 / 63 ( 0 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 4 / 65 ( 6 % ) ; 2.5V ; -- ;
-; 6 ; 6 / 58 ( 10 % ) ; 2.5V ; -- ;
-; 7 ; 14 / 72 ( 19 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA23 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA24 ; 279 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB24 ; 274 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB25 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB26 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB27 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC25 ; 272 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC26 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD27 ; 286 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E18 ; 427 ; 7 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E19 ; 421 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; LEDG[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E22 ; 403 ; 7 ; LEDG[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; LEDG[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E25 ; 434 ; 7 ; LEDG[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F22 ; 409 ; 7 ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; HEX0[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; HEX0[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; HEX0[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; HEX0[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; L26 ; 363 ; 6 ; HEX0[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y24 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; HEX0[6] ; Incomplete set of assignments ;
-; HEX0[5] ; Incomplete set of assignments ;
-; HEX0[4] ; Incomplete set of assignments ;
-; HEX0[3] ; Incomplete set of assignments ;
-; HEX0[2] ; Incomplete set of assignments ;
-; HEX0[1] ; Incomplete set of assignments ;
-; HEX0[0] ; Incomplete set of assignments ;
-; LEDG[3] ; Incomplete set of assignments ;
-; LEDG[2] ; Incomplete set of assignments ;
-; LEDG[1] ; Incomplete set of assignments ;
-; LEDG[0] ; Incomplete set of assignments ;
-; LEDR[6] ; Incomplete set of assignments ;
-; LEDR[5] ; Incomplete set of assignments ;
-; LEDR[4] ; Incomplete set of assignments ;
-; LEDR[3] ; Incomplete set of assignments ;
-; LEDR[2] ; Incomplete set of assignments ;
-; LEDR[1] ; Incomplete set of assignments ;
-; LEDR[0] ; Incomplete set of assignments ;
-; KEY[0] ; Incomplete set of assignments ;
-; SW[2] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-; SW[1] ; Incomplete set of assignments ;
-; SW[3] ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------+----------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------+----------------+--------------+
-; |DisplayDemo ; 14 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 ; 0 ; 14 (0) ; 0 (0) ; 0 (0) ; |DisplayDemo ; DisplayDemo ; work ;
-; |Bin7SegDecoder:inst| ; 14 (14) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; |DisplayDemo|Bin7SegDecoder:inst ; Bin7SegDecoder ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------+----------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-----------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDG[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDG[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDG[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDG[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; KEY[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+------------------------------------------+-------------------+---------+
-; KEY[0] ; ; ;
-; - Bin7SegDecoder:inst|decOut_n[6]~1 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~3 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~5 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n[3]~7 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~9 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~11 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~13 ; 1 ; 6 ;
-; SW[2] ; ; ;
-; - Bin7SegDecoder:inst|decOut_n[6]~0 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~2 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~4 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n[3]~6 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~8 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~9 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~10 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~12 ; 1 ; 6 ;
-; - LEDG[2]~output ; 1 ; 6 ;
-; SW[0] ; ; ;
-; - Bin7SegDecoder:inst|decOut_n[6]~0 ; 0 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~2 ; 0 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~3 ; 0 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~4 ; 0 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n[3]~6 ; 0 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~8 ; 0 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~10 ; 0 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~12 ; 0 ; 6 ;
-; - LEDG[0]~output ; 0 ; 6 ;
-; SW[1] ; ; ;
-; - Bin7SegDecoder:inst|decOut_n[6]~0 ; 0 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~2 ; 0 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~4 ; 0 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n[3]~6 ; 0 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~8 ; 0 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~10 ; 0 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~12 ; 0 ; 6 ;
-; - LEDG[1]~output ; 0 ; 6 ;
-; SW[3] ; ; ;
-; - Bin7SegDecoder:inst|decOut_n[6]~0 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~3 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~4 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n[3]~6 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~9 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~10 ; 1 ; 6 ;
-; - Bin7SegDecoder:inst|decOut_n~12 ; 1 ; 6 ;
-; - LEDG[3]~output ; 1 ; 6 ;
-+------------------------------------------+-------------------+---------+
-
-
-+------------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+------------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+------------------------+
-; Block interconnects ; 22 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 21 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 24 / 209,544 ( < 1 % ) ;
-; Direct links ; 0 / 342,891 ( 0 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 7 / 119,088 ( < 1 % ) ;
-; R24 interconnects ; 13 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 41 / 289,782 ( < 1 % ) ;
-+-----------------------+------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+---------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 14.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 1 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-+---------------------------------------------+-----------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+----------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 14.00) ; Number of LABs (Total = 1) ;
-+----------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 1 ;
-+----------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 7.00) ; Number of LABs (Total = 1) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 1 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 5.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 23 ; 23 ; 0 ; 0 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; 0 ; 0 ; 5 ; 18 ; 0 ; 5 ; 0 ; 0 ; 18 ; 0 ; 23 ; 23 ; 23 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 23 ; 0 ; 0 ; 23 ; 23 ; 0 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 23 ; 5 ; 23 ; 23 ; 23 ; 18 ; 5 ; 23 ; 18 ; 23 ; 23 ; 5 ; 23 ; 0 ; 0 ; 0 ; 23 ; 23 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; HEX0[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDG[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDG[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDG[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDG[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "DisplayDemo"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'DisplayDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y61 to location X115_Y73
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 503 warnings
- Info: Peak virtual memory: 1149 megabytes
- Info: Processing ended: Thu Mar 9 10:12:37 2023
- Info: Elapsed time: 00:00:08
- Info: Total CPU time (on all processors): 00:00:12
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.smsg b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.summary b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.summary
deleted file mode 100644
index d39e8f9..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Thu Mar 9 10:12:37 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : DisplayDemo
-Top-level Entity Name : DisplayDemo
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 14 / 114,480 ( < 1 % )
- Total combinational functions : 14 / 114,480 ( < 1 % )
- Dedicated logic registers : 0 / 114,480 ( 0 % )
-Total registers : 0
-Total pins : 23 / 529 ( 4 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.flow.rpt b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.flow.rpt
deleted file mode 100644
index fb5fb24..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.flow.rpt
+++ /dev/null
@@ -1,136 +0,0 @@
-Flow report for DisplayDemo
-Thu Mar 9 10:12:44 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Thu Mar 9 10:12:44 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; DisplayDemo ;
-; Top-level Entity Name ; DisplayDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 14 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 14 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 23 / 529 ( 4 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/09/2023 10:12:21 ;
-; Main task ; Compilation ;
-; Revision Name ; DisplayDemo ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 198516037997543.167835674105522 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 434 MB ; 00:00:16 ;
-; Fitter ; 00:00:08 ; 1.0 ; 1149 MB ; 00:00:12 ;
-; Assembler ; 00:00:03 ; 1.0 ; 365 MB ; 00:00:03 ;
-; Timing Analyzer ; 00:00:01 ; 1.0 ; 536 MB ; 00:00:01 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 611 MB ; 00:00:00 ;
-; Total ; 00:00:19 ; -- ; -- ; 00:00:32 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off DisplayDemo -c DisplayDemo
-quartus_fit --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo
-quartus_asm --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo
-quartus_sta DisplayDemo -c DisplayDemo
-quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.jdi b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.jdi
deleted file mode 100644
index fc39762..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.map.rpt b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.map.rpt
deleted file mode 100644
index 3ec002b..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.map.rpt
+++ /dev/null
@@ -1,299 +0,0 @@
-Analysis & Synthesis report for DisplayDemo
-Thu Mar 9 10:12:28 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Multiplexer Restructuring Statistics (Restructuring Performed)
- 10. Post-Synthesis Netlist Statistics for Top Partition
- 11. Elapsed Time Per Partition
- 12. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Thu Mar 9 10:12:28 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; DisplayDemo ;
-; Top-level Entity Name ; DisplayDemo ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 14 ;
-; Total combinational functions ; 14 ;
-; Dedicated logic registers ; 0 ;
-; Total registers ; 0 ;
-; Total pins ; 23 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; DisplayDemo ; DisplayDemo ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------+---------+
-; Bin7SegDecoder.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.vhd ; ;
-; DisplayDemo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.bdf ; ;
-+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------+---------+
-
-
-+-----------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+-------------+
-; Resource ; Usage ;
-+---------------------------------------------+-------------+
-; Estimated Total logic elements ; 14 ;
-; ; ;
-; Total combinational functions ; 14 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 7 ;
-; -- 3 input functions ; 2 ;
-; -- <=2 input functions ; 5 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 14 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers ; 0 ;
-; -- Dedicated logic registers ; 0 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 23 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; SW[2]~input ;
-; Maximum fan-out ; 9 ;
-; Total fan-out ; 85 ;
-; Average fan-out ; 1.42 ;
-+---------------------------------------------+-------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------+----------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------+----------------+--------------+
-; |DisplayDemo ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 23 ; 0 ; |DisplayDemo ; DisplayDemo ; work ;
-; |Bin7SegDecoder:inst| ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DisplayDemo|Bin7SegDecoder:inst ; Bin7SegDecoder ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------+----------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 0 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
-; 17:1 ; 2 bits ; 22 LEs ; 16 LEs ; 6 LEs ; No ; |DisplayDemo|Bin7SegDecoder:inst|decOut_n[6] ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 23 ;
-; cycloneiii_lcell_comb ; 14 ;
-; normal ; 14 ;
-; 2 data inputs ; 5 ;
-; 3 data inputs ; 2 ;
-; 4 data inputs ; 7 ;
-; ; ;
-; Max LUT depth ; 2.00 ;
-; Average LUT depth ; 1.95 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Thu Mar 9 10:12:21 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DisplayDemo -c DisplayDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 2 design units, including 1 entities, in source file Bin7SegDecoder.vhd
- Info (12022): Found design unit 1: Bin7SegDecoder-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.vhd Line: 13
- Info (12023): Found entity 1: Bin7SegDecoder File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.vhd Line: 4
-Info (12021): Found 1 design units, including 1 entities, in source file DisplayDemo.bdf
- Info (12023): Found entity 1: DisplayDemo
-Info (12127): Elaborating entity "DisplayDemo" for the top level hierarchy
-Info (12128): Elaborating entity "Bin7SegDecoder" for hierarchy "Bin7SegDecoder:inst"
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 37 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 5 input pins
- Info (21059): Implemented 18 output pins
- Info (21061): Implemented 14 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 434 megabytes
- Info: Processing ended: Thu Mar 9 10:12:28 2023
- Info: Elapsed time: 00:00:07
- Info: Total CPU time (on all processors): 00:00:17
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.map.summary b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.map.summary
deleted file mode 100644
index bce5607..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Thu Mar 9 10:12:28 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : DisplayDemo
-Top-level Entity Name : DisplayDemo
-Family : Cyclone IV E
-Total logic elements : 14
- Total combinational functions : 14
- Dedicated logic registers : 0
-Total registers : 0
-Total pins : 23
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.pin b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.pin
deleted file mode 100644
index 089d022..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "DisplayDemo" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5 :
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC26 : : : : 5 :
-SW[2] : AC27 : input : 2.5 V : : 5 : Y
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5 :
-SW[3] : AD27 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-HEX0[2] : E17 : output : 2.5 V : : 7 : Y
-LEDR[5] : E18 : output : 2.5 V : : 7 : Y
-LEDR[2] : E19 : output : 2.5 V : : 7 : Y
-VCCIO7 : E20 : power : : 2.5V : 7 :
-LEDG[0] : E21 : output : 2.5 V : : 7 : Y
-LEDG[1] : E22 : output : 2.5 V : : 7 : Y
-VCCIO7 : E23 : power : : 2.5V : 7 :
-LEDG[3] : E24 : output : 2.5 V : : 7 : Y
-LEDG[2] : E25 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-LEDR[4] : F18 : output : 2.5 V : : 7 : Y
-LEDR[1] : F19 : output : 2.5 V : : 7 : Y
-GND : F20 : gnd : : : :
-LEDR[3] : F21 : output : 2.5 V : : 7 : Y
-HEX0[1] : F22 : output : 2.5 V : : 7 : Y
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-HEX0[0] : G18 : output : 2.5 V : : 7 : Y
-LEDR[0] : G19 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
-VCCIO7 : H18 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-HEX0[6] : H22 : output : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
-GND : J18 : gnd : : : :
-LEDR[6] : J19 : output : 2.5 V : : 7 : Y
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-HEX0[5] : J22 : output : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-HEX0[4] : L25 : output : 2.5 V : : 6 : Y
-HEX0[3] : L26 : output : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6 :
-MSEL2 : M22 : : : : 6 :
-KEY[0] : M23 : input : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-GND+ : Y2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.sld b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.sta.rpt b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.sta.rpt
deleted file mode 100644
index ee5d2cf..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.sta.rpt
+++ /dev/null
@@ -1,542 +0,0 @@
-Timing Analyzer report for DisplayDemo
-Thu Mar 9 10:12:42 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Unconstrained Input Ports
- 37. Unconstrained Output Ports
- 38. Unconstrained Input Ports
- 39. Unconstrained Output Ports
- 40. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; DisplayDemo ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.2% ;
-+----------------------------+-------------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDG[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDG[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDG[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ;
-; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ;
-; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ;
-; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ;
-; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ;
-; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ;
-; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ;
-; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ;
-; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ;
-; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ;
-; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ;
-; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ;
-; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 5 ; 5 ;
-; Unconstrained Input Port Paths ; 74 ; 74 ;
-; Unconstrained Output Ports ; 18 ; 18 ;
-; Unconstrained Output Port Paths ; 74 ; 74 ;
-+---------------------------------+-------+------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Thu Mar 9 10:12:41 2023
-Info: Command: quartus_sta DisplayDemo -c DisplayDemo
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'DisplayDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 536 megabytes
- Info: Processing ended: Thu Mar 9 10:12:42 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.sta.summary b/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.sta.summary
deleted file mode 100644
index aa5b327..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/DisplayDemo.sft b/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/DisplayDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/DisplayDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/DisplayDemo.vho b/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/DisplayDemo.vho
deleted file mode 100644
index eaaeebb..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/DisplayDemo.vho
+++ /dev/null
@@ -1,724 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/09/2023 10:12:44"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY DisplayDemo IS
- PORT (
- HEX0 : OUT std_logic_vector(6 DOWNTO 0);
- KEY : IN std_logic_vector(0 DOWNTO 0);
- SW : IN std_logic_vector(3 DOWNTO 0);
- LEDG : OUT std_logic_vector(3 DOWNTO 0);
- LEDR : OUT std_logic_vector(6 DOWNTO 0)
- );
-END DisplayDemo;
-
--- Design Ports Information
--- HEX0[6] => Location: PIN_H22, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[5] => Location: PIN_J22, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[4] => Location: PIN_L25, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[3] => Location: PIN_L26, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[2] => Location: PIN_E17, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[1] => Location: PIN_F22, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[0] => Location: PIN_G18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDG[3] => Location: PIN_E24, I/O Standard: 2.5 V, Current Strength: Default
--- LEDG[2] => Location: PIN_E25, I/O Standard: 2.5 V, Current Strength: Default
--- LEDG[1] => Location: PIN_E22, I/O Standard: 2.5 V, Current Strength: Default
--- LEDG[0] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[6] => Location: PIN_J19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[5] => Location: PIN_E18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[4] => Location: PIN_F18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF DisplayDemo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_HEX0 : std_logic_vector(6 DOWNTO 0);
-SIGNAL ww_KEY : std_logic_vector(0 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(3 DOWNTO 0);
-SIGNAL ww_LEDG : std_logic_vector(3 DOWNTO 0);
-SIGNAL ww_LEDR : std_logic_vector(6 DOWNTO 0);
-SIGNAL \HEX0[6]~output_o\ : std_logic;
-SIGNAL \HEX0[5]~output_o\ : std_logic;
-SIGNAL \HEX0[4]~output_o\ : std_logic;
-SIGNAL \HEX0[3]~output_o\ : std_logic;
-SIGNAL \HEX0[2]~output_o\ : std_logic;
-SIGNAL \HEX0[1]~output_o\ : std_logic;
-SIGNAL \HEX0[0]~output_o\ : std_logic;
-SIGNAL \LEDG[3]~output_o\ : std_logic;
-SIGNAL \LEDG[2]~output_o\ : std_logic;
-SIGNAL \LEDG[1]~output_o\ : std_logic;
-SIGNAL \LEDG[0]~output_o\ : std_logic;
-SIGNAL \LEDR[6]~output_o\ : std_logic;
-SIGNAL \LEDR[5]~output_o\ : std_logic;
-SIGNAL \LEDR[4]~output_o\ : std_logic;
-SIGNAL \LEDR[3]~output_o\ : std_logic;
-SIGNAL \LEDR[2]~output_o\ : std_logic;
-SIGNAL \LEDR[1]~output_o\ : std_logic;
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \KEY[0]~input_o\ : std_logic;
-SIGNAL \SW[3]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[2]~input_o\ : std_logic;
-SIGNAL \inst|decOut_n[6]~0_combout\ : std_logic;
-SIGNAL \inst|decOut_n[6]~1_combout\ : std_logic;
-SIGNAL \inst|decOut_n~2_combout\ : std_logic;
-SIGNAL \inst|decOut_n~3_combout\ : std_logic;
-SIGNAL \inst|decOut_n~4_combout\ : std_logic;
-SIGNAL \inst|decOut_n~5_combout\ : std_logic;
-SIGNAL \inst|decOut_n[3]~6_combout\ : std_logic;
-SIGNAL \inst|decOut_n[3]~7_combout\ : std_logic;
-SIGNAL \inst|decOut_n~8_combout\ : std_logic;
-SIGNAL \inst|decOut_n~9_combout\ : std_logic;
-SIGNAL \inst|decOut_n~10_combout\ : std_logic;
-SIGNAL \inst|decOut_n~11_combout\ : std_logic;
-SIGNAL \inst|decOut_n~12_combout\ : std_logic;
-SIGNAL \inst|decOut_n~13_combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-HEX0 <= ww_HEX0;
-ww_KEY <= KEY;
-ww_SW <= SW;
-LEDG <= ww_LEDG;
-LEDR <= ww_LEDR;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X115_Y69_N2
-\HEX0[6]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n[6]~1_combout\,
- devoe => ww_devoe,
- o => \HEX0[6]~output_o\);
-
--- Location: IOOBUF_X115_Y67_N16
-\HEX0[5]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n~3_combout\,
- devoe => ww_devoe,
- o => \HEX0[5]~output_o\);
-
--- Location: IOOBUF_X115_Y54_N16
-\HEX0[4]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n~5_combout\,
- devoe => ww_devoe,
- o => \HEX0[4]~output_o\);
-
--- Location: IOOBUF_X115_Y50_N2
-\HEX0[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n[3]~7_combout\,
- devoe => ww_devoe,
- o => \HEX0[3]~output_o\);
-
--- Location: IOOBUF_X67_Y73_N23
-\HEX0[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n~9_combout\,
- devoe => ww_devoe,
- o => \HEX0[2]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N23
-\HEX0[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n~11_combout\,
- devoe => ww_devoe,
- o => \HEX0[1]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N23
-\HEX0[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n~13_combout\,
- devoe => ww_devoe,
- o => \HEX0[0]~output_o\);
-
--- Location: IOOBUF_X85_Y73_N23
-\LEDG[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \SW[3]~input_o\,
- devoe => ww_devoe,
- o => \LEDG[3]~output_o\);
-
--- Location: IOOBUF_X83_Y73_N2
-\LEDG[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \SW[2]~input_o\,
- devoe => ww_devoe,
- o => \LEDG[2]~output_o\);
-
--- Location: IOOBUF_X111_Y73_N9
-\LEDG[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \SW[1]~input_o\,
- devoe => ww_devoe,
- o => \LEDG[1]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N9
-\LEDG[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \SW[0]~input_o\,
- devoe => ww_devoe,
- o => \LEDG[0]~output_o\);
-
--- Location: IOOBUF_X72_Y73_N9
-\LEDR[6]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n[6]~1_combout\,
- devoe => ww_devoe,
- o => \LEDR[6]~output_o\);
-
--- Location: IOOBUF_X87_Y73_N9
-\LEDR[5]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n~3_combout\,
- devoe => ww_devoe,
- o => \LEDR[5]~output_o\);
-
--- Location: IOOBUF_X87_Y73_N16
-\LEDR[4]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n~5_combout\,
- devoe => ww_devoe,
- o => \LEDR[4]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N16
-\LEDR[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n[3]~7_combout\,
- devoe => ww_devoe,
- o => \LEDR[3]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N9
-\LEDR[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n~9_combout\,
- devoe => ww_devoe,
- o => \LEDR[2]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N2
-\LEDR[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n~11_combout\,
- devoe => ww_devoe,
- o => \LEDR[1]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N16
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|decOut_n~13_combout\,
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
--- Location: IOIBUF_X115_Y40_N8
-\KEY[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY(0),
- o => \KEY[0]~input_o\);
-
--- Location: IOIBUF_X115_Y13_N8
-\SW[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(3),
- o => \SW[3]~input_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N8
-\SW[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(2),
- o => \SW[2]~input_o\);
-
--- Location: LCCOMB_X107_Y72_N24
-\inst|decOut_n[6]~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n[6]~0_combout\ = (\SW[0]~input_o\ & (!\SW[3]~input_o\ & (\SW[1]~input_o\ $ (!\SW[2]~input_o\)))) # (!\SW[0]~input_o\ & (!\SW[1]~input_o\ & (\SW[3]~input_o\ $ (!\SW[2]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0100001000000101",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \inst|decOut_n[6]~0_combout\);
-
--- Location: LCCOMB_X107_Y72_N10
-\inst|decOut_n[6]~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n[6]~1_combout\ = (\KEY[0]~input_o\) # (\inst|decOut_n[6]~0_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \KEY[0]~input_o\,
- datad => \inst|decOut_n[6]~0_combout\,
- combout => \inst|decOut_n[6]~1_combout\);
-
--- Location: LCCOMB_X107_Y72_N28
-\inst|decOut_n~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n~2_combout\ = (\SW[2]~input_o\ & (\SW[0]~input_o\ & !\SW[1]~input_o\)) # (!\SW[2]~input_o\ & (!\SW[0]~input_o\ & \SW[1]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0001100000011000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[2]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- combout => \inst|decOut_n~2_combout\);
-
--- Location: LCCOMB_X107_Y72_N22
-\inst|decOut_n~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n~3_combout\ = (\KEY[0]~input_o\) # ((\SW[3]~input_o\ & (\SW[0]~input_o\ & \inst|decOut_n~2_combout\)) # (!\SW[3]~input_o\ & (\SW[0]~input_o\ $ (\inst|decOut_n~2_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111100111110100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \KEY[0]~input_o\,
- datad => \inst|decOut_n~2_combout\,
- combout => \inst|decOut_n~3_combout\);
-
--- Location: LCCOMB_X107_Y72_N0
-\inst|decOut_n~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n~4_combout\ = (\SW[1]~input_o\ & (!\SW[3]~input_o\ & (\SW[0]~input_o\))) # (!\SW[1]~input_o\ & ((\SW[2]~input_o\ & (!\SW[3]~input_o\)) # (!\SW[2]~input_o\ & ((\SW[0]~input_o\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0100010101001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \inst|decOut_n~4_combout\);
-
--- Location: LCCOMB_X107_Y72_N18
-\inst|decOut_n~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n~5_combout\ = (\KEY[0]~input_o\) # (\inst|decOut_n~4_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \KEY[0]~input_o\,
- datad => \inst|decOut_n~4_combout\,
- combout => \inst|decOut_n~5_combout\);
-
--- Location: LCCOMB_X107_Y72_N12
-\inst|decOut_n[3]~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n[3]~6_combout\ = (\SW[1]~input_o\ & ((\SW[0]~input_o\ & ((\SW[2]~input_o\))) # (!\SW[0]~input_o\ & (\SW[3]~input_o\ & !\SW[2]~input_o\)))) # (!\SW[1]~input_o\ & (!\SW[3]~input_o\ & (\SW[0]~input_o\ $ (\SW[2]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100000100100100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \inst|decOut_n[3]~6_combout\);
-
--- Location: LCCOMB_X107_Y72_N6
-\inst|decOut_n[3]~7\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n[3]~7_combout\ = (\KEY[0]~input_o\) # (\inst|decOut_n[3]~6_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \KEY[0]~input_o\,
- datad => \inst|decOut_n[3]~6_combout\,
- combout => \inst|decOut_n[3]~7_combout\);
-
--- Location: LCCOMB_X107_Y72_N8
-\inst|decOut_n~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n~8_combout\ = (\SW[2]~input_o\ & (\SW[0]~input_o\ & !\SW[1]~input_o\)) # (!\SW[2]~input_o\ & (!\SW[0]~input_o\ & \SW[1]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0001100000011000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[2]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- combout => \inst|decOut_n~8_combout\);
-
--- Location: LCCOMB_X107_Y72_N2
-\inst|decOut_n~9\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n~9_combout\ = (\KEY[0]~input_o\) # ((\SW[3]~input_o\ & (!\inst|decOut_n~8_combout\ & \SW[2]~input_o\)) # (!\SW[3]~input_o\ & (\inst|decOut_n~8_combout\ & !\SW[2]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111001011110100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \inst|decOut_n~8_combout\,
- datac => \KEY[0]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \inst|decOut_n~9_combout\);
-
--- Location: LCCOMB_X107_Y72_N20
-\inst|decOut_n~10\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n~10_combout\ = (\SW[3]~input_o\ & ((\SW[0]~input_o\ & (\SW[1]~input_o\)) # (!\SW[0]~input_o\ & ((\SW[2]~input_o\))))) # (!\SW[3]~input_o\ & (\SW[2]~input_o\ & (\SW[0]~input_o\ $ (\SW[1]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1011011010000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \inst|decOut_n~10_combout\);
-
--- Location: LCCOMB_X107_Y72_N30
-\inst|decOut_n~11\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n~11_combout\ = (\KEY[0]~input_o\) # (\inst|decOut_n~10_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \KEY[0]~input_o\,
- datad => \inst|decOut_n~10_combout\,
- combout => \inst|decOut_n~11_combout\);
-
--- Location: LCCOMB_X107_Y72_N16
-\inst|decOut_n~12\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n~12_combout\ = (\SW[3]~input_o\ & (\SW[0]~input_o\ & (\SW[1]~input_o\ $ (\SW[2]~input_o\)))) # (!\SW[3]~input_o\ & (!\SW[1]~input_o\ & (\SW[0]~input_o\ $ (\SW[2]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000100110000100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \inst|decOut_n~12_combout\);
-
--- Location: LCCOMB_X107_Y72_N26
-\inst|decOut_n~13\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|decOut_n~13_combout\ = (\KEY[0]~input_o\) # (\inst|decOut_n~12_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \KEY[0]~input_o\,
- datad => \inst|decOut_n~12_combout\,
- combout => \inst|decOut_n~13_combout\);
-
-ww_HEX0(6) <= \HEX0[6]~output_o\;
-
-ww_HEX0(5) <= \HEX0[5]~output_o\;
-
-ww_HEX0(4) <= \HEX0[4]~output_o\;
-
-ww_HEX0(3) <= \HEX0[3]~output_o\;
-
-ww_HEX0(2) <= \HEX0[2]~output_o\;
-
-ww_HEX0(1) <= \HEX0[1]~output_o\;
-
-ww_HEX0(0) <= \HEX0[0]~output_o\;
-
-ww_LEDG(3) <= \LEDG[3]~output_o\;
-
-ww_LEDG(2) <= \LEDG[2]~output_o\;
-
-ww_LEDG(1) <= \LEDG[1]~output_o\;
-
-ww_LEDG(0) <= \LEDG[0]~output_o\;
-
-ww_LEDR(6) <= \LEDR[6]~output_o\;
-
-ww_LEDR(5) <= \LEDR[5]~output_o\;
-
-ww_LEDR(4) <= \LEDR[4]~output_o\;
-
-ww_LEDR(3) <= \LEDR[3]~output_o\;
-
-ww_LEDR(2) <= \LEDR[2]~output_o\;
-
-ww_LEDR(1) <= \LEDR[1]~output_o\;
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/DisplayDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/DisplayDemo_modelsim.xrf
deleted file mode 100644
index 4f2d639..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/DisplayDemo_modelsim.xrf
+++ /dev/null
@@ -1,47 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.bdf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cbx.xml
-design_name = hard_block
-design_name = DisplayDemo
-instance = comp, \HEX0[6]~output\, HEX0[6]~output, DisplayDemo, 1
-instance = comp, \HEX0[5]~output\, HEX0[5]~output, DisplayDemo, 1
-instance = comp, \HEX0[4]~output\, HEX0[4]~output, DisplayDemo, 1
-instance = comp, \HEX0[3]~output\, HEX0[3]~output, DisplayDemo, 1
-instance = comp, \HEX0[2]~output\, HEX0[2]~output, DisplayDemo, 1
-instance = comp, \HEX0[1]~output\, HEX0[1]~output, DisplayDemo, 1
-instance = comp, \HEX0[0]~output\, HEX0[0]~output, DisplayDemo, 1
-instance = comp, \LEDG[3]~output\, LEDG[3]~output, DisplayDemo, 1
-instance = comp, \LEDG[2]~output\, LEDG[2]~output, DisplayDemo, 1
-instance = comp, \LEDG[1]~output\, LEDG[1]~output, DisplayDemo, 1
-instance = comp, \LEDG[0]~output\, LEDG[0]~output, DisplayDemo, 1
-instance = comp, \LEDR[6]~output\, LEDR[6]~output, DisplayDemo, 1
-instance = comp, \LEDR[5]~output\, LEDR[5]~output, DisplayDemo, 1
-instance = comp, \LEDR[4]~output\, LEDR[4]~output, DisplayDemo, 1
-instance = comp, \LEDR[3]~output\, LEDR[3]~output, DisplayDemo, 1
-instance = comp, \LEDR[2]~output\, LEDR[2]~output, DisplayDemo, 1
-instance = comp, \LEDR[1]~output\, LEDR[1]~output, DisplayDemo, 1
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, DisplayDemo, 1
-instance = comp, \KEY[0]~input\, KEY[0]~input, DisplayDemo, 1
-instance = comp, \SW[3]~input\, SW[3]~input, DisplayDemo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, DisplayDemo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, DisplayDemo, 1
-instance = comp, \SW[2]~input\, SW[2]~input, DisplayDemo, 1
-instance = comp, \inst|decOut_n[6]~0\, inst|decOut_n[6]~0, DisplayDemo, 1
-instance = comp, \inst|decOut_n[6]~1\, inst|decOut_n[6]~1, DisplayDemo, 1
-instance = comp, \inst|decOut_n~2\, inst|decOut_n~2, DisplayDemo, 1
-instance = comp, \inst|decOut_n~3\, inst|decOut_n~3, DisplayDemo, 1
-instance = comp, \inst|decOut_n~4\, inst|decOut_n~4, DisplayDemo, 1
-instance = comp, \inst|decOut_n~5\, inst|decOut_n~5, DisplayDemo, 1
-instance = comp, \inst|decOut_n[3]~6\, inst|decOut_n[3]~6, DisplayDemo, 1
-instance = comp, \inst|decOut_n[3]~7\, inst|decOut_n[3]~7, DisplayDemo, 1
-instance = comp, \inst|decOut_n~8\, inst|decOut_n~8, DisplayDemo, 1
-instance = comp, \inst|decOut_n~9\, inst|decOut_n~9, DisplayDemo, 1
-instance = comp, \inst|decOut_n~10\, inst|decOut_n~10, DisplayDemo, 1
-instance = comp, \inst|decOut_n~11\, inst|decOut_n~11, DisplayDemo, 1
-instance = comp, \inst|decOut_n~12\, inst|decOut_n~12, DisplayDemo, 1
-instance = comp, \inst|decOut_n~13\, inst|decOut_n~13, DisplayDemo, 1
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.qpf b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.qpf
deleted file mode 100644
index a065fcc..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 20:48:57 March 08, 2023
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "20.1"
-DATE = "20:48:57 March 08, 2023"
-
-# Revisions
-
-PROJECT_REVISION = "DisplayDemoVHDL"
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.qsf b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.qsf
deleted file mode 100644
index 63d4124..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.qsf
+++ /dev/null
@@ -1,584 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 20:48:57 March 08, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# DisplayDemoVHDL_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY DisplayDemoVHDL
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:48:57 MARCH 08, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VHDL_FILE Bin7SegDecoder.vhd
-set_global_assignment -name VHDL_FILE DisplayDemoVHDL.vhd
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.qsf.bak b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.qsf.bak
deleted file mode 100644
index d98c221..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.qsf.bak
+++ /dev/null
@@ -1,65 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 20:48:57 March 08, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# DisplayDemoVHDL_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY Bin7SegDecoder
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:48:57 MARCH 08, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VHDL_FILE Bin7SegDecoder.vhd
-set_global_assignment -name VHDL_FILE DisplayDemoVHDL.vhd
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.qws b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.qws
deleted file mode 100644
index f81850b..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.(0).cnf.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.(0).cnf.cdb
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index 2fec249..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.(0).cnf.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.(0).cnf.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.(1).cnf.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.(1).cnf.cdb
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index 7d0e107..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.(1).cnf.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.(1).cnf.hdb
deleted file mode 100644
index 1c387e3..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.(2).cnf.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.(2).cnf.cdb
deleted file mode 100644
index e5feb19..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.(2).cnf.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.(2).cnf.hdb
deleted file mode 100644
index f1671ae..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.asm.qmsg b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.asm.qmsg
deleted file mode 100644
index aa11afb..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.asm.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678308862733 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678308862733 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 20:54:22 2023 " "Processing started: Wed Mar 8 20:54:22 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678308862733 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678308862733 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL " "Command: quartus_asm --read_settings_files=off --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678308862733 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678308862860 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678308864330 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678308864395 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "365 " "Peak virtual memory: 365 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678308864576 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 20:54:24 2023 " "Processing ended: Wed Mar 8 20:54:24 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678308864576 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678308864576 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678308864576 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678308864576 ""}
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.asm.rdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.asm.rdb
deleted file mode 100644
index 26b74c9..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.asm_labs.ddb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.asm_labs.ddb
deleted file mode 100644
index df5a102..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.asm_labs.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cbx.xml b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cbx.xml
deleted file mode 100644
index 7206baf..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.bpm b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.bpm
deleted file mode 100644
index 54c3e4e..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.cdb
deleted file mode 100644
index 368ab08..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.hdb
deleted file mode 100644
index 3590792..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.idb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.idb
deleted file mode 100644
index da2015e..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.idb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.logdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.logdb
deleted file mode 100644
index 2fddd50..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.logdb
+++ /dev/null
@@ -1,66 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;24;24;0;0;24;24;0;0;0;0;0;0;18;0;0;0;6;18;0;6;0;0;18;0;24;24;24;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,24;0;0;24;24;0;0;24;24;24;24;24;24;6;24;24;24;18;6;24;18;24;24;6;24;0;0;0;24;24,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,KEY[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDG[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDG[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDG[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDG[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.rdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp.rdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp_merge.kpt b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cmp_merge.kpt
deleted file mode 100644
index 33b5e42..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index 12d57d7..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
deleted file mode 100644
index 218eca7..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
deleted file mode 100644
index bea9e20..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.db_info b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.db_info
deleted file mode 100644
index afd05cf..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Thu Mar 9 10:15:06 2023
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.eda.qmsg b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.eda.qmsg
deleted file mode 100644
index dda8c01..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678308866431 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678308866431 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 20:54:26 2023 " "Processing started: Wed Mar 8 20:54:26 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678308866431 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678308866431 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL " "Command: quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678308866431 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678308866588 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "DisplayDemoVHDL.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/ simulation " "Generated file DisplayDemoVHDL.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678308866613 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "613 " "Peak virtual memory: 613 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678308866624 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 20:54:26 2023 " "Processing ended: Wed Mar 8 20:54:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678308866624 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678308866624 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678308866624 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678308866624 ""}
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.fit.qmsg b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.fit.qmsg
deleted file mode 100644
index 0cfa299..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.fit.qmsg
+++ /dev/null
@@ -1,48 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678308856295 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678308856295 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "DisplayDemoVHDL EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"DisplayDemoVHDL\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678308856297 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678308856343 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678308856343 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678308856566 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678308856570 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678308856593 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678308856593 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678308856593 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678308856593 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678308856593 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678308856593 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678308856593 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678308856593 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678308856593 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678308856593 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/" { { 0 { 0 ""} 0 608 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678308856594 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/" { { 0 { 0 ""} 0 610 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678308856594 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/" { { 0 { 0 ""} 0 612 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678308856594 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/" { { 0 { 0 ""} 0 614 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678308856594 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/" { { 0 { 0 ""} 0 616 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678308856594 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678308856594 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678308856595 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DisplayDemoVHDL.sdc " "Synopsys Design Constraints File file not found: 'DisplayDemoVHDL.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678308857092 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678308857092 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678308857092 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678308857092 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678308857093 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678308857093 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678308857093 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678308857095 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678308857095 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678308857095 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678308857095 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678308857095 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678308857095 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678308857095 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678308857095 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678308857095 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678308857096 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678308857096 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678308857113 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678308857113 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678308857121 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678308857124 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678308858704 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678308858770 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678308858795 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678308858946 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678308858946 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678308859108 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y61 X115_Y73 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y61 to location X115_Y73" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y61 to location X115_Y73"} { { 12 { 0 ""} 104 61 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678308861165 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678308861165 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678308861271 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678308861271 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678308861271 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678308861272 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678308861343 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678308861348 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678308861502 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678308861502 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678308861648 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678308861881 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678308862054 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678308862087 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 502 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 502 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1153 " "Peak virtual memory: 1153 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678308862208 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 20:54:22 2023 " "Processing ended: Wed Mar 8 20:54:22 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678308862208 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678308862208 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678308862208 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678308862208 ""}
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.hier_info b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.hier_info
deleted file mode 100644
index eb1de82..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.hier_info
+++ /dev/null
@@ -1,108 +0,0 @@
-|DisplayDemoVHDL
-SW[0] => bin7segdecoder:system_core.binInput[0]
-SW[0] => LEDG[0].DATAIN
-SW[1] => bin7segdecoder:system_core.binInput[1]
-SW[1] => LEDG[1].DATAIN
-SW[2] => bin7segdecoder:system_core.binInput[2]
-SW[2] => LEDG[2].DATAIN
-SW[3] => bin7segdecoder:system_core.binInput[3]
-SW[3] => LEDG[3].DATAIN
-KEY[0] => bin7segdecoder:system_core.enable
-KEY[1] => ~NO_FANOUT~
-LEDG[0] <= SW[0].DB_MAX_OUTPUT_PORT_TYPE
-LEDG[1] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE
-LEDG[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE
-LEDG[3] <= SW[3].DB_MAX_OUTPUT_PORT_TYPE
-LEDR[0] <= bin7segdecoder:system_core.decOut_n[0]
-LEDR[1] <= bin7segdecoder:system_core.decOut_n[1]
-LEDR[2] <= bin7segdecoder:system_core.decOut_n[2]
-LEDR[3] <= bin7segdecoder:system_core.decOut_n[3]
-LEDR[4] <= bin7segdecoder:system_core.decOut_n[4]
-LEDR[5] <= bin7segdecoder:system_core.decOut_n[5]
-LEDR[6] <= bin7segdecoder:system_core.decOut_n[6]
-HEX0[0] <= bin7segdecoder:system_core.decOut_n[0]
-HEX0[1] <= bin7segdecoder:system_core.decOut_n[1]
-HEX0[2] <= bin7segdecoder:system_core.decOut_n[2]
-HEX0[3] <= bin7segdecoder:system_core.decOut_n[3]
-HEX0[4] <= bin7segdecoder:system_core.decOut_n[4]
-HEX0[5] <= bin7segdecoder:system_core.decOut_n[5]
-HEX0[6] <= bin7segdecoder:system_core.decOut_n[6]
-
-
-|DisplayDemoVHDL|Bin7SegDecoder:system_core
-binInput[0] => Equal0.IN3
-binInput[0] => Equal1.IN0
-binInput[0] => Equal2.IN3
-binInput[0] => Equal3.IN1
-binInput[0] => Equal4.IN3
-binInput[0] => Equal5.IN1
-binInput[0] => Equal6.IN3
-binInput[0] => Equal7.IN2
-binInput[0] => Equal8.IN3
-binInput[0] => Equal9.IN1
-binInput[0] => Equal10.IN3
-binInput[0] => Equal11.IN2
-binInput[0] => Equal12.IN3
-binInput[0] => Equal13.IN2
-binInput[0] => Equal14.IN3
-binInput[1] => Equal0.IN2
-binInput[1] => Equal1.IN3
-binInput[1] => Equal2.IN0
-binInput[1] => Equal3.IN0
-binInput[1] => Equal4.IN2
-binInput[1] => Equal5.IN3
-binInput[1] => Equal6.IN1
-binInput[1] => Equal7.IN1
-binInput[1] => Equal8.IN2
-binInput[1] => Equal9.IN3
-binInput[1] => Equal10.IN1
-binInput[1] => Equal11.IN1
-binInput[1] => Equal12.IN2
-binInput[1] => Equal13.IN3
-binInput[1] => Equal14.IN2
-binInput[2] => Equal0.IN1
-binInput[2] => Equal1.IN2
-binInput[2] => Equal2.IN2
-binInput[2] => Equal3.IN3
-binInput[2] => Equal4.IN0
-binInput[2] => Equal5.IN0
-binInput[2] => Equal6.IN0
-binInput[2] => Equal7.IN0
-binInput[2] => Equal8.IN1
-binInput[2] => Equal9.IN2
-binInput[2] => Equal10.IN2
-binInput[2] => Equal11.IN3
-binInput[2] => Equal12.IN1
-binInput[2] => Equal13.IN1
-binInput[2] => Equal14.IN1
-binInput[3] => Equal0.IN0
-binInput[3] => Equal1.IN1
-binInput[3] => Equal2.IN1
-binInput[3] => Equal3.IN2
-binInput[3] => Equal4.IN1
-binInput[3] => Equal5.IN2
-binInput[3] => Equal6.IN2
-binInput[3] => Equal7.IN3
-binInput[3] => Equal8.IN0
-binInput[3] => Equal9.IN0
-binInput[3] => Equal10.IN0
-binInput[3] => Equal11.IN0
-binInput[3] => Equal12.IN0
-binInput[3] => Equal13.IN0
-binInput[3] => Equal14.IN0
-enable => decOut_n.OUTPUTSELECT
-enable => decOut_n.OUTPUTSELECT
-enable => decOut_n.OUTPUTSELECT
-enable => decOut_n.OUTPUTSELECT
-enable => decOut_n.OUTPUTSELECT
-enable => decOut_n.OUTPUTSELECT
-enable => decOut_n.OUTPUTSELECT
-decOut_n[0] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[1] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[2] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[3] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[4] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[5] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[6] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.hif b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.hif
deleted file mode 100644
index bc56b43..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.lpc.html b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.lpc.html
deleted file mode 100644
index f68faa5..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.lpc.html
+++ /dev/null
@@ -1,34 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| system_core |
-5 |
-0 |
-0 |
-0 |
-7 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.lpc.rdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.lpc.rdb
deleted file mode 100644
index 1b75a36..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.lpc.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.lpc.txt b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.lpc.txt
deleted file mode 100644
index f01feb8..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.lpc.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; system_core ; 5 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.ammdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.ammdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.bpm b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.bpm
deleted file mode 100644
index ea984a6..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.cdb
deleted file mode 100644
index 9bc6c5c..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.hdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.kpt b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.kpt
deleted file mode 100644
index 0d325ee..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.logdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.qmsg b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.qmsg
deleted file mode 100644
index e893966..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.qmsg
+++ /dev/null
@@ -1,14 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678308849812 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678308849812 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 20:54:09 2023 " "Processing started: Wed Mar 8 20:54:09 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678308849812 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678308849812 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL " "Command: quartus_map --read_settings_files=on --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678308849813 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678308849933 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678308849934 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Bin7SegDecoder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Bin7SegDecoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Bin7SegDecoder-Behavioral " "Found design unit 1: Bin7SegDecoder-Behavioral" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/Bin7SegDecoder.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678308854924 ""} { "Info" "ISGN_ENTITY_NAME" "1 Bin7SegDecoder " "Found entity 1: Bin7SegDecoder" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/Bin7SegDecoder.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678308854924 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678308854924 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DisplayDemoVHDL.vhd 2 1 " "Found 2 design units, including 1 entities, in source file DisplayDemoVHDL.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DisplayDemoVHDL-Shell " "Found design unit 1: DisplayDemoVHDL-Shell" { } { { "DisplayDemoVHDL.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678308854925 ""} { "Info" "ISGN_ENTITY_NAME" "1 DisplayDemoVHDL " "Found entity 1: DisplayDemoVHDL" { } { { "DisplayDemoVHDL.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678308854925 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678308854925 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "DisplayDemoVHDL " "Elaborating entity \"DisplayDemoVHDL\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678308854951 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "Bin7SegDecoder Bin7SegDecoder:system_core A:behavioral " "Elaborating entity \"Bin7SegDecoder\" using architecture \"A:behavioral\" for hierarchy \"Bin7SegDecoder:system_core\"" { } { { "DisplayDemoVHDL.vhd" "system_core" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd" 18 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678308854955 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678308855359 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678308855689 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678308855689 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" { } { { "DisplayDemoVHDL.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd" 8 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1678308855711 "|DisplayDemoVHDL|KEY[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1678308855711 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "38 " "Implemented 38 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678308855711 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678308855711 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678308855711 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678308855711 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "428 " "Peak virtual memory: 428 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678308855717 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 20:54:15 2023 " "Processing ended: Wed Mar 8 20:54:15 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678308855717 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678308855717 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678308855717 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678308855717 ""}
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.rdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map.rdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map_bb.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map_bb.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map_bb.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map_bb.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map_bb.logdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.pre_map.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.root_partition.map.reg_db.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.routing.rdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.rtlv.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.rtlv_sg.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.rtlv_sg.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.rtlv_sg_swap.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.rtlv_sg_swap.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.sld_design_entry.sci b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.smart_action.txt b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.smart_action.txt
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--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.smart_action.txt
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-DONE
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.sta.qmsg b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.sta.qmsg
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-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678308865038 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678308865038 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 20:54:24 2023 " "Processing started: Wed Mar 8 20:54:24 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678308865038 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678308865038 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DisplayDemoVHDL -c DisplayDemoVHDL " "Command: quartus_sta DisplayDemoVHDL -c DisplayDemoVHDL" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678308865038 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678308865058 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678308865116 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678308865116 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678308865166 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678308865166 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DisplayDemoVHDL.sdc " "Synopsys Design Constraints File file not found: 'DisplayDemoVHDL.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678308865464 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678308865465 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678308865465 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678308865465 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678308865465 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678308865465 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678308865466 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678308865468 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678308865468 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865469 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865471 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865471 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865471 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865472 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865472 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678308865473 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678308865486 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678308865668 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678308865682 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678308865682 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678308865682 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678308865682 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865682 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865683 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865683 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865684 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865684 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865684 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678308865685 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678308865721 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678308865722 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678308865722 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678308865722 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865722 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865723 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865723 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865723 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308865724 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678308865943 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678308865944 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "535 " "Peak virtual memory: 535 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678308865953 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 20:54:25 2023 " "Processing ended: Wed Mar 8 20:54:25 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678308865953 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678308865953 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678308865953 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678308865953 ""}
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.sta.rdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.sta.rdb
deleted file mode 100644
index 4bdc376..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.sta_cmp.7_slow_1200mv_85c.tdb
deleted file mode 100644
index 01343d3..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.tis_db_list.ddb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.tis_db_list.ddb
deleted file mode 100644
index 73e5ec9..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index 87612ec..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index 6f3757e..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index 588c970..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.tmw_info b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.tmw_info
deleted file mode 100644
index 1bd50f7..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.tmw_info
+++ /dev/null
@@ -1,4 +0,0 @@
-start_full_compilation:s
-start_assembler:s-start_full_compilation
-start_timing_analyzer:s-start_full_compilation
-start_eda_netlist_writer:s-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.vpr.ammdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.vpr.ammdb
deleted file mode 100644
index 2d98843..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL_partition_pins.json b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL_partition_pins.json
deleted file mode 100644
index 7b4d209..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL_partition_pins.json
+++ /dev/null
@@ -1,101 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "LEDG[0]",
- "strict" : false
- },
- {
- "name" : "LEDG[1]",
- "strict" : false
- },
- {
- "name" : "LEDG[2]",
- "strict" : false
- },
- {
- "name" : "LEDG[3]",
- "strict" : false
- },
- {
- "name" : "LEDR[0]",
- "strict" : false
- },
- {
- "name" : "LEDR[1]",
- "strict" : false
- },
- {
- "name" : "LEDR[2]",
- "strict" : false
- },
- {
- "name" : "LEDR[3]",
- "strict" : false
- },
- {
- "name" : "LEDR[4]",
- "strict" : false
- },
- {
- "name" : "LEDR[5]",
- "strict" : false
- },
- {
- "name" : "LEDR[6]",
- "strict" : false
- },
- {
- "name" : "HEX0[0]",
- "strict" : false
- },
- {
- "name" : "HEX0[1]",
- "strict" : false
- },
- {
- "name" : "HEX0[2]",
- "strict" : false
- },
- {
- "name" : "HEX0[3]",
- "strict" : false
- },
- {
- "name" : "HEX0[4]",
- "strict" : false
- },
- {
- "name" : "HEX0[5]",
- "strict" : false
- },
- {
- "name" : "HEX0[6]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- },
- {
- "name" : "SW[2]",
- "strict" : false
- },
- {
- "name" : "SW[3]",
- "strict" : false
- },
- {
- "name" : "KEY[0]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/prev_cmp_DisplayDemoVHDL.qmsg b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/prev_cmp_DisplayDemoVHDL.qmsg
deleted file mode 100644
index 8499693..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/prev_cmp_DisplayDemoVHDL.qmsg
+++ /dev/null
@@ -1,12 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678308810958 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678308810958 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 20:53:30 2023 " "Processing started: Wed Mar 8 20:53:30 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678308810958 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678308810958 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL " "Command: quartus_map --read_settings_files=on --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678308810958 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678308811045 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678308811045 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Bin7SegDecoder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Bin7SegDecoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Bin7SegDecoder-Behavioral " "Found design unit 1: Bin7SegDecoder-Behavioral" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/Bin7SegDecoder.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678308815814 ""} { "Info" "ISGN_ENTITY_NAME" "1 Bin7SegDecoder " "Found entity 1: Bin7SegDecoder" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/Bin7SegDecoder.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678308815814 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678308815814 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DisplayDemoVHDL.vhd 2 1 " "Found 2 design units, including 1 entities, in source file DisplayDemoVHDL.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DisplayDemoVHDL-Shell " "Found design unit 1: DisplayDemoVHDL-Shell" { } { { "DisplayDemoVHDL.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678308815814 ""} { "Info" "ISGN_ENTITY_NAME" "1 DisplayDemoVHDL " "Found entity 1: DisplayDemoVHDL" { } { { "DisplayDemoVHDL.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678308815814 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678308815814 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "Bin7SegDecoder " "Elaborating entity \"Bin7SegDecoder\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678308815838 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678308816170 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678308816448 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678308816448 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "27 " "Implemented 27 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678308816461 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678308816461 ""} { "Info" "ICUT_CUT_TM_LCELLS" "15 " "Implemented 15 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678308816461 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678308816461 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678308816464 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 20:53:36 2023 " "Processing ended: Wed Mar 8 20:53:36 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678308816464 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678308816464 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678308816464 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678308816464 ""}
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/README b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.db_info b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.db_info
deleted file mode 100644
index 392a2ee..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Wed Mar 8 20:53:35 2023
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.ammdb
deleted file mode 100644
index 4e06226..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.cdb
deleted file mode 100644
index 193c4d8..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.hdb
deleted file mode 100644
index c6ecf6e..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.cmp.rcfdb
deleted file mode 100644
index 5e877a3..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.cdb
deleted file mode 100644
index 098bfc6..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.dpi b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.dpi
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.hbdb.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.hbdb.hb_info
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.hbdb.hdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.hdb
deleted file mode 100644
index 3401f91..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.kpt b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.kpt
deleted file mode 100644
index adee78f..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.root_partition.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.rrp.hdb b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.rrp.hdb
deleted file mode 100644
index c864b0b..0000000
Binary files a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/incremental_db/compiled_partitions/DisplayDemoVHDL.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.asm.rpt b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.asm.rpt
deleted file mode 100644
index 60fc7d5..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for DisplayDemoVHDL
-Wed Mar 8 20:54:24 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: DisplayDemoVHDL.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Wed Mar 8 20:54:24 2023 ;
-; Revision Name ; DisplayDemoVHDL ;
-; Top-level Entity Name ; DisplayDemoVHDL ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+----------------------------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+----------------------------------------------------------------------------------------------------------------+
-; File Name ;
-+----------------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.sof ;
-+----------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------+
-; Assembler Device Options: DisplayDemoVHDL.sof ;
-+----------------+------------------------------+
-; Option ; Setting ;
-+----------------+------------------------------+
-; JTAG usercode ; 0x00567351 ;
-; Checksum ; 0x00567351 ;
-+----------------+------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 8 20:54:22 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 365 megabytes
- Info: Processing ended: Wed Mar 8 20:54:24 2023
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.done b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.done
deleted file mode 100644
index a8f245c..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.done
+++ /dev/null
@@ -1 +0,0 @@
-Wed Mar 8 20:54:27 2023
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.eda.rpt b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.eda.rpt
deleted file mode 100644
index b7de74f..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.eda.rpt
+++ /dev/null
@@ -1,94 +0,0 @@
-EDA Netlist Writer report for DisplayDemoVHDL
-Wed Mar 8 20:54:26 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Wed Mar 8 20:54:26 2023 ;
-; Revision Name ; DisplayDemoVHDL ;
-; Top-level Entity Name ; DisplayDemoVHDL ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+-----------------------------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+-----------------------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/DisplayDemoVHDL.vho ;
-+-----------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 8 20:54:26 2023
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file DisplayDemoVHDL.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 613 megabytes
- Info: Processing ended: Wed Mar 8 20:54:26 2023
- Info: Elapsed time: 00:00:00
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.fit.rpt b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.fit.rpt
deleted file mode 100644
index be4162a..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.fit.rpt
+++ /dev/null
@@ -1,2608 +0,0 @@
-Fitter report for DisplayDemoVHDL
-Wed Mar 8 20:54:22 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Wed Mar 8 20:54:22 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; DisplayDemoVHDL ;
-; Top-level Entity Name ; DisplayDemoVHDL ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 14 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 14 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 24 / 529 ( 5 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.1% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; CLOCK_50 ; PIN_Y2 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_H19 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; SW[10] ; PIN_AC24 ; QSF Assignment ;
-; Location ; ; ; SW[11] ; PIN_AB24 ; QSF Assignment ;
-; Location ; ; ; SW[12] ; PIN_AB23 ; QSF Assignment ;
-; Location ; ; ; SW[13] ; PIN_AA24 ; QSF Assignment ;
-; Location ; ; ; SW[14] ; PIN_AA23 ; QSF Assignment ;
-; Location ; ; ; SW[15] ; PIN_AA22 ; QSF Assignment ;
-; Location ; ; ; SW[16] ; PIN_Y24 ; QSF Assignment ;
-; Location ; ; ; SW[17] ; PIN_Y23 ; QSF Assignment ;
-; Location ; ; ; SW[4] ; PIN_AB27 ; QSF Assignment ;
-; Location ; ; ; SW[5] ; PIN_AC26 ; QSF Assignment ;
-; Location ; ; ; SW[6] ; PIN_AD26 ; QSF Assignment ;
-; Location ; ; ; SW[7] ; PIN_AB26 ; QSF Assignment ;
-; Location ; ; ; SW[8] ; PIN_AC25 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AB25 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 73 ) ; 0.00 % ( 0 / 73 ) ; 0.00 % ( 0 / 73 ) ;
-; -- Achieved ; 0.00 % ( 0 / 73 ) ; 0.00 % ( 0 / 73 ) ; 0.00 % ( 0 / 73 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 63 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.pin.
-
-
-+----------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+------------------------+
-; Total logic elements ; 14 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 14 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 7 ;
-; -- 3 input functions ; 1 ;
-; -- <=2 input functions ; 6 ;
-; -- Register only ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 14 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers* ; 0 / 117,053 ( 0 % ) ;
-; -- Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 1 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 24 / 529 ( 5 % ) ;
-; -- Clock pins ; 0 / 7 ( 0 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.4% / 0.4% / 0.6% ;
-; Maximum fan-out ; 9 ;
-; Highest non-global fan-out ; 9 ;
-; Total fan-out ; 90 ;
-; Average fan-out ; 1.25 ;
-+---------------------------------------------+------------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 14 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 14 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 7 ; 0 ;
-; -- 3 input functions ; 1 ; 0 ;
-; -- <=2 input functions ; 6 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 14 ; 0 ;
-; -- arithmetic mode ; 0 ; 0 ;
-; ; ; ;
-; Total registers ; 0 ; 0 ;
-; -- Dedicated logic registers ; 0 / 114480 ( 0 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 1 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 24 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 85 ; 5 ;
-; -- Registered Connections ; 0 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 6 ; 0 ;
-; -- Output Ports ; 18 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+-----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; KEY[0] ; M23 ; 6 ; 115 ; 40 ; 7 ; 7 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; KEY[1] ; M21 ; 6 ; 115 ; 53 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 8 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 8 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 8 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[3] ; AD27 ; 5 ; 115 ; 13 ; 7 ; 9 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; HEX0[0] ; G18 ; 7 ; 69 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[1] ; F22 ; 7 ; 107 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[2] ; E17 ; 7 ; 67 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[3] ; L26 ; 6 ; 115 ; 50 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[4] ; L25 ; 6 ; 115 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[5] ; J22 ; 6 ; 115 ; 67 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[6] ; H22 ; 6 ; 115 ; 69 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDG[0] ; E21 ; 7 ; 107 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDG[1] ; E22 ; 7 ; 111 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDG[2] ; E25 ; 7 ; 83 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDG[3] ; E24 ; 7 ; 85 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[2] ; E19 ; 7 ; 94 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[3] ; F21 ; 7 ; 107 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[4] ; F18 ; 7 ; 87 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[5] ; E18 ; 7 ; 87 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[6] ; J19 ; 7 ; 72 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 0 / 63 ( 0 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 4 / 65 ( 6 % ) ; 2.5V ; -- ;
-; 6 ; 7 / 58 ( 12 % ) ; 2.5V ; -- ;
-; 7 ; 14 / 72 ( 19 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA23 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA24 ; 279 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB24 ; 274 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB25 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB26 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB27 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC25 ; 272 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC26 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD27 ; 286 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E18 ; 427 ; 7 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E19 ; 421 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; LEDG[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E22 ; 403 ; 7 ; LEDG[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; LEDG[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E25 ; 434 ; 7 ; LEDG[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F22 ; 409 ; 7 ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; HEX0[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; HEX0[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; HEX0[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; HEX0[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; L26 ; 363 ; 6 ; HEX0[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; KEY[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y24 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; KEY[1] ; Incomplete set of assignments ;
-; LEDG[0] ; Incomplete set of assignments ;
-; LEDG[1] ; Incomplete set of assignments ;
-; LEDG[2] ; Incomplete set of assignments ;
-; LEDG[3] ; Incomplete set of assignments ;
-; LEDR[0] ; Incomplete set of assignments ;
-; LEDR[1] ; Incomplete set of assignments ;
-; LEDR[2] ; Incomplete set of assignments ;
-; LEDR[3] ; Incomplete set of assignments ;
-; LEDR[4] ; Incomplete set of assignments ;
-; LEDR[5] ; Incomplete set of assignments ;
-; LEDR[6] ; Incomplete set of assignments ;
-; HEX0[0] ; Incomplete set of assignments ;
-; HEX0[1] ; Incomplete set of assignments ;
-; HEX0[2] ; Incomplete set of assignments ;
-; HEX0[3] ; Incomplete set of assignments ;
-; HEX0[4] ; Incomplete set of assignments ;
-; HEX0[5] ; Incomplete set of assignments ;
-; HEX0[6] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-; SW[1] ; Incomplete set of assignments ;
-; SW[2] ; Incomplete set of assignments ;
-; SW[3] ; Incomplete set of assignments ;
-; KEY[0] ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------+-----------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------+-----------------+--------------+
-; |DisplayDemoVHDL ; 14 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 24 ; 0 ; 14 (0) ; 0 (0) ; 0 (0) ; |DisplayDemoVHDL ; DisplayDemoVHDL ; work ;
-; |Bin7SegDecoder:system_core| ; 14 (14) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; |DisplayDemoVHDL|Bin7SegDecoder:system_core ; Bin7SegDecoder ; work ;
-+---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------+-----------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-----------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; KEY[1] ; Input ; -- ; -- ; -- ; -- ; -- ;
-; LEDG[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDG[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDG[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDG[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; KEY[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+--------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+--------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+--------------------------------------------------+-------------------+---------+
-; KEY[1] ; ; ;
-; SW[0] ; ; ;
-; - Bin7SegDecoder:system_core|decOut_n~6 ; 0 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~8 ; 0 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~10 ; 0 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~12 ; 0 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~14 ; 0 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n[3]~2 ; 0 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n[6]~5 ; 0 ; 6 ;
-; - LEDG[0]~output ; 0 ; 6 ;
-; SW[1] ; ; ;
-; - Bin7SegDecoder:system_core|decOut_n~6 ; 0 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~8 ; 0 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~10 ; 0 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~12 ; 0 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~14 ; 0 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n[3]~2 ; 0 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n[6]~5 ; 0 ; 6 ;
-; - LEDG[1]~output ; 0 ; 6 ;
-; SW[2] ; ; ;
-; - Bin7SegDecoder:system_core|decOut_n~6 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~8 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~11 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~12 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~14 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n[3]~2 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n[6]~5 ; 1 ; 6 ;
-; - LEDG[2]~output ; 1 ; 6 ;
-; SW[3] ; ; ;
-; - Bin7SegDecoder:system_core|decOut_n~6 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~8 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~10 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~11 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~12 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~14 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n[3]~2 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n[6]~5 ; 1 ; 6 ;
-; - LEDG[3]~output ; 1 ; 6 ;
-; KEY[0] ; ; ;
-; - Bin7SegDecoder:system_core|decOut_n~7 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~9 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~11 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~13 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n~15 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n[3]~16 ; 1 ; 6 ;
-; - Bin7SegDecoder:system_core|decOut_n[6]~17 ; 1 ; 6 ;
-+--------------------------------------------------+-------------------+---------+
-
-
-+------------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+------------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+------------------------+
-; Block interconnects ; 22 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 21 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 21 / 209,544 ( < 1 % ) ;
-; Direct links ; 0 / 342,891 ( 0 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 7 / 119,088 ( < 1 % ) ;
-; R24 interconnects ; 12 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 41 / 289,782 ( < 1 % ) ;
-+-----------------------+------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+---------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 14.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 1 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-+---------------------------------------------+-----------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+----------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 14.00) ; Number of LABs (Total = 1) ;
-+----------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 1 ;
-+----------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 7.00) ; Number of LABs (Total = 1) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 1 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 5.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 24 ; 24 ; 0 ; 0 ; 24 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; 0 ; 0 ; 6 ; 18 ; 0 ; 6 ; 0 ; 0 ; 18 ; 0 ; 24 ; 24 ; 24 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 24 ; 0 ; 0 ; 24 ; 24 ; 0 ; 0 ; 24 ; 24 ; 24 ; 24 ; 24 ; 24 ; 6 ; 24 ; 24 ; 24 ; 18 ; 6 ; 24 ; 18 ; 24 ; 24 ; 6 ; 24 ; 0 ; 0 ; 0 ; 24 ; 24 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; KEY[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDG[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDG[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDG[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDG[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "DisplayDemoVHDL"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'DisplayDemoVHDL.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y61 to location X115_Y73
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 502 warnings
- Info: Peak virtual memory: 1153 megabytes
- Info: Processing ended: Wed Mar 8 20:54:22 2023
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:10
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.fit.smsg b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.fit.summary b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.fit.summary
deleted file mode 100644
index f76fd96..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Wed Mar 8 20:54:22 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : DisplayDemoVHDL
-Top-level Entity Name : DisplayDemoVHDL
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 14 / 114,480 ( < 1 % )
- Total combinational functions : 14 / 114,480 ( < 1 % )
- Dedicated logic registers : 0 / 114,480 ( 0 % )
-Total registers : 0
-Total pins : 24 / 529 ( 5 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.flow.rpt b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.flow.rpt
deleted file mode 100644
index 733f66b..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.flow.rpt
+++ /dev/null
@@ -1,136 +0,0 @@
-Flow report for DisplayDemoVHDL
-Wed Mar 8 20:54:26 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Wed Mar 8 20:54:26 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; DisplayDemoVHDL ;
-; Top-level Entity Name ; DisplayDemoVHDL ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 14 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 14 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 24 / 529 ( 5 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/08/2023 20:54:09 ;
-; Main task ; Compilation ;
-; Revision Name ; DisplayDemoVHDL ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 2690080394329.167830884924110 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 428 MB ; 00:00:14 ;
-; Fitter ; 00:00:06 ; 1.0 ; 1153 MB ; 00:00:09 ;
-; Assembler ; 00:00:02 ; 1.0 ; 365 MB ; 00:00:02 ;
-; Timing Analyzer ; 00:00:01 ; 1.0 ; 535 MB ; 00:00:01 ;
-; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 613 MB ; 00:00:00 ;
-; Total ; 00:00:15 ; -- ; -- ; 00:00:26 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL
-quartus_fit --read_settings_files=off --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL
-quartus_asm --read_settings_files=off --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL
-quartus_sta DisplayDemoVHDL -c DisplayDemoVHDL
-quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.jdi b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.jdi
deleted file mode 100644
index 23e4511..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.map.rpt b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.map.rpt
deleted file mode 100644
index 4fdabdd..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.map.rpt
+++ /dev/null
@@ -1,302 +0,0 @@
-Analysis & Synthesis report for DisplayDemoVHDL
-Wed Mar 8 20:54:15 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Multiplexer Restructuring Statistics (Restructuring Performed)
- 10. Post-Synthesis Netlist Statistics for Top Partition
- 11. Elapsed Time Per Partition
- 12. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Wed Mar 8 20:54:15 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; DisplayDemoVHDL ;
-; Top-level Entity Name ; DisplayDemoVHDL ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 14 ;
-; Total combinational functions ; 14 ;
-; Dedicated logic registers ; 0 ;
-; Total registers ; 0 ;
-; Total pins ; 24 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; DisplayDemoVHDL ; DisplayDemoVHDL ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------------------------------------+---------+
-; Bin7SegDecoder.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/Bin7SegDecoder.vhd ; ;
-; DisplayDemoVHDL.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd ; ;
-+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------------------------------------+---------+
-
-
-+-----------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+-------------+
-; Resource ; Usage ;
-+---------------------------------------------+-------------+
-; Estimated Total logic elements ; 14 ;
-; ; ;
-; Total combinational functions ; 14 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 7 ;
-; -- 3 input functions ; 1 ;
-; -- <=2 input functions ; 6 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 14 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers ; 0 ;
-; -- Dedicated logic registers ; 0 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 24 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; SW[3]~input ;
-; Maximum fan-out ; 9 ;
-; Total fan-out ; 85 ;
-; Average fan-out ; 1.37 ;
-+---------------------------------------------+-------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+---------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------+-----------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+---------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------+-----------------+--------------+
-; |DisplayDemoVHDL ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 24 ; 0 ; |DisplayDemoVHDL ; DisplayDemoVHDL ; work ;
-; |Bin7SegDecoder:system_core| ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DisplayDemoVHDL|Bin7SegDecoder:system_core ; Bin7SegDecoder ; work ;
-+---------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------+-----------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 0 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------+
-; 17:1 ; 2 bits ; 22 LEs ; 16 LEs ; 6 LEs ; No ; |DisplayDemoVHDL|Bin7SegDecoder:system_core|decOut_n[3] ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 24 ;
-; cycloneiii_lcell_comb ; 14 ;
-; normal ; 14 ;
-; 2 data inputs ; 6 ;
-; 3 data inputs ; 1 ;
-; 4 data inputs ; 7 ;
-; ; ;
-; Max LUT depth ; 2.00 ;
-; Average LUT depth ; 1.95 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 8 20:54:09 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DisplayDemoVHDL -c DisplayDemoVHDL
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 2 design units, including 1 entities, in source file Bin7SegDecoder.vhd
- Info (12022): Found design unit 1: Bin7SegDecoder-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/Bin7SegDecoder.vhd Line: 13
- Info (12023): Found entity 1: Bin7SegDecoder File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/Bin7SegDecoder.vhd Line: 4
-Info (12021): Found 2 design units, including 1 entities, in source file DisplayDemoVHDL.vhd
- Info (12022): Found design unit 1: DisplayDemoVHDL-Shell File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd Line: 15
- Info (12023): Found entity 1: DisplayDemoVHDL File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd Line: 4
-Info (12127): Elaborating entity "DisplayDemoVHDL" for the top level hierarchy
-Info (12129): Elaborating entity "Bin7SegDecoder" using architecture "A:behavioral" for hierarchy "Bin7SegDecoder:system_core" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd Line: 18
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 1 input pin(s) that do not drive logic
- Warning (15610): No output dependent on input pin "KEY[1]" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd Line: 8
-Info (21057): Implemented 38 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 6 input pins
- Info (21059): Implemented 18 output pins
- Info (21061): Implemented 14 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings
- Info: Peak virtual memory: 428 megabytes
- Info: Processing ended: Wed Mar 8 20:54:15 2023
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:14
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.map.summary b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.map.summary
deleted file mode 100644
index 5161556..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Wed Mar 8 20:54:15 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : DisplayDemoVHDL
-Top-level Entity Name : DisplayDemoVHDL
-Family : Cyclone IV E
-Total logic elements : 14
- Total combinational functions : 14
- Dedicated logic registers : 0
-Total registers : 0
-Total pins : 24
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.pin b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.pin
deleted file mode 100644
index ec7b33c..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "DisplayDemoVHDL" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5 :
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC26 : : : : 5 :
-SW[2] : AC27 : input : 2.5 V : : 5 : Y
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5 :
-SW[3] : AD27 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-HEX0[2] : E17 : output : 2.5 V : : 7 : Y
-LEDR[5] : E18 : output : 2.5 V : : 7 : Y
-LEDR[2] : E19 : output : 2.5 V : : 7 : Y
-VCCIO7 : E20 : power : : 2.5V : 7 :
-LEDG[0] : E21 : output : 2.5 V : : 7 : Y
-LEDG[1] : E22 : output : 2.5 V : : 7 : Y
-VCCIO7 : E23 : power : : 2.5V : 7 :
-LEDG[3] : E24 : output : 2.5 V : : 7 : Y
-LEDG[2] : E25 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-LEDR[4] : F18 : output : 2.5 V : : 7 : Y
-LEDR[1] : F19 : output : 2.5 V : : 7 : Y
-GND : F20 : gnd : : : :
-LEDR[3] : F21 : output : 2.5 V : : 7 : Y
-HEX0[1] : F22 : output : 2.5 V : : 7 : Y
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-HEX0[0] : G18 : output : 2.5 V : : 7 : Y
-LEDR[0] : G19 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
-VCCIO7 : H18 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-HEX0[6] : H22 : output : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
-GND : J18 : gnd : : : :
-LEDR[6] : J19 : output : 2.5 V : : 7 : Y
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-HEX0[5] : J22 : output : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-HEX0[4] : L25 : output : 2.5 V : : 6 : Y
-HEX0[3] : L26 : output : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-KEY[1] : M21 : input : 2.5 V : : 6 : Y
-MSEL2 : M22 : : : : 6 :
-KEY[0] : M23 : input : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-GND+ : Y2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.sld b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.sta.rpt b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.sta.rpt
deleted file mode 100644
index ec6d034..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.sta.rpt
+++ /dev/null
@@ -1,543 +0,0 @@
-Timing Analyzer report for DisplayDemoVHDL
-Wed Mar 8 20:54:25 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Unconstrained Input Ports
- 37. Unconstrained Output Ports
- 38. Unconstrained Input Ports
- 39. Unconstrained Output Ports
- 40. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; DisplayDemoVHDL ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.2% ;
-+----------------------------+-------------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDG[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDG[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDG[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ;
-; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ;
-; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ;
-; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ;
-; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ;
-; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ;
-; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ;
-; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ;
-; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ;
-; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ;
-; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 5 ; 5 ;
-; Unconstrained Input Port Paths ; 74 ; 74 ;
-; Unconstrained Output Ports ; 18 ; 18 ;
-; Unconstrained Output Port Paths ; 74 ; 74 ;
-+---------------------------------+-------+------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 8 20:54:24 2023
-Info: Command: quartus_sta DisplayDemoVHDL -c DisplayDemoVHDL
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'DisplayDemoVHDL.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 535 megabytes
- Info: Processing ended: Wed Mar 8 20:54:25 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.sta.summary b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.sta.summary
deleted file mode 100644
index aa5b327..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/output_files/DisplayDemoVHDL.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/DisplayDemoVHDL.sft b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/DisplayDemoVHDL.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/DisplayDemoVHDL.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/DisplayDemoVHDL.vho b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/DisplayDemoVHDL.vho
deleted file mode 100644
index 062513e..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/DisplayDemoVHDL.vho
+++ /dev/null
@@ -1,736 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/08/2023 20:54:26"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY DisplayDemoVHDL IS
- PORT (
- SW : IN std_logic_vector(3 DOWNTO 0);
- KEY : IN std_logic_vector(1 DOWNTO 0);
- LEDG : OUT std_logic_vector(3 DOWNTO 0);
- LEDR : OUT std_logic_vector(6 DOWNTO 0);
- HEX0 : OUT std_logic_vector(6 DOWNTO 0)
- );
-END DisplayDemoVHDL;
-
--- Design Ports Information
--- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDG[0] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDG[1] => Location: PIN_E22, I/O Standard: 2.5 V, Current Strength: Default
--- LEDG[2] => Location: PIN_E25, I/O Standard: 2.5 V, Current Strength: Default
--- LEDG[3] => Location: PIN_E24, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[4] => Location: PIN_F18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[5] => Location: PIN_E18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[6] => Location: PIN_J19, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[0] => Location: PIN_G18, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[1] => Location: PIN_F22, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[2] => Location: PIN_E17, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[3] => Location: PIN_L26, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[4] => Location: PIN_L25, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[5] => Location: PIN_J22, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[6] => Location: PIN_H22, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF DisplayDemoVHDL IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_SW : std_logic_vector(3 DOWNTO 0);
-SIGNAL ww_KEY : std_logic_vector(1 DOWNTO 0);
-SIGNAL ww_LEDG : std_logic_vector(3 DOWNTO 0);
-SIGNAL ww_LEDR : std_logic_vector(6 DOWNTO 0);
-SIGNAL ww_HEX0 : std_logic_vector(6 DOWNTO 0);
-SIGNAL \KEY[1]~input_o\ : std_logic;
-SIGNAL \LEDG[0]~output_o\ : std_logic;
-SIGNAL \LEDG[1]~output_o\ : std_logic;
-SIGNAL \LEDG[2]~output_o\ : std_logic;
-SIGNAL \LEDG[3]~output_o\ : std_logic;
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \LEDR[1]~output_o\ : std_logic;
-SIGNAL \LEDR[2]~output_o\ : std_logic;
-SIGNAL \LEDR[3]~output_o\ : std_logic;
-SIGNAL \LEDR[4]~output_o\ : std_logic;
-SIGNAL \LEDR[5]~output_o\ : std_logic;
-SIGNAL \LEDR[6]~output_o\ : std_logic;
-SIGNAL \HEX0[0]~output_o\ : std_logic;
-SIGNAL \HEX0[1]~output_o\ : std_logic;
-SIGNAL \HEX0[2]~output_o\ : std_logic;
-SIGNAL \HEX0[3]~output_o\ : std_logic;
-SIGNAL \HEX0[4]~output_o\ : std_logic;
-SIGNAL \HEX0[5]~output_o\ : std_logic;
-SIGNAL \HEX0[6]~output_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[2]~input_o\ : std_logic;
-SIGNAL \SW[3]~input_o\ : std_logic;
-SIGNAL \KEY[0]~input_o\ : std_logic;
-SIGNAL \system_core|decOut_n~6_combout\ : std_logic;
-SIGNAL \system_core|decOut_n~7_combout\ : std_logic;
-SIGNAL \system_core|decOut_n~8_combout\ : std_logic;
-SIGNAL \system_core|decOut_n~9_combout\ : std_logic;
-SIGNAL \system_core|decOut_n~10_combout\ : std_logic;
-SIGNAL \system_core|decOut_n~11_combout\ : std_logic;
-SIGNAL \system_core|decOut_n[3]~2_combout\ : std_logic;
-SIGNAL \system_core|decOut_n[3]~16_combout\ : std_logic;
-SIGNAL \system_core|decOut_n~12_combout\ : std_logic;
-SIGNAL \system_core|decOut_n~13_combout\ : std_logic;
-SIGNAL \system_core|decOut_n~14_combout\ : std_logic;
-SIGNAL \system_core|decOut_n~15_combout\ : std_logic;
-SIGNAL \system_core|decOut_n[6]~5_combout\ : std_logic;
-SIGNAL \system_core|decOut_n[6]~17_combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-ww_SW <= SW;
-ww_KEY <= KEY;
-LEDG <= ww_LEDG;
-LEDR <= ww_LEDR;
-HEX0 <= ww_HEX0;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X107_Y73_N9
-\LEDG[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \SW[0]~input_o\,
- devoe => ww_devoe,
- o => \LEDG[0]~output_o\);
-
--- Location: IOOBUF_X111_Y73_N9
-\LEDG[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \SW[1]~input_o\,
- devoe => ww_devoe,
- o => \LEDG[1]~output_o\);
-
--- Location: IOOBUF_X83_Y73_N2
-\LEDG[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \SW[2]~input_o\,
- devoe => ww_devoe,
- o => \LEDG[2]~output_o\);
-
--- Location: IOOBUF_X85_Y73_N23
-\LEDG[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \SW[3]~input_o\,
- devoe => ww_devoe,
- o => \LEDG[3]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N16
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n~7_combout\,
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N2
-\LEDR[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n~9_combout\,
- devoe => ww_devoe,
- o => \LEDR[1]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N9
-\LEDR[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n~11_combout\,
- devoe => ww_devoe,
- o => \LEDR[2]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N16
-\LEDR[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n[3]~16_combout\,
- devoe => ww_devoe,
- o => \LEDR[3]~output_o\);
-
--- Location: IOOBUF_X87_Y73_N16
-\LEDR[4]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n~13_combout\,
- devoe => ww_devoe,
- o => \LEDR[4]~output_o\);
-
--- Location: IOOBUF_X87_Y73_N9
-\LEDR[5]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n~15_combout\,
- devoe => ww_devoe,
- o => \LEDR[5]~output_o\);
-
--- Location: IOOBUF_X72_Y73_N9
-\LEDR[6]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n[6]~17_combout\,
- devoe => ww_devoe,
- o => \LEDR[6]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N23
-\HEX0[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n~7_combout\,
- devoe => ww_devoe,
- o => \HEX0[0]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N23
-\HEX0[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n~9_combout\,
- devoe => ww_devoe,
- o => \HEX0[1]~output_o\);
-
--- Location: IOOBUF_X67_Y73_N23
-\HEX0[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n~11_combout\,
- devoe => ww_devoe,
- o => \HEX0[2]~output_o\);
-
--- Location: IOOBUF_X115_Y50_N2
-\HEX0[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n[3]~16_combout\,
- devoe => ww_devoe,
- o => \HEX0[3]~output_o\);
-
--- Location: IOOBUF_X115_Y54_N16
-\HEX0[4]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n~13_combout\,
- devoe => ww_devoe,
- o => \HEX0[4]~output_o\);
-
--- Location: IOOBUF_X115_Y67_N16
-\HEX0[5]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n~15_combout\,
- devoe => ww_devoe,
- o => \HEX0[5]~output_o\);
-
--- Location: IOOBUF_X115_Y69_N2
-\HEX0[6]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|decOut_n[6]~17_combout\,
- devoe => ww_devoe,
- o => \HEX0[6]~output_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N8
-\SW[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(2),
- o => \SW[2]~input_o\);
-
--- Location: IOIBUF_X115_Y13_N8
-\SW[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(3),
- o => \SW[3]~input_o\);
-
--- Location: IOIBUF_X115_Y40_N8
-\KEY[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY(0),
- o => \KEY[0]~input_o\);
-
--- Location: LCCOMB_X107_Y72_N24
-\system_core|decOut_n~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n~6_combout\ = (\SW[3]~input_o\ & (\SW[0]~input_o\ & (\SW[1]~input_o\ $ (\SW[2]~input_o\)))) # (!\SW[3]~input_o\ & (!\SW[1]~input_o\ & (\SW[0]~input_o\ $ (\SW[2]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000100110000100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \system_core|decOut_n~6_combout\);
-
--- Location: LCCOMB_X107_Y72_N26
-\system_core|decOut_n~7\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n~7_combout\ = (\KEY[0]~input_o\) # (\system_core|decOut_n~6_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \KEY[0]~input_o\,
- datad => \system_core|decOut_n~6_combout\,
- combout => \system_core|decOut_n~7_combout\);
-
--- Location: LCCOMB_X107_Y72_N20
-\system_core|decOut_n~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n~8_combout\ = (\SW[3]~input_o\ & ((\SW[0]~input_o\ & (\SW[1]~input_o\)) # (!\SW[0]~input_o\ & ((\SW[2]~input_o\))))) # (!\SW[3]~input_o\ & (\SW[2]~input_o\ & (\SW[0]~input_o\ $ (\SW[1]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1011011010000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \system_core|decOut_n~8_combout\);
-
--- Location: LCCOMB_X107_Y72_N22
-\system_core|decOut_n~9\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n~9_combout\ = (\KEY[0]~input_o\) # (\system_core|decOut_n~8_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \KEY[0]~input_o\,
- datad => \system_core|decOut_n~8_combout\,
- combout => \system_core|decOut_n~9_combout\);
-
--- Location: LCCOMB_X107_Y72_N16
-\system_core|decOut_n~10\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n~10_combout\ = (\SW[3]~input_o\ & (\SW[0]~input_o\ & !\SW[1]~input_o\)) # (!\SW[3]~input_o\ & (!\SW[0]~input_o\ & \SW[1]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0001100000011000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- combout => \system_core|decOut_n~10_combout\);
-
--- Location: LCCOMB_X107_Y72_N18
-\system_core|decOut_n~11\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n~11_combout\ = (\KEY[0]~input_o\) # ((\SW[3]~input_o\ & (!\system_core|decOut_n~10_combout\ & \SW[2]~input_o\)) # (!\SW[3]~input_o\ & (\system_core|decOut_n~10_combout\ & !\SW[2]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111001011110100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \system_core|decOut_n~10_combout\,
- datac => \KEY[0]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \system_core|decOut_n~11_combout\);
-
--- Location: LCCOMB_X107_Y72_N12
-\system_core|decOut_n[3]~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n[3]~2_combout\ = (\SW[1]~input_o\ & ((\SW[0]~input_o\ & ((\SW[2]~input_o\))) # (!\SW[0]~input_o\ & (\SW[3]~input_o\ & !\SW[2]~input_o\)))) # (!\SW[1]~input_o\ & (!\SW[3]~input_o\ & (\SW[0]~input_o\ $ (\SW[2]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100000100100100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \system_core|decOut_n[3]~2_combout\);
-
--- Location: LCCOMB_X107_Y72_N14
-\system_core|decOut_n[3]~16\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n[3]~16_combout\ = (\KEY[0]~input_o\) # (\system_core|decOut_n[3]~2_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \KEY[0]~input_o\,
- datad => \system_core|decOut_n[3]~2_combout\,
- combout => \system_core|decOut_n[3]~16_combout\);
-
--- Location: LCCOMB_X107_Y72_N28
-\system_core|decOut_n~12\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n~12_combout\ = (\SW[1]~input_o\ & (!\SW[3]~input_o\ & (\SW[0]~input_o\))) # (!\SW[1]~input_o\ & ((\SW[2]~input_o\ & (!\SW[3]~input_o\)) # (!\SW[2]~input_o\ & ((\SW[0]~input_o\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0100010101001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \system_core|decOut_n~12_combout\);
-
--- Location: LCCOMB_X107_Y72_N30
-\system_core|decOut_n~13\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n~13_combout\ = (\KEY[0]~input_o\) # (\system_core|decOut_n~12_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \KEY[0]~input_o\,
- datad => \system_core|decOut_n~12_combout\,
- combout => \system_core|decOut_n~13_combout\);
-
--- Location: LCCOMB_X107_Y72_N8
-\system_core|decOut_n~14\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n~14_combout\ = (\SW[0]~input_o\ & (\SW[3]~input_o\ $ (((\SW[1]~input_o\) # (!\SW[2]~input_o\))))) # (!\SW[0]~input_o\ & (!\SW[3]~input_o\ & (\SW[1]~input_o\ & !\SW[2]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0100100001010100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \system_core|decOut_n~14_combout\);
-
--- Location: LCCOMB_X107_Y72_N2
-\system_core|decOut_n~15\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n~15_combout\ = (\system_core|decOut_n~14_combout\) # (\KEY[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111110011111100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \system_core|decOut_n~14_combout\,
- datac => \KEY[0]~input_o\,
- combout => \system_core|decOut_n~15_combout\);
-
--- Location: LCCOMB_X107_Y72_N0
-\system_core|decOut_n[6]~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n[6]~5_combout\ = (\SW[0]~input_o\ & (!\SW[3]~input_o\ & (\SW[1]~input_o\ $ (!\SW[2]~input_o\)))) # (!\SW[0]~input_o\ & (!\SW[1]~input_o\ & (\SW[3]~input_o\ $ (!\SW[2]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0100001000000101",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \system_core|decOut_n[6]~5_combout\);
-
--- Location: LCCOMB_X107_Y72_N10
-\system_core|decOut_n[6]~17\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|decOut_n[6]~17_combout\ = (\KEY[0]~input_o\) # (\system_core|decOut_n[6]~5_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \KEY[0]~input_o\,
- datad => \system_core|decOut_n[6]~5_combout\,
- combout => \system_core|decOut_n[6]~17_combout\);
-
--- Location: IOIBUF_X115_Y53_N15
-\KEY[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY(1),
- o => \KEY[1]~input_o\);
-
-ww_LEDG(0) <= \LEDG[0]~output_o\;
-
-ww_LEDG(1) <= \LEDG[1]~output_o\;
-
-ww_LEDG(2) <= \LEDG[2]~output_o\;
-
-ww_LEDG(3) <= \LEDG[3]~output_o\;
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-
-ww_LEDR(1) <= \LEDR[1]~output_o\;
-
-ww_LEDR(2) <= \LEDR[2]~output_o\;
-
-ww_LEDR(3) <= \LEDR[3]~output_o\;
-
-ww_LEDR(4) <= \LEDR[4]~output_o\;
-
-ww_LEDR(5) <= \LEDR[5]~output_o\;
-
-ww_LEDR(6) <= \LEDR[6]~output_o\;
-
-ww_HEX0(0) <= \HEX0[0]~output_o\;
-
-ww_HEX0(1) <= \HEX0[1]~output_o\;
-
-ww_HEX0(2) <= \HEX0[2]~output_o\;
-
-ww_HEX0(3) <= \HEX0[3]~output_o\;
-
-ww_HEX0(4) <= \HEX0[4]~output_o\;
-
-ww_HEX0(5) <= \HEX0[5]~output_o\;
-
-ww_HEX0(6) <= \HEX0[6]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/DisplayDemoVHDL_modelsim.xrf b/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/DisplayDemoVHDL_modelsim.xrf
deleted file mode 100644
index 768aae0..0000000
--- a/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/DisplayDemoVHDL_modelsim.xrf
+++ /dev/null
@@ -1,48 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/Bin7SegDecoder.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cbx.xml
-design_name = hard_block
-design_name = DisplayDemoVHDL
-instance = comp, \LEDG[0]~output\, LEDG[0]~output, DisplayDemoVHDL, 1
-instance = comp, \LEDG[1]~output\, LEDG[1]~output, DisplayDemoVHDL, 1
-instance = comp, \LEDG[2]~output\, LEDG[2]~output, DisplayDemoVHDL, 1
-instance = comp, \LEDG[3]~output\, LEDG[3]~output, DisplayDemoVHDL, 1
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, DisplayDemoVHDL, 1
-instance = comp, \LEDR[1]~output\, LEDR[1]~output, DisplayDemoVHDL, 1
-instance = comp, \LEDR[2]~output\, LEDR[2]~output, DisplayDemoVHDL, 1
-instance = comp, \LEDR[3]~output\, LEDR[3]~output, DisplayDemoVHDL, 1
-instance = comp, \LEDR[4]~output\, LEDR[4]~output, DisplayDemoVHDL, 1
-instance = comp, \LEDR[5]~output\, LEDR[5]~output, DisplayDemoVHDL, 1
-instance = comp, \LEDR[6]~output\, LEDR[6]~output, DisplayDemoVHDL, 1
-instance = comp, \HEX0[0]~output\, HEX0[0]~output, DisplayDemoVHDL, 1
-instance = comp, \HEX0[1]~output\, HEX0[1]~output, DisplayDemoVHDL, 1
-instance = comp, \HEX0[2]~output\, HEX0[2]~output, DisplayDemoVHDL, 1
-instance = comp, \HEX0[3]~output\, HEX0[3]~output, DisplayDemoVHDL, 1
-instance = comp, \HEX0[4]~output\, HEX0[4]~output, DisplayDemoVHDL, 1
-instance = comp, \HEX0[5]~output\, HEX0[5]~output, DisplayDemoVHDL, 1
-instance = comp, \HEX0[6]~output\, HEX0[6]~output, DisplayDemoVHDL, 1
-instance = comp, \SW[0]~input\, SW[0]~input, DisplayDemoVHDL, 1
-instance = comp, \SW[1]~input\, SW[1]~input, DisplayDemoVHDL, 1
-instance = comp, \SW[2]~input\, SW[2]~input, DisplayDemoVHDL, 1
-instance = comp, \SW[3]~input\, SW[3]~input, DisplayDemoVHDL, 1
-instance = comp, \KEY[0]~input\, KEY[0]~input, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n~6\, system_core|decOut_n~6, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n~7\, system_core|decOut_n~7, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n~8\, system_core|decOut_n~8, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n~9\, system_core|decOut_n~9, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n~10\, system_core|decOut_n~10, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n~11\, system_core|decOut_n~11, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n[3]~2\, system_core|decOut_n[3]~2, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n[3]~16\, system_core|decOut_n[3]~16, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n~12\, system_core|decOut_n~12, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n~13\, system_core|decOut_n~13, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n~14\, system_core|decOut_n~14, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n~15\, system_core|decOut_n~15, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n[6]~5\, system_core|decOut_n[6]~5, DisplayDemoVHDL, 1
-instance = comp, \system_core|decOut_n[6]~17\, system_core|decOut_n[6]~17, DisplayDemoVHDL, 1
-instance = comp, \KEY[1]~input\, KEY[1]~input, DisplayDemoVHDL, 1
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1.vhd.bak b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1.vhd.bak
deleted file mode 100644
index ba2d901..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1.vhd.bak
+++ /dev/null
@@ -1,4 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity Mux2_1 is
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1Demo.qpf b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1Demo.qpf
deleted file mode 100644
index 0842c64..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1Demo.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 21:28:47 March 07, 2023
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "20.1"
-DATE = "21:28:47 March 07, 2023"
-
-# Revisions
-
-PROJECT_REVISION = "Mux2_1Demo"
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1Demo.qsf b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1Demo.qsf
deleted file mode 100644
index eb52759..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1Demo.qsf
+++ /dev/null
@@ -1,583 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 21:28:47 March 07, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# Mux2_1Demo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY Mux2_1
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:28:47 MARCH 07, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VHDL_FILE Mux2_1.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE Mux2_1.vwf
-set_global_assignment -name BDF_FILE Mux2_1Demo.bdf
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1Demo.qsf.bak b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1Demo.qsf.bak
deleted file mode 100644
index dae1dc7..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1Demo.qsf.bak
+++ /dev/null
@@ -1,64 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 21:28:47 March 07, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# Mux2_1Demo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY Mux2_1Demo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:28:47 MARCH 07, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VHDL_FILE Mux2_1.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE Mux2_1.vwf
-set_global_assignment -name BDF_FILE Mux2_1Demo.bdf
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1Demo.qws b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1Demo.qws
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.(0).cnf.cdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.(0).cnf.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.(0).cnf.hdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.(0).cnf.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.(1).cnf.cdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.(1).cnf.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.(1).cnf.hdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.(1).cnf.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.asm.qmsg b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.asm.qmsg
deleted file mode 100644
index c2fbdd1..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.asm.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678227226957 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227226957 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 22:13:46 2023 " "Processing started: Tue Mar 7 22:13:46 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678227226957 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678227226957 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Mux2_1Demo -c Mux2_1Demo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Mux2_1Demo -c Mux2_1Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678227226957 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678227227081 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678227228548 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678227228621 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "365 " "Peak virtual memory: 365 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678227228804 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 22:13:48 2023 " "Processing ended: Tue Mar 7 22:13:48 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678227228804 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678227228804 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678227228804 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678227228804 ""}
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.asm.rdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.asm.rdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.asm_labs.ddb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.asm_labs.ddb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cbx.xml b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cbx.xml
deleted file mode 100644
index 926b79e..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp.bpm b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp.bpm
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp.cdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp.hdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp.idb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp.idb
deleted file mode 100644
index bc2c2aa..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp.logdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp.logdb
deleted file mode 100644
index 6a52aa0..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp.logdb
+++ /dev/null
@@ -1,46 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;4;4;0;0;4;4;0;0;0;0;0;0;1;0;0;0;3;1;0;3;0;0;1;0;4;4;4;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,4;0;0;4;4;0;0;4;4;4;4;4;4;3;4;4;4;1;3;4;1;4;4;3;4;0;0;0;4;4,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,LEDG[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp.rdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp.rdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp_merge.kpt b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cmp_merge.kpt
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.db_info b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.db_info
deleted file mode 100644
index f9d1c20..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Wed Mar 8 09:48:15 2023
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.eda.qmsg b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.eda.qmsg
deleted file mode 100644
index 9991fb8..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.eda.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678268911921 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2020 Intel Corporation. All rights reserved. " "Copyright (C) 2020 Intel Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions " "Your use of Intel Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and any partner logic " "and other software and tools, and any partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License " "to the terms and conditions of the Intel Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel FPGA IP License Agreement, or other applicable license " "the Intel FPGA IP License Agreement, or other applicable license" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement, including, without limitation, that your use is for " "agreement, including, without limitation, that your use is for" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the sole purpose of programming logic devices manufactured by " "the sole purpose of programming logic devices manufactured by" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Intel and sold by Intel or its authorized distributors. Please " "Intel and sold by Intel or its authorized distributors. Please" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "refer to the applicable agreement for further details, at " "refer to the applicable agreement for further details, at" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "https://fpgasoftware.intel.com/eula. " "https://fpgasoftware.intel.com/eula." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 09:48:31 2023 " "Processing started: Wed Mar 8 09:48:31 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678268911921 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht " "Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678268911922 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678268912094 ""}
-{ "Error" "EQNETO_INVALID_TESTBENCH_OUTPUT_PATH" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht " "HDL output file name \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht\" used with --testbench_file option contains a non-existent directory path" { } { } 0 199013 "HDL output file name \"%1!s!\" used with --testbench_file option contains a non-existent directory path" 0 0 "EDA Netlist Writer" 0 -1 1678268912095 ""}
-{ "Error" "EQNETO_INVALID_TESTBENCH_INPUT_PATH" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf " "Vector source file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf specified with --testbench_vector_input_file option does not exist" { } { } 0 199014 "Vector source file %1!s! specified with --testbench_vector_input_file option does not exist" 0 0 "EDA Netlist Writer" 0 -1 1678268912095 ""}
-{ "Error" "EQEXE_ERROR_COUNT" "EDA Netlist Writer 2 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "608 " "Peak virtual memory: 608 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678268912108 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Mar 8 09:48:32 2023 " "Processing ended: Wed Mar 8 09:48:32 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678268912108 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678268912108 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678268912108 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678268912108 ""}
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.fit.qmsg b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.fit.qmsg
deleted file mode 100644
index abd1331..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.fit.qmsg
+++ /dev/null
@@ -1,48 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678227221001 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678227221001 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "Mux2_1Demo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"Mux2_1Demo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678227221003 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678227221052 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678227221052 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678227221271 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678227221274 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678227221308 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678227221308 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678227221308 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678227221308 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678227221308 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678227221308 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678227221308 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678227221308 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678227221308 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678227221308 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/" { { 0 { 0 ""} 0 573 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678227221310 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/" { { 0 { 0 ""} 0 575 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678227221310 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/" { { 0 { 0 ""} 0 577 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678227221310 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/" { { 0 { 0 ""} 0 579 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678227221310 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/" { { 0 { 0 ""} 0 581 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678227221310 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678227221310 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678227221311 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Mux2_1Demo.sdc " "Synopsys Design Constraints File file not found: 'Mux2_1Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678227221778 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678227221779 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678227221779 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678227221779 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678227221780 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678227221780 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678227221780 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678227221781 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678227221781 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678227221781 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678227221782 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678227221782 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678227221782 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678227221782 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678227221782 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678227221782 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678227221782 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678227221782 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678227221791 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678227221791 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678227221798 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678227221800 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678227223200 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678227223269 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678227223295 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678227223437 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678227223437 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678227223549 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y12 X115_Y23 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23"} { { 12 { 0 ""} 104 12 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678227225482 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678227225482 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678227225586 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678227225586 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678227225586 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678227225587 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678227225658 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678227225663 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678227225808 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678227225808 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678227225944 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678227226159 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678227226321 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/output_files/Mux2_1Demo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/output_files/Mux2_1Demo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678227226354 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 522 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 522 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1148 " "Peak virtual memory: 1148 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678227226471 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 22:13:46 2023 " "Processing ended: Tue Mar 7 22:13:46 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678227226471 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678227226471 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678227226471 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678227226471 ""}
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.hier_info b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.hier_info
deleted file mode 100644
index 2bea375..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.hier_info
+++ /dev/null
@@ -1,14 +0,0 @@
-|Mux2_1Demo
-LEDG[0] <= Mux2_1:inst.dataOut
-SW[0] => Mux2_1:inst.dataIn0
-SW[1] => Mux2_1:inst.dataIn1
-KEY[0] => Mux2_1:inst.sel
-
-
-|Mux2_1Demo|Mux2_1:inst
-dataIn0 => dataOut.DATAB
-dataIn1 => dataOut.DATAA
-sel => dataOut.OUTPUTSELECT
-dataOut <= dataOut.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.hif b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.hif
deleted file mode 100644
index c5daeff..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.lpc.html b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.lpc.html
deleted file mode 100644
index b14705f..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.lpc.html
+++ /dev/null
@@ -1,34 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| inst |
-3 |
-0 |
-0 |
-0 |
-1 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.lpc.rdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.lpc.rdb
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index b705227..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.lpc.txt b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.lpc.txt
deleted file mode 100644
index 7e6b718..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.lpc.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; inst ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.ammdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.ammdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.bpm b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.bpm
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.cdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.hdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.kpt b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.kpt
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.logdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.qmsg b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.qmsg
deleted file mode 100644
index 1486f95..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.qmsg
+++ /dev/null
@@ -1,13 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678227215091 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227215092 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 22:13:35 2023 " "Processing started: Tue Mar 7 22:13:35 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678227215092 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678227215092 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Mux2_1Demo -c Mux2_1Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off Mux2_1Demo -c Mux2_1Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678227215092 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678227215218 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678227215218 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mux2_1.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Mux2_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Mux2_1-Behavioral " "Found design unit 1: Mux2_1-Behavioral" { } { { "Mux2_1.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678227219814 ""} { "Info" "ISGN_ENTITY_NAME" "1 Mux2_1 " "Found entity 1: Mux2_1" { } { { "Mux2_1.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678227219814 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678227219814 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mux2_1Demo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Mux2_1Demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Mux2_1Demo " "Found entity 1: Mux2_1Demo" { } { { "Mux2_1Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1Demo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678227219814 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678227219814 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "Mux2_1Demo " "Elaborating entity \"Mux2_1Demo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678227219839 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Mux2_1 Mux2_1:inst " "Elaborating entity \"Mux2_1\" for hierarchy \"Mux2_1:inst\"" { } { { "Mux2_1Demo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1Demo.bdf" { { 192 480 640 304 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678227219840 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678227220171 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678227220468 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678227220468 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "5 " "Implemented 5 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678227220482 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678227220482 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678227220482 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678227220482 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "431 " "Peak virtual memory: 431 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678227220485 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 22:13:40 2023 " "Processing ended: Tue Mar 7 22:13:40 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678227220485 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678227220485 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678227220485 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678227220485 ""}
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.rdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map.rdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map_bb.cdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map_bb.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map_bb.hdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map_bb.hdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map_bb.logdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.pre_map.hdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.routing.rdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.rtlv.hdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.sld_design_entry.sci b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.smart_action.txt b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.smart_action.txt
deleted file mode 100644
index 11b531f..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-SOURCE
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.sta.qmsg b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.sta.qmsg
deleted file mode 100644
index f5fd627..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678227229266 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227229267 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 22:13:49 2023 " "Processing started: Tue Mar 7 22:13:49 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678227229267 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678227229267 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Mux2_1Demo -c Mux2_1Demo " "Command: quartus_sta Mux2_1Demo -c Mux2_1Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678227229267 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678227229288 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678227229346 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678227229346 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678227229394 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678227229394 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Mux2_1Demo.sdc " "Synopsys Design Constraints File file not found: 'Mux2_1Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678227229705 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678227229706 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678227229706 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678227229706 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678227229706 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678227229706 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678227229706 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678227229709 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678227229710 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229710 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229712 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229712 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229712 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229713 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229713 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678227229715 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678227229733 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678227229889 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678227229900 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678227229900 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678227229900 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678227229900 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229900 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229901 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229901 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229902 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229902 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229902 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678227229903 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678227229942 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678227229942 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678227229942 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678227229942 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229943 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229943 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229943 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229944 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678227229944 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678227230154 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678227230155 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "536 " "Peak virtual memory: 536 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678227230163 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 22:13:50 2023 " "Processing ended: Tue Mar 7 22:13:50 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678227230163 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678227230163 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678227230163 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678227230163 ""}
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.sta.rdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.sta.rdb
deleted file mode 100644
index fe0bf54..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.sta_cmp.7_slow_1200mv_85c.tdb
deleted file mode 100644
index a4d2e93..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.tis_db_list.ddb
deleted file mode 100644
index 73e5ec9..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index 68f9e6b..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index d984e46..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index b42264a..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.vpr.ammdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.vpr.ammdb
deleted file mode 100644
index c28efb4..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo_partition_pins.json b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo_partition_pins.json
deleted file mode 100644
index ac71659..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/Mux2_1Demo_partition_pins.json
+++ /dev/null
@@ -1,25 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "LEDG[0]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- },
- {
- "name" : "KEY[0]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/prev_cmp_Mux2_1Demo.qmsg b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/prev_cmp_Mux2_1Demo.qmsg
deleted file mode 100644
index d8a4fe1..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/db/prev_cmp_Mux2_1Demo.qmsg
+++ /dev/null
@@ -1,10 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678226734293 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678226734293 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 22:05:34 2023 " "Processing started: Tue Mar 7 22:05:34 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678226734293 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678226734293 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Mux2_1Demo -c Mux2_1Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off Mux2_1Demo -c Mux2_1Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678226734293 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678226734384 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678226734384 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mux2_1.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Mux2_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Mux2_1-Behavioral " "Found design unit 1: Mux2_1-Behavioral" { } { { "Mux2_1.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/part2/Mux2_1.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678226739144 ""} { "Info" "ISGN_ENTITY_NAME" "1 Mux2_1 " "Found entity 1: Mux2_1" { } { { "Mux2_1.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/part2/Mux2_1.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678226739144 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678226739144 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mux2_1Demo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Mux2_1Demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Mux2_1Demo " "Found entity 1: Mux2_1Demo" { } { { "Mux2_1Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/part2/Mux2_1Demo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678226739144 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678226739144 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "Mux2_1Demo " "Elaborating entity \"Mux2_1Demo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678226739172 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Mux2_1 Mux2_1:inst " "Elaborating entity \"Mux2_1\" for hierarchy \"Mux2_1:inst\"" { } { { "Mux2_1Demo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/part2/Mux2_1Demo.bdf" { { 192 480 640 304 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678226739174 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678226739517 ""}
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/README b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.db_info b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.db_info
deleted file mode 100644
index 7399f6c..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Tue Mar 7 21:48:07 2023
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.ammdb
deleted file mode 100644
index 38fe574..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.cdb
deleted file mode 100644
index 7ec919b..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.dfp and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.hdb
deleted file mode 100644
index a57bd9f..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.rcfdb
deleted file mode 100644
index 8ed4eed..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.cmp.rcfdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.cdb
deleted file mode 100644
index 9c2afce..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.dpi
deleted file mode 100644
index 40b404f..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.dpi and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hbdb.cdb
deleted file mode 100644
index 9045b84..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hbdb.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hbdb.hdb
deleted file mode 100644
index 3b6599d..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hdb
deleted file mode 100644
index 14f8798..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.kpt
deleted file mode 100644
index f26ec8a..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.root_partition.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.rrp.hdb b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.rrp.hdb
deleted file mode 100644
index 2641b6f..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/incremental_db/compiled_partitions/Mux2_1Demo.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.asm.rpt b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.asm.rpt
deleted file mode 100644
index b92be29..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for Mux2_1Demo
-Tue Mar 7 22:13:48 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: Mux2_1Demo.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Tue Mar 7 22:13:48 2023 ;
-; Revision Name ; Mux2_1Demo ;
-; Top-level Entity Name ; Mux2_1Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+--------------------------------------------------------------------------------------------------+
-; File Name ;
-+--------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/output_files/Mux2_1Demo.sof ;
-+--------------------------------------------------------------------------------------------------+
-
-
-+------------------------------------------+
-; Assembler Device Options: Mux2_1Demo.sof ;
-+----------------+-------------------------+
-; Option ; Setting ;
-+----------------+-------------------------+
-; JTAG usercode ; 0x005631B5 ;
-; Checksum ; 0x005631B5 ;
-+----------------+-------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 22:13:46 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Mux2_1Demo -c Mux2_1Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 365 megabytes
- Info: Processing ended: Tue Mar 7 22:13:48 2023
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.done b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.done
deleted file mode 100644
index acea63d..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.done
+++ /dev/null
@@ -1 +0,0 @@
-Tue Mar 7 22:14:00 2023
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.eda.rpt b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.eda.rpt
deleted file mode 100644
index def02d4..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.eda.rpt
+++ /dev/null
@@ -1,76 +0,0 @@
-EDA Netlist Writer report for Mux2_1Demo
-Wed Mar 8 09:48:32 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+-----------------------------------+
-; EDA Netlist Writer Status ; Failed - Wed Mar 8 09:48:32 2023 ;
-; Revision Name ; Mux2_1Demo ;
-; Top-level Entity Name ; Mux2_1Demo ;
-; Family ; Cyclone IV E ;
-+---------------------------+-----------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
- Info: Your use of Intel Corporation's design tools, logic functions
- Info: and other software and tools, and any partner logic
- Info: functions, and any output files from any of the foregoing
- Info: (including device programming or simulation files), and any
- Info: associated documentation or information are expressly subject
- Info: to the terms and conditions of the Intel Program License
- Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
- Info: the Intel FPGA IP License Agreement, or other applicable license
- Info: agreement, including, without limitation, that your use is for
- Info: the sole purpose of programming logic devices manufactured by
- Info: Intel and sold by Intel or its authorized distributors. Please
- Info: refer to the applicable agreement for further details, at
- Info: https://fpgasoftware.intel.com/eula.
- Info: Processing started: Wed Mar 8 09:48:31 2023
-Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Error (199013): HDL output file name "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht" used with --testbench_file option contains a non-existent directory path
-Error (199014): Vector source file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf specified with --testbench_vector_input_file option does not exist
-Error: Quartus Prime EDA Netlist Writer was unsuccessful. 2 errors, 1 warning
- Error: Peak virtual memory: 608 megabytes
- Error: Processing ended: Wed Mar 8 09:48:32 2023
- Error: Elapsed time: 00:00:01
- Error: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.fit.rpt b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.fit.rpt
deleted file mode 100644
index c6f47e2..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.fit.rpt
+++ /dev/null
@@ -1,2507 +0,0 @@
-Fitter report for Mux2_1Demo
-Tue Mar 7 22:13:46 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Tue Mar 7 22:13:46 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; Mux2_1Demo ;
-; Top-level Entity Name ; Mux2_1Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 1 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 1 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 4 / 529 ( < 1 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; CLOCK_50 ; PIN_Y2 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
-; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
-; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
-; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
-; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
-; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
-; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[1] ; PIN_M21 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
-; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
-; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[0] ; PIN_G19 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[1] ; PIN_F19 ; QSF Assignment ;
-; Location ; ; ; LEDR[2] ; PIN_E19 ; QSF Assignment ;
-; Location ; ; ; LEDR[3] ; PIN_F21 ; QSF Assignment ;
-; Location ; ; ; LEDR[4] ; PIN_F18 ; QSF Assignment ;
-; Location ; ; ; LEDR[5] ; PIN_E18 ; QSF Assignment ;
-; Location ; ; ; LEDR[6] ; PIN_J19 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_H19 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; SW[10] ; PIN_AC24 ; QSF Assignment ;
-; Location ; ; ; SW[11] ; PIN_AB24 ; QSF Assignment ;
-; Location ; ; ; SW[12] ; PIN_AB23 ; QSF Assignment ;
-; Location ; ; ; SW[13] ; PIN_AA24 ; QSF Assignment ;
-; Location ; ; ; SW[14] ; PIN_AA23 ; QSF Assignment ;
-; Location ; ; ; SW[15] ; PIN_AA22 ; QSF Assignment ;
-; Location ; ; ; SW[16] ; PIN_Y24 ; QSF Assignment ;
-; Location ; ; ; SW[17] ; PIN_Y23 ; QSF Assignment ;
-; Location ; ; ; SW[2] ; PIN_AC27 ; QSF Assignment ;
-; Location ; ; ; SW[3] ; PIN_AD27 ; QSF Assignment ;
-; Location ; ; ; SW[4] ; PIN_AB27 ; QSF Assignment ;
-; Location ; ; ; SW[5] ; PIN_AC26 ; QSF Assignment ;
-; Location ; ; ; SW[6] ; PIN_AD26 ; QSF Assignment ;
-; Location ; ; ; SW[7] ; PIN_AB26 ; QSF Assignment ;
-; Location ; ; ; SW[8] ; PIN_AC25 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AB25 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 20 ) ; 0.00 % ( 0 / 20 ) ; 0.00 % ( 0 / 20 ) ;
-; -- Achieved ; 0.00 % ( 0 / 20 ) ; 0.00 % ( 0 / 20 ) ; 0.00 % ( 0 / 20 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/output_files/Mux2_1Demo.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+-----------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-----------------------+
-; Total logic elements ; 1 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 1 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 1 ;
-; -- <=2 input functions ; 0 ;
-; -- Register only ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers* ; 0 / 117,053 ( 0 % ) ;
-; -- Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 1 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 4 / 529 ( < 1 % ) ;
-; -- Clock pins ; 0 / 7 ( 0 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.1% / 0.0% / 0.2% ;
-; Maximum fan-out ; 1 ;
-; Highest non-global fan-out ; 1 ;
-; Total fan-out ; 13 ;
-; Average fan-out ; 0.68 ;
-+---------------------------------------------+-----------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 1 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 1 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 0 ; 0 ;
-; -- 3 input functions ; 1 ; 0 ;
-; -- <=2 input functions ; 0 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 1 ; 0 ;
-; -- arithmetic mode ; 0 ; 0 ;
-; ; ; ;
-; Total registers ; 0 ; 0 ;
-; -- Dedicated logic registers ; 0 / 114480 ( 0 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 1 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 4 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 8 ; 5 ;
-; -- Registered Connections ; 0 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 3 ; 0 ;
-; -- Output Ports ; 1 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; KEY[0] ; M23 ; 6 ; 115 ; 40 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; LEDG[0] ; E21 ; 7 ; 107 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+----------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+----------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+----------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 0 / 63 ( 0 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 2 / 65 ( 3 % ) ; 2.5V ; -- ;
-; 6 ; 2 / 58 ( 3 % ) ; 2.5V ; -- ;
-; 7 ; 1 / 72 ( 1 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+----------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA23 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA24 ; 279 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB24 ; 274 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB25 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB26 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB27 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC25 ; 272 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC26 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC27 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD27 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; LEDG[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y24 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; LEDG[0] ; Incomplete set of assignments ;
-; SW[1] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-; KEY[0] ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+-------------+--------------+
-; |Mux2_1Demo ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |Mux2_1Demo ; Mux2_1Demo ; work ;
-; |Mux2_1:inst| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |Mux2_1Demo|Mux2_1:inst ; Mux2_1 ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-----------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; LEDG[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[1] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; KEY[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+------------------------------+-------------------+---------+
-; SW[1] ; ; ;
-; - Mux2_1:inst|dataOut~0 ; 1 ; 6 ;
-; SW[0] ; ; ;
-; - Mux2_1:inst|dataOut~0 ; 0 ; 6 ;
-; KEY[0] ; ; ;
-; - Mux2_1:inst|dataOut~0 ; 1 ; 6 ;
-+------------------------------+-------------------+---------+
-
-
-+------------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+------------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+------------------------+
-; Block interconnects ; 4 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 1 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 17 / 209,544 ( < 1 % ) ;
-; Direct links ; 0 / 342,891 ( 0 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 0 / 119,088 ( 0 % ) ;
-; R24 interconnects ; 1 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 2 / 289,782 ( < 1 % ) ;
-+-----------------------+------------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 1.00) ; Number of LABs (Total = 1) ;
-+--------------------------------------------+-----------------------------+
-; 1 ; 1 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-+--------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 1.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 1) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 1 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 3.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 4 ; 4 ; 0 ; 0 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 3 ; 1 ; 0 ; 3 ; 0 ; 0 ; 1 ; 0 ; 4 ; 4 ; 4 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 4 ; 0 ; 0 ; 4 ; 4 ; 0 ; 0 ; 4 ; 4 ; 4 ; 4 ; 4 ; 4 ; 3 ; 4 ; 4 ; 4 ; 1 ; 3 ; 4 ; 1 ; 4 ; 4 ; 3 ; 4 ; 0 ; 0 ; 0 ; 4 ; 4 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; LEDG[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "Mux2_1Demo"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'Mux2_1Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/output_files/Mux2_1Demo.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 522 warnings
- Info: Peak virtual memory: 1148 megabytes
- Info: Processing ended: Tue Mar 7 22:13:46 2023
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:09
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/output_files/Mux2_1Demo.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.fit.smsg b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.fit.summary b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.fit.summary
deleted file mode 100644
index 3dbcf57..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Tue Mar 7 22:13:46 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : Mux2_1Demo
-Top-level Entity Name : Mux2_1Demo
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 1 / 114,480 ( < 1 % )
- Total combinational functions : 1 / 114,480 ( < 1 % )
- Dedicated logic registers : 0 / 114,480 ( 0 % )
-Total registers : 0
-Total pins : 4 / 529 ( < 1 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.flow.rpt b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.flow.rpt
deleted file mode 100644
index 716b53a..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.flow.rpt
+++ /dev/null
@@ -1,149 +0,0 @@
-Flow report for Mux2_1Demo
-Wed Mar 8 09:48:32 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+------------------------------------------------------+
-; Flow Status ; EDA Netlist Writer Failed - Wed Mar 8 09:48:32 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; Mux2_1Demo ;
-; Top-level Entity Name ; Mux2_1Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 1 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 1 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 4 / 529 ( < 1 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+------------------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/07/2023 22:13:35 ;
-; Main task ; Compilation ;
-; Revision Name ; Mux2_1Demo ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 2690080394329.167822721516887 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 431 MB ; 00:00:12 ;
-; Fitter ; 00:00:06 ; 1.0 ; 1148 MB ; 00:00:09 ;
-; Assembler ; 00:00:02 ; 1.0 ; 365 MB ; 00:00:02 ;
-; Timing Analyzer ; 00:00:01 ; 1.0 ; 536 MB ; 00:00:01 ;
-; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 612 MB ; 00:00:00 ;
-; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 608 MB ; 00:00:00 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 611 MB ; 00:00:00 ;
-; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 608 MB ; 00:00:00 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 611 MB ; 00:00:00 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 608 MB ; 00:00:00 ;
-; Total ; 00:00:17 ; -- ; -- ; 00:00:24 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off Mux2_1Demo -c Mux2_1Demo
-quartus_fit --read_settings_files=off --write_settings_files=off Mux2_1Demo -c Mux2_1Demo
-quartus_asm --read_settings_files=off --write_settings_files=off Mux2_1Demo -c Mux2_1Demo
-quartus_sta Mux2_1Demo -c Mux2_1Demo
-quartus_eda --read_settings_files=off --write_settings_files=off Mux2_1Demo -c Mux2_1Demo
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht
-quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/ Mux2_1Demo -c Mux2_1Demo
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht
-quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/ Mux2_1Demo -c Mux2_1Demo
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.jdi b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.jdi
deleted file mode 100644
index da05b52..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.map.rpt b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.map.rpt
deleted file mode 100644
index 6b016a4..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.map.rpt
+++ /dev/null
@@ -1,287 +0,0 @@
-Analysis & Synthesis report for Mux2_1Demo
-Tue Mar 7 22:13:40 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Post-Synthesis Netlist Statistics for Top Partition
- 10. Elapsed Time Per Partition
- 11. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Tue Mar 7 22:13:40 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; Mux2_1Demo ;
-; Top-level Entity Name ; Mux2_1Demo ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 1 ;
-; Total combinational functions ; 1 ;
-; Dedicated logic registers ; 0 ;
-; Total registers ; 0 ;
-; Total pins ; 4 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; Mux2_1Demo ; Mux2_1Demo ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------------+---------+
-; Mux2_1.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vhd ; ;
-; Mux2_1Demo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1Demo.bdf ; ;
-+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------------+---------+
-
-
-+---------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+-----------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-----------------------+
-; Estimated Total logic elements ; 1 ;
-; ; ;
-; Total combinational functions ; 1 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 1 ;
-; -- <=2 input functions ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers ; 0 ;
-; -- Dedicated logic registers ; 0 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 4 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; Mux2_1:inst|dataOut~0 ;
-; Maximum fan-out ; 1 ;
-; Total fan-out ; 8 ;
-; Average fan-out ; 0.89 ;
-+---------------------------------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+-------------+--------------+
-; |Mux2_1Demo ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; |Mux2_1Demo ; Mux2_1Demo ; work ;
-; |Mux2_1:inst| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Mux2_1Demo|Mux2_1:inst ; Mux2_1 ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 0 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 4 ;
-; cycloneiii_lcell_comb ; 1 ;
-; normal ; 1 ;
-; 3 data inputs ; 1 ;
-; ; ;
-; Max LUT depth ; 1.00 ;
-; Average LUT depth ; 1.00 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 22:13:35 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Mux2_1Demo -c Mux2_1Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 2 design units, including 1 entities, in source file Mux2_1.vhd
- Info (12022): Found design unit 1: Mux2_1-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vhd Line: 14
- Info (12023): Found entity 1: Mux2_1 File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vhd Line: 4
-Info (12021): Found 1 design units, including 1 entities, in source file Mux2_1Demo.bdf
- Info (12023): Found entity 1: Mux2_1Demo
-Info (12127): Elaborating entity "Mux2_1Demo" for the top level hierarchy
-Info (12128): Elaborating entity "Mux2_1" for hierarchy "Mux2_1:inst"
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 5 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 3 input pins
- Info (21059): Implemented 1 output pins
- Info (21061): Implemented 1 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 431 megabytes
- Info: Processing ended: Tue Mar 7 22:13:40 2023
- Info: Elapsed time: 00:00:05
- Info: Total CPU time (on all processors): 00:00:12
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.map.summary b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.map.summary
deleted file mode 100644
index 36add4d..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Tue Mar 7 22:13:40 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : Mux2_1Demo
-Top-level Entity Name : Mux2_1Demo
-Family : Cyclone IV E
-Total logic elements : 1
- Total combinational functions : 1
- Dedicated logic registers : 0
-Total registers : 0
-Total pins : 4
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.pin b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.pin
deleted file mode 100644
index b9b5204..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "Mux2_1Demo" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5 :
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 5 :
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7 :
-VCCIO7 : E20 : power : : 2.5V : 7 :
-LEDG[0] : E21 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
-VCCIO7 : E23 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7 :
-GND : F20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
-VCCIO7 : H18 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7 :
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6 :
-MSEL2 : M22 : : : : 6 :
-KEY[0] : M23 : input : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-GND+ : Y2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.sld b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.sta.rpt b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.sta.rpt
deleted file mode 100644
index e5f1ce2..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.sta.rpt
+++ /dev/null
@@ -1,434 +0,0 @@
-Timing Analyzer report for Mux2_1Demo
-Tue Mar 7 22:13:50 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Unconstrained Input Ports
- 37. Unconstrained Output Ports
- 38. Unconstrained Input Ports
- 39. Unconstrained Output Ports
- 40. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; Mux2_1Demo ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.1% ;
-+----------------------------+-------------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 3 ; 3 ;
-; Unconstrained Input Port Paths ; 3 ; 3 ;
-; Unconstrained Output Ports ; 1 ; 1 ;
-; Unconstrained Output Port Paths ; 3 ; 3 ;
-+---------------------------------+-------+------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 22:13:49 2023
-Info: Command: quartus_sta Mux2_1Demo -c Mux2_1Demo
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'Mux2_1Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 536 megabytes
- Info: Processing ended: Tue Mar 7 22:13:50 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.sta.summary b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.sta.summary
deleted file mode 100644
index aa5b327..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/modelsim/Mux2_1Demo.sft b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/modelsim/Mux2_1Demo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/modelsim/Mux2_1Demo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/modelsim/Mux2_1Demo.vho b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/modelsim/Mux2_1Demo.vho
deleted file mode 100644
index 6dd4dee..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/modelsim/Mux2_1Demo.vho
+++ /dev/null
@@ -1,197 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/07/2023 22:14:00"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY Mux2_1Demo IS
- PORT (
- LEDG : OUT std_logic_vector(0 DOWNTO 0);
- SW : IN std_logic_vector(1 DOWNTO 0);
- KEY : IN std_logic_vector(0 DOWNTO 0)
- );
-END Mux2_1Demo;
-
--- Design Ports Information
--- LEDG[0] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF Mux2_1Demo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDG : std_logic_vector(0 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(1 DOWNTO 0);
-SIGNAL ww_KEY : std_logic_vector(0 DOWNTO 0);
-SIGNAL \LEDG[0]~output_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \KEY[0]~input_o\ : std_logic;
-SIGNAL \inst|dataOut~0_combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-LEDG <= ww_LEDG;
-ww_SW <= SW;
-ww_KEY <= KEY;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X107_Y73_N9
-\LEDG[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|dataOut~0_combout\,
- devoe => ww_devoe,
- o => \LEDG[0]~output_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y40_N8
-\KEY[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY(0),
- o => \KEY[0]~input_o\);
-
--- Location: LCCOMB_X114_Y17_N8
-\inst|dataOut~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|dataOut~0_combout\ = (\KEY[0]~input_o\ & ((\SW[1]~input_o\))) # (!\KEY[0]~input_o\ & (\SW[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000011001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- datad => \KEY[0]~input_o\,
- combout => \inst|dataOut~0_combout\);
-
-ww_LEDG(0) <= \LEDG[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/modelsim/Mux2_1Demo_modelsim.xrf b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/modelsim/Mux2_1Demo_modelsim.xrf
deleted file mode 100644
index 7baee24..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/modelsim/Mux2_1Demo_modelsim.xrf
+++ /dev/null
@@ -1,16 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1Demo.bdf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/db/Mux2_1Demo.cbx.xml
-design_name = hard_block
-design_name = Mux2_1Demo
-instance = comp, \LEDG[0]~output\, LEDG[0]~output, Mux2_1Demo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, Mux2_1Demo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, Mux2_1Demo, 1
-instance = comp, \KEY[0]~input\, KEY[0]~input, Mux2_1Demo, 1
-instance = comp, \inst|dataOut~0\, inst|dataOut~0, Mux2_1Demo, 1
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1.vwf.vht b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1.vwf.vht
deleted file mode 100644
index 2882285..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1.vwf.vht
+++ /dev/null
@@ -1,55 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- *****************************************************************************
--- This file contains a Vhdl test bench with test vectors .The test vectors
--- are exported from a vector file in the Quartus Waveform Editor and apply to
--- the top level entity of the current Quartus project .The user can use this
--- testbench to simulate his design using a third-party simulation tool .
--- *****************************************************************************
--- Generated on "03/07/2023 22:14:31"
-
--- Vhdl Test Bench(with test vectors) for design : Mux2_1Demo
---
--- Simulation tool : 3rd Party
---
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY Mux2_1Demo_vhd_vec_tst IS
-END Mux2_1Demo_vhd_vec_tst;
-ARCHITECTURE Mux2_1Demo_arch OF Mux2_1Demo_vhd_vec_tst IS
--- constants
--- signals
-SIGNAL KEY : STD_LOGIC_VECTOR(0 DOWNTO 0);
-SIGNAL LEDG : STD_LOGIC_VECTOR(0 DOWNTO 0);
-SIGNAL SW : STD_LOGIC_VECTOR(1 DOWNTO 0);
-COMPONENT Mux2_1Demo
- PORT (
- KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- LEDG : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- SW : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
- );
-END COMPONENT;
-BEGIN
- i1 : Mux2_1Demo
- PORT MAP (
--- list connections between master ports and signals
- KEY => KEY,
- LEDG => LEDG,
- SW => SW
- );
-END Mux2_1Demo_arch;
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo.do b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo.do
deleted file mode 100644
index d517e1f..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo.do
+++ /dev/null
@@ -1,18 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vcom -work work Mux2_1Demo.vho
-vcom -work work Mux2_1.vwf.vht
-vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux2_1Demo_vhd_vec_tst
-vcd file -direction Mux2_1Demo.msim.vcd
-vcd add -internal Mux2_1Demo_vhd_vec_tst/*
-vcd add -internal Mux2_1Demo_vhd_vec_tst/i1/*
-proc simTimestamp {} {
- echo "Simulation time: $::now ps"
- if { [string equal running [runStatus]] } {
- after 2500 simTimestamp
- }
-}
-after 2500 simTimestamp
-run -all
-quit -f
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo.msim.vcd b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo.msim.vcd
deleted file mode 100644
index 38e0e95..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo.msim.vcd
+++ /dev/null
@@ -1,68 +0,0 @@
-$comment
- File created using the following command:
- vcd file Mux2_1Demo.msim.vcd -direction
-$end
-$date
- Tue Mar 7 22:14:32 2023
-$end
-$version
- ModelSim Version 2020.1
-$end
-$timescale
- 1ps
-$end
-
-$scope module mux2_1demo_vhd_vec_tst $end
-$var wire 1 ! KEY [0] $end
-$var wire 1 " LEDG [0] $end
-$var wire 1 # SW [1] $end
-$var wire 1 $ SW [0] $end
-
-$scope module i1 $end
-$var wire 1 % gnd $end
-$var wire 1 & vcc $end
-$var wire 1 ' unknown $end
-$var wire 1 ( devoe $end
-$var wire 1 ) devclrn $end
-$var wire 1 * devpor $end
-$var wire 1 + ww_devoe $end
-$var wire 1 , ww_devclrn $end
-$var wire 1 - ww_devpor $end
-$var wire 1 . ww_LEDG [0] $end
-$var wire 1 / ww_SW [1] $end
-$var wire 1 0 ww_SW [0] $end
-$var wire 1 1 ww_KEY [0] $end
-$var wire 1 2 \LEDG[0]~output_o\ $end
-$var wire 1 3 \SW[0]~input_o\ $end
-$var wire 1 4 \SW[1]~input_o\ $end
-$var wire 1 5 \KEY[0]~input_o\ $end
-$var wire 1 6 \inst|dataOut~0_combout\ $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0%
-1&
-x'
-1(
-1)
-1*
-1+
-1,
-1-
-x2
-x3
-x4
-x5
-x6
-x.
-x/
-x0
-x1
-x!
-x"
-x#
-x$
-$end
-#1000000
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo.sft b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo.vho b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo.vho
deleted file mode 100644
index 25ef52b..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo.vho
+++ /dev/null
@@ -1,197 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/07/2023 22:14:32"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY Mux2_1Demo IS
- PORT (
- LEDG : OUT std_logic_vector(0 DOWNTO 0);
- SW : IN std_logic_vector(1 DOWNTO 0);
- KEY : IN std_logic_vector(0 DOWNTO 0)
- );
-END Mux2_1Demo;
-
--- Design Ports Information
--- LEDG[0] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF Mux2_1Demo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDG : std_logic_vector(0 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(1 DOWNTO 0);
-SIGNAL ww_KEY : std_logic_vector(0 DOWNTO 0);
-SIGNAL \LEDG[0]~output_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \KEY[0]~input_o\ : std_logic;
-SIGNAL \inst|dataOut~0_combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-LEDG <= ww_LEDG;
-ww_SW <= SW;
-ww_KEY <= KEY;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X107_Y73_N9
-\LEDG[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|dataOut~0_combout\,
- devoe => ww_devoe,
- o => \LEDG[0]~output_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y40_N8
-\KEY[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY(0),
- o => \KEY[0]~input_o\);
-
--- Location: LCCOMB_X114_Y17_N8
-\inst|dataOut~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|dataOut~0_combout\ = (\KEY[0]~input_o\ & ((\SW[1]~input_o\))) # (!\KEY[0]~input_o\ & (\SW[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000011001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[0]~input_o\,
- datac => \SW[1]~input_o\,
- datad => \KEY[0]~input_o\,
- combout => \inst|dataOut~0_combout\);
-
-ww_LEDG(0) <= \LEDG[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo_20230307215305.sim.vwf b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo_20230307215305.sim.vwf
deleted file mode 100644
index 69a5e04..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo_20230307215305.sim.vwf
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("dataIn0")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("dataIn1")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("dataOut")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("sel")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-TRANSITION_LIST("dataIn0")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("dataIn1")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- }
- }
-}
-
-TRANSITION_LIST("dataOut")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("sel")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 400.0;
- LEVEL 1 FOR 400.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn0";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn1";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "sel";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataOut";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo_20230307221405.sim.vwf b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo_20230307221405.sim.vwf
deleted file mode 100644
index ea0b018..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo_20230307221405.sim.vwf
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("dataIn0")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("dataIn1")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("dataOut")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("sel")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-TRANSITION_LIST("dataIn0")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 2;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- }
- LEVEL 0 FOR 200.0;
- }
-}
-
-TRANSITION_LIST("dataIn1")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 5;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- }
- }
-}
-
-TRANSITION_LIST("dataOut")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL X FOR 1000.0;
- }
-}
-
-TRANSITION_LIST("sel")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 400.0;
- LEVEL 1 FOR 400.0;
- }
- LEVEL 0 FOR 200.0;
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn0";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn1";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "sel";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataOut";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo_20230307221433.sim.vwf b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo_20230307221433.sim.vwf
deleted file mode 100644
index ea0b018..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo_20230307221433.sim.vwf
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("dataIn0")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("dataIn1")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("dataOut")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("sel")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-TRANSITION_LIST("dataIn0")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 2;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- }
- LEVEL 0 FOR 200.0;
- }
-}
-
-TRANSITION_LIST("dataIn1")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 5;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- }
- }
-}
-
-TRANSITION_LIST("dataOut")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL X FOR 1000.0;
- }
-}
-
-TRANSITION_LIST("sel")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 400.0;
- LEVEL 1 FOR 400.0;
- }
- LEVEL 0 FOR 200.0;
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn0";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn1";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "sel";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataOut";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo_modelsim.xrf b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo_modelsim.xrf
deleted file mode 100644
index 7baee24..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/Mux2_1Demo_modelsim.xrf
+++ /dev/null
@@ -1,16 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1Demo.bdf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/db/Mux2_1Demo.cbx.xml
-design_name = hard_block
-design_name = Mux2_1Demo
-instance = comp, \LEDG[0]~output\, LEDG[0]~output, Mux2_1Demo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, Mux2_1Demo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, Mux2_1Demo, 1
-instance = comp, \KEY[0]~input\, KEY[0]~input, Mux2_1Demo, 1
-instance = comp, \inst|dataOut~0\, inst|dataOut~0, Mux2_1Demo, 1
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/transcript
deleted file mode 100644
index 694dd80..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/transcript
+++ /dev/null
@@ -1,47 +0,0 @@
-# do Mux2_1Demo.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 22:14:32 on Mar 07,2023
-# vcom -work work Mux2_1Demo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity hard_block
-# -- Compiling architecture structure of hard_block
-# -- Compiling entity Mux2_1Demo
-# -- Compiling architecture structure of Mux2_1Demo
-# End time: 22:14:32 on Mar 07,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 22:14:32 on Mar 07,2023
-# vcom -work work Mux2_1.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity Mux2_1Demo_vhd_vec_tst
-# -- Compiling architecture Mux2_1Demo_arch of Mux2_1Demo_vhd_vec_tst
-# End time: 22:14:32 on Mar 07,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux2_1Demo_vhd_vec_tst
-# Start time: 22:14:32 on Mar 07,2023
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading work.mux2_1demo_vhd_vec_tst(mux2_1demo_arch)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading cycloneive.cycloneive_atom_pack(body)
-# Loading cycloneive.cycloneive_components
-# Loading work.mux2_1demo(structure)
-# Loading work.hard_block(structure)
-# Loading ieee.std_logic_arith(body)
-# Loading cycloneive.cycloneive_io_obuf(arch)
-# Loading cycloneive.cycloneive_io_ibuf(arch)
-# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#33
-# End time: 22:14:32 on Mar 07,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/vwf_sim_transcript
deleted file mode 100644
index 3e9db9d..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/vwf_sim_transcript
+++ /dev/null
@@ -1,84 +0,0 @@
-Determining the location of the ModelSim executable...
-
-Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
-
-To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
-Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
-
-**** Generating the ModelSim Testbench ****
-
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht"
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Mar 7 22:14:31 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vhtWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Completed successfully.
-
-**** Generating the functional simulation netlist ****
-
-quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/" Mux2_1Demo -c Mux2_1Demo
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Mar 7 22:14:31 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/ Mux2_1Demo -c Mux2_1DemoWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file Mux2_1Demo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 611 megabytes Info: Processing ended: Tue Mar 7 22:14:32 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00
-Completed successfully.
-
-**** Generating the ModelSim .do script ****
-
-/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1Demo.do generated.
-
-Completed successfully.
-
-**** Running the ModelSim simulation ****
-
-/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do Mux2_1Demo.do
-
-Reading pref.tcl
-# 2020.1
-# do Mux2_1Demo.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 22:14:32 on Mar 07,2023# vcom -work work Mux2_1Demo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity hard_block
-# -- Compiling architecture structure of hard_block
-# -- Compiling entity Mux2_1Demo
-# -- Compiling architecture structure of Mux2_1Demo
-# End time: 22:14:32 on Mar 07,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020# Start time: 22:14:32 on Mar 07,2023
-# vcom -work work Mux2_1.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164# -- Compiling entity Mux2_1Demo_vhd_vec_tst# -- Compiling architecture Mux2_1Demo_arch of Mux2_1Demo_vhd_vec_tst
-# End time: 22:14:32 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux2_1Demo_vhd_vec_tst # Start time: 22:14:32 on Mar 07,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.mux2_1demo_vhd_vec_tst(mux2_1demo_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.mux2_1demo(structure)# Loading work.hard_block(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#33
-# End time: 22:14:32 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-Completed successfully.
-
-**** Converting ModelSim VCD to vector waveform ****
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf...
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1Demo.msim.vcd...
-
-Processing channel transitions...
-
-Warning: dataIn0 - signal not found in VCD.
-
-Warning: dataIn1 - signal not found in VCD.
-
-Warning: dataOut - signal not found in VCD.
-
-Warning: sel - signal not found in VCD.
-
-Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1Demo_20230307221433.sim.vwf
-
-Finished VCD to VWF conversion.
-
-Completed successfully.
-
-All completed.
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/work/_info
deleted file mode 100644
index 4e2987a..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux2_1Demo/simulation/qsim/work/_info
+++ /dev/null
@@ -1,240 +0,0 @@
-m255
-K4
-z2
-!s11e vcom 2020.1 2020.02, Feb 28 2020
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-Z0 d/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/part2/simulation/qsim
-Ehard_block
-Z1 w1678227272
-Z2 DPx4 ieee 16 vital_primitives 0 22 G>kiXP8Q9dRClKfK1Zn7j1
-Z3 DPx10 cycloneive 20 cycloneive_atom_pack 0 22 WOh:M[al;oVzG5c`D0
-Z4 DPx4 ieee 12 vital_timing 0 22 J>EBealN09f8GzldA[z2>3
-Z5 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
-Z6 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
-Z7 DPx10 cycloneive 21 cycloneive_components 0 22 zGMDhP>8e@2k@f0emXi5[`cD`bFC`UBKA5o7W??azG@W@@eFOTF0
-!s100 [5;Wd8QGQ>@2NGoJ1I]Y43
-R12
-32
-R13
-!i10b 1
-R14
-R15
-R16
-!i113 1
-R17
-R18
-Emux2_1
-Z19 w1678225984
-R2
-R3
-R4
-R5
-R6
-R7
-!i122 0
-R0
-R9
-R10
-l0
-R11
-V[DV<0g1>9M>Uij:TMQ1of2
-!s100 Y;j9QG;eVdR8h71b5c>i@1
-R12
-32
-Z20 !s110 1678225984
-!i10b 1
-Z21 !s108 1678225984.000000
-R15
-R16
-!i113 1
-R17
-R18
-Astructure
-R2
-R3
-R4
-R5
-R6
-R7
-DEx4 work 6 mux2_1 0 22 [DV<0g1>9M>Uij:TMQ1of2
-!i122 0
-l64
-L44 88
-Vgj@oR@N46djJVLJ2oXYhi3
-!s100 ]nOzH5oh4RHPRRFA5ic9H1
-R12
-32
-R20
-!i10b 1
-R21
-R15
-R16
-!i113 1
-R17
-R18
-Emux2_1_vhd_vec_tst
-Z22 w1678225983
-R5
-R6
-!i122 1
-R0
-Z23 8Mux2_1.vwf.vht
-Z24 FMux2_1.vwf.vht
-l0
-Z25 L32 1
-V[ORYg62AM_BILSVA?UIV<3
-!s100 W1o]ga;bSNYF[;7Nj6K:?1
-R12
-32
-R20
-!i10b 1
-R21
-Z26 !s90 -work|work|Mux2_1.vwf.vht|
-Z27 !s107 Mux2_1.vwf.vht|
-!i113 1
-R17
-R18
-Amux2_1_arch
-R5
-R6
-DEx4 work 18 mux2_1_vhd_vec_tst 0 22 [ORYg62AM_BILSVA?UIV<3
-!i122 1
-l49
-L34 62
-Vl@i7^;bA9=RmRNK>UN@EK0
-!s100 P>BQU@iN:LL1^T?ToRDQ>0
-R12
-32
-R20
-!i10b 1
-R21
-R26
-R27
-!i113 1
-R17
-R18
-Emux2_1demo
-R1
-R2
-R3
-R4
-R5
-R6
-R7
-!i122 4
-R8
-R9
-R10
-l0
-L78 1
-VLZ40neQbZ?MaT1jJGiT0
-R12
-32
-R13
-!i10b 1
-R14
-R15
-R16
-!i113 1
-R17
-R18
-Emux2_1demo_vhd_vec_tst
-Z28 w1678227271
-R5
-R6
-!i122 5
-R8
-R23
-R24
-l0
-R25
-V3C=jfC[[SFE>PIho5L8i70
-!s100 ^?39^IT5@jeE^S2LT95P`3
-R12
-32
-R13
-!i10b 1
-R14
-R26
-R27
-!i113 1
-R17
-R18
-Amux2_1demo_arch
-R5
-R6
-Z29 DEx4 work 22 mux2_1demo_vhd_vec_tst 0 22 3C=jfC[[SFE>PIho5L8i70
-!i122 5
-l47
-Z30 L34 22
-Z31 Vlla6l@`UISZMAL4NHgkRB3
-Z32 !s100 YgE
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.bpm b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.bpm
deleted file mode 100644
index 8c5f0fe..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.cdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.cdb
deleted file mode 100644
index 4f82765..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.hdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.hdb
deleted file mode 100644
index cfbbdce..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.idb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.idb
deleted file mode 100644
index f39b64c..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.idb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.logdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.logdb
deleted file mode 100644
index fb39398..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.logdb
+++ /dev/null
@@ -1,49 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;7;7;0;0;7;7;0;0;0;0;0;0;1;0;0;0;6;1;0;6;0;0;1;0;7;7;7;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,7;0;0;7;7;0;0;7;7;7;7;7;7;6;7;7;7;1;6;7;1;7;7;6;7;0;0;0;7;7,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,LEDG[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.rdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp.rdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp_merge.kpt b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cmp_merge.kpt
deleted file mode 100644
index 2c903c5..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index 12d57d7..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
deleted file mode 100644
index 218eca7..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
deleted file mode 100644
index bea9e20..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.db_info b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.db_info
deleted file mode 100644
index 4a9447f..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Thu Mar 9 10:09:54 2023
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.eda.qmsg b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.eda.qmsg
deleted file mode 100644
index a91cca8..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678229306868 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678229306868 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 22:48:26 2023 " "Processing started: Tue Mar 7 22:48:26 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678229306868 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678229306868 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off Mux4_1Demo -c Mux4_1Demo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off Mux4_1Demo -c Mux4_1Demo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678229306868 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678229307032 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "Mux4_1Demo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/modelsim/ simulation " "Generated file Mux4_1Demo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678229307057 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678229307068 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 22:48:27 2023 " "Processing ended: Tue Mar 7 22:48:27 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678229307068 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678229307068 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678229307068 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678229307068 ""}
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.fit.qmsg b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.fit.qmsg
deleted file mode 100644
index 43a555c..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.fit.qmsg
+++ /dev/null
@@ -1,48 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678229297121 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678229297121 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "Mux4_1Demo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"Mux4_1Demo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678229297122 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678229297167 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678229297167 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678229297393 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678229297396 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678229297420 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678229297420 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678229297420 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678229297420 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678229297420 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678229297420 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678229297420 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678229297420 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678229297420 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678229297420 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/" { { 0 { 0 ""} 0 577 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678229297421 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/" { { 0 { 0 ""} 0 579 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678229297421 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/" { { 0 { 0 ""} 0 581 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678229297421 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/" { { 0 { 0 ""} 0 583 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678229297421 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/" { { 0 { 0 ""} 0 585 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678229297421 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678229297421 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678229297422 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Mux4_1Demo.sdc " "Synopsys Design Constraints File file not found: 'Mux4_1Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678229297874 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678229297874 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678229297874 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678229297875 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678229297875 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678229297875 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678229297875 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678229297877 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678229297877 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678229297877 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678229297877 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678229297877 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678229297877 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678229297877 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678229297877 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678229297878 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678229297878 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678229297878 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678229297888 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678229297888 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678229297895 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678229297897 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678229299281 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678229299345 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678229299376 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678229299521 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678229299521 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678229299676 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y12 X115_Y23 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23"} { { 12 { 0 ""} 104 12 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678229301652 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678229301652 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678229301770 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678229301770 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678229301770 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678229301771 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678229301838 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678229301844 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678229301989 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678229301989 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678229302131 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678229302354 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678229302519 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678229302550 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 519 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 519 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1144 " "Peak virtual memory: 1144 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678229302667 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 22:48:22 2023 " "Processing ended: Tue Mar 7 22:48:22 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678229302667 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678229302667 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678229302667 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678229302667 ""}
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.hier_info b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.hier_info
deleted file mode 100644
index db5570a..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.hier_info
+++ /dev/null
@@ -1,24 +0,0 @@
-|Mux4_1Demo
-LEDG[0] <= Mux4_1:inst.dataOut
-SW[0] => Mux4_1:inst.dataIn0
-SW[1] => Mux4_1:inst.dataIn1
-SW[2] => Mux4_1:inst.dataIn2
-SW[3] => Mux4_1:inst.dataIn3
-KEY[0] => Mux4_1:inst.sel[0]
-KEY[1] => Mux4_1:inst.sel[1]
-
-
-|Mux4_1Demo|Mux4_1:inst
-dataIn3 => dataOut.DATAA
-dataIn2 => dataOut.DATAB
-dataIn1 => dataOut.DATAB
-dataIn0 => dataOut.DATAB
-sel[0] => Equal0.IN1
-sel[0] => Equal1.IN1
-sel[0] => Equal2.IN0
-sel[1] => Equal0.IN0
-sel[1] => Equal1.IN0
-sel[1] => Equal2.IN1
-dataOut <= dataOut.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.hif b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.hif
deleted file mode 100644
index da086ce..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.hif and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.lpc.html b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.lpc.html
deleted file mode 100644
index f5763fa..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.lpc.html
+++ /dev/null
@@ -1,34 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| inst |
-6 |
-0 |
-0 |
-0 |
-1 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.lpc.rdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.lpc.rdb
deleted file mode 100644
index dbf8e20..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.lpc.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.lpc.txt b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.lpc.txt
deleted file mode 100644
index 9306f42..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.lpc.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; inst ; 6 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map.ammdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map.ammdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map.kpt b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map.kpt
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map.logdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map.logdb
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--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map.qmsg b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map.qmsg
deleted file mode 100644
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--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map.qmsg
+++ /dev/null
@@ -1,13 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678229290495 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678229290496 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 22:48:10 2023 " "Processing started: Tue Mar 7 22:48:10 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678229290496 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678229290496 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Mux4_1Demo -c Mux4_1Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off Mux4_1Demo -c Mux4_1Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678229290496 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678229290615 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678229290615 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mux4_1.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Mux4_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Mux4_1-Behavioral " "Found design unit 1: Mux4_1-Behavioral" { } { { "Mux4_1.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vhd" 16 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678229295911 ""} { "Info" "ISGN_ENTITY_NAME" "1 Mux4_1 " "Found entity 1: Mux4_1" { } { { "Mux4_1.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678229295911 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678229295911 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mux4_1Demo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Mux4_1Demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Mux4_1Demo " "Found entity 1: Mux4_1Demo" { } { { "Mux4_1Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1Demo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678229295911 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678229295911 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "Mux4_1Demo " "Elaborating entity \"Mux4_1Demo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678229295935 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Mux4_1 Mux4_1:inst " "Elaborating entity \"Mux4_1\" for hierarchy \"Mux4_1:inst\"" { } { { "Mux4_1Demo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1Demo.bdf" { { 160 424 584 304 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678229295937 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678229296271 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678229296587 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678229296587 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "9 " "Implemented 9 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678229296601 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678229296601 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2 " "Implemented 2 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678229296601 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678229296601 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "428 " "Peak virtual memory: 428 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678229296605 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 22:48:16 2023 " "Processing ended: Tue Mar 7 22:48:16 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678229296605 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678229296605 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678229296605 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678229296605 ""}
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map.rdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map.rdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map_bb.cdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map_bb.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map_bb.hdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map_bb.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map_bb.logdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.pre_map.hdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.root_partition.map.reg_db.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.routing.rdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.rtlv.hdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.rtlv_sg.cdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.rtlv_sg.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.sld_design_entry.sci b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.smart_action.txt b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.smart_action.txt
deleted file mode 100644
index c8e8a13..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.sta.qmsg b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.sta.qmsg
deleted file mode 100644
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--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678229305504 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678229305504 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 22:48:25 2023 " "Processing started: Tue Mar 7 22:48:25 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678229305504 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678229305504 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Mux4_1Demo -c Mux4_1Demo " "Command: quartus_sta Mux4_1Demo -c Mux4_1Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678229305504 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678229305525 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678229305582 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678229305582 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678229305627 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678229305627 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Mux4_1Demo.sdc " "Synopsys Design Constraints File file not found: 'Mux4_1Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678229305921 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678229305921 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678229305921 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678229305922 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678229305922 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678229305922 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678229305922 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678229305925 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678229305925 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229305926 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229305927 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229305928 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229305928 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229305928 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229305928 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678229305930 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678229305943 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678229306113 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678229306123 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678229306123 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678229306124 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678229306124 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229306124 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229306125 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229306125 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229306125 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229306126 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229306126 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678229306127 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678229306163 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678229306163 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678229306163 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678229306163 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229306163 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229306164 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229306164 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229306165 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678229306165 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678229306366 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678229306366 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "537 " "Peak virtual memory: 537 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678229306374 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 22:48:26 2023 " "Processing ended: Tue Mar 7 22:48:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678229306374 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678229306374 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678229306374 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678229306374 ""}
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.sta.rdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.sta.rdb
deleted file mode 100644
index 4a9a4ff..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.sta_cmp.7_slow_1200mv_85c.tdb
deleted file mode 100644
index 78d4f05..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.tis_db_list.ddb
deleted file mode 100644
index 73e5ec9..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index 8dddd27..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index fcce3c2..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index c8cc8bd..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.tmw_info b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.tmw_info
deleted file mode 100644
index 1bd50f7..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.tmw_info
+++ /dev/null
@@ -1,4 +0,0 @@
-start_full_compilation:s
-start_assembler:s-start_full_compilation
-start_timing_analyzer:s-start_full_compilation
-start_eda_netlist_writer:s-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.vpr.ammdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.vpr.ammdb
deleted file mode 100644
index b032876..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo_partition_pins.json b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo_partition_pins.json
deleted file mode 100644
index f406d26..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo_partition_pins.json
+++ /dev/null
@@ -1,37 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "LEDG[0]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- },
- {
- "name" : "KEY[0]",
- "strict" : false
- },
- {
- "name" : "SW[2]",
- "strict" : false
- },
- {
- "name" : "KEY[1]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- },
- {
- "name" : "SW[3]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/prev_cmp_Mux4_1Demo.qmsg b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/prev_cmp_Mux4_1Demo.qmsg
deleted file mode 100644
index 2975e44..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/prev_cmp_Mux4_1Demo.qmsg
+++ /dev/null
@@ -1,5 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678229263516 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678229263516 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 22:47:43 2023 " "Processing started: Tue Mar 7 22:47:43 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678229263516 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678229263516 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Mux4_1Demo -c Mux4_1Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off Mux4_1Demo -c Mux4_1Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678229263516 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678229263615 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678229263615 ""}
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/README b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.db_info b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.db_info
deleted file mode 100644
index 5c559d5..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Tue Mar 7 22:29:45 2023
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.cmp.ammdb
deleted file mode 100644
index 5e2f68b..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.cmp.cdb
deleted file mode 100644
index 97c884a..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.cmp.hdb
deleted file mode 100644
index 8e783f0..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.cmp.rcfdb
deleted file mode 100644
index b882bee..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.cdb
deleted file mode 100644
index a7c90e2..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.dpi
deleted file mode 100644
index 524d724..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.hbdb.cdb
deleted file mode 100644
index 9df3e6e..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.hbdb.hdb
deleted file mode 100644
index d727c71..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.hdb
deleted file mode 100644
index c3701f1..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.root_partition.map.kpt
deleted file mode 100644
index b45882e..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.rrp.hdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.rrp.hdb
deleted file mode 100644
index d757b53..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/incremental_db/compiled_partitions/Mux4_1Demo.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.asm.rpt b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.asm.rpt
deleted file mode 100644
index 516631b..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for Mux4_1Demo
-Tue Mar 7 22:48:25 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: Mux4_1Demo.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Tue Mar 7 22:48:25 2023 ;
-; Revision Name ; Mux4_1Demo ;
-; Top-level Entity Name ; Mux4_1Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+------------------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+------------------------------------------------------------------------------------------------------+
-; File Name ;
-+------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.sof ;
-+------------------------------------------------------------------------------------------------------+
-
-
-+------------------------------------------+
-; Assembler Device Options: Mux4_1Demo.sof ;
-+----------------+-------------------------+
-; Option ; Setting ;
-+----------------+-------------------------+
-; JTAG usercode ; 0x005632B6 ;
-; Checksum ; 0x005632B6 ;
-+----------------+-------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 22:48:23 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Mux4_1Demo -c Mux4_1Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 364 megabytes
- Info: Processing ended: Tue Mar 7 22:48:25 2023
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.done b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.done
deleted file mode 100644
index 2bf6f51..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.done
+++ /dev/null
@@ -1 +0,0 @@
-Tue Mar 7 22:48:27 2023
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.eda.rpt b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.eda.rpt
deleted file mode 100644
index fe09fc0..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.eda.rpt
+++ /dev/null
@@ -1,94 +0,0 @@
-EDA Netlist Writer report for Mux4_1Demo
-Tue Mar 7 22:48:27 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Tue Mar 7 22:48:27 2023 ;
-; Revision Name ; Mux4_1Demo ;
-; Top-level Entity Name ; Mux4_1Demo ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+-------------------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+-------------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/modelsim/Mux4_1Demo.vho ;
-+-------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 22:48:26 2023
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Mux4_1Demo -c Mux4_1Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file Mux4_1Demo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 612 megabytes
- Info: Processing ended: Tue Mar 7 22:48:27 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.fit.rpt b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.fit.rpt
deleted file mode 100644
index 41217f2..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.fit.rpt
+++ /dev/null
@@ -1,2524 +0,0 @@
-Fitter report for Mux4_1Demo
-Tue Mar 7 22:48:22 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Tue Mar 7 22:48:22 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; Mux4_1Demo ;
-; Top-level Entity Name ; Mux4_1Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 2 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 2 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 7 / 529 ( 1 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; CLOCK_50 ; PIN_Y2 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
-; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
-; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
-; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
-; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
-; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
-; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
-; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
-; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[0] ; PIN_G19 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[1] ; PIN_F19 ; QSF Assignment ;
-; Location ; ; ; LEDR[2] ; PIN_E19 ; QSF Assignment ;
-; Location ; ; ; LEDR[3] ; PIN_F21 ; QSF Assignment ;
-; Location ; ; ; LEDR[4] ; PIN_F18 ; QSF Assignment ;
-; Location ; ; ; LEDR[5] ; PIN_E18 ; QSF Assignment ;
-; Location ; ; ; LEDR[6] ; PIN_J19 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_H19 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; SW[10] ; PIN_AC24 ; QSF Assignment ;
-; Location ; ; ; SW[11] ; PIN_AB24 ; QSF Assignment ;
-; Location ; ; ; SW[12] ; PIN_AB23 ; QSF Assignment ;
-; Location ; ; ; SW[13] ; PIN_AA24 ; QSF Assignment ;
-; Location ; ; ; SW[14] ; PIN_AA23 ; QSF Assignment ;
-; Location ; ; ; SW[15] ; PIN_AA22 ; QSF Assignment ;
-; Location ; ; ; SW[16] ; PIN_Y24 ; QSF Assignment ;
-; Location ; ; ; SW[17] ; PIN_Y23 ; QSF Assignment ;
-; Location ; ; ; SW[4] ; PIN_AB27 ; QSF Assignment ;
-; Location ; ; ; SW[5] ; PIN_AC26 ; QSF Assignment ;
-; Location ; ; ; SW[6] ; PIN_AD26 ; QSF Assignment ;
-; Location ; ; ; SW[7] ; PIN_AB26 ; QSF Assignment ;
-; Location ; ; ; SW[8] ; PIN_AC25 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AB25 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 27 ) ; 0.00 % ( 0 / 27 ) ; 0.00 % ( 0 / 27 ) ;
-; -- Achieved ; 0.00 % ( 0 / 27 ) ; 0.00 % ( 0 / 27 ) ; 0.00 % ( 0 / 27 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 17 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+-----------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-----------------------+
-; Total logic elements ; 2 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 2 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 2 ;
-; -- 3 input functions ; 0 ;
-; -- <=2 input functions ; 0 ;
-; -- Register only ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 2 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers* ; 0 / 117,053 ( 0 % ) ;
-; -- Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 1 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 7 / 529 ( 1 % ) ;
-; -- Clock pins ; 0 / 7 ( 0 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.1% / 0.0% / 0.2% ;
-; Maximum fan-out ; 2 ;
-; Highest non-global fan-out ; 2 ;
-; Total fan-out ; 21 ;
-; Average fan-out ; 0.81 ;
-+---------------------------------------------+-----------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 2 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 2 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 2 ; 0 ;
-; -- 3 input functions ; 0 ; 0 ;
-; -- <=2 input functions ; 0 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 2 ; 0 ;
-; -- arithmetic mode ; 0 ; 0 ;
-; ; ; ;
-; Total registers ; 0 ; 0 ;
-; -- Dedicated logic registers ; 0 / 114480 ( 0 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 1 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 7 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 16 ; 5 ;
-; -- Registered Connections ; 0 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 6 ; 0 ;
-; -- Output Ports ; 1 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; KEY[0] ; M23 ; 6 ; 115 ; 40 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; KEY[1] ; M21 ; 6 ; 115 ; 53 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[3] ; AD27 ; 5 ; 115 ; 13 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; LEDG[0] ; E21 ; 7 ; 107 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+----------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+----------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+----------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 0 / 63 ( 0 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 4 / 65 ( 6 % ) ; 2.5V ; -- ;
-; 6 ; 3 / 58 ( 5 % ) ; 2.5V ; -- ;
-; 7 ; 1 / 72 ( 1 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+----------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA23 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA24 ; 279 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB24 ; 274 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB25 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB26 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB27 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC25 ; 272 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC26 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD27 ; 286 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; LEDG[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; KEY[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y24 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; LEDG[0] ; Incomplete set of assignments ;
-; SW[1] ; Incomplete set of assignments ;
-; KEY[0] ; Incomplete set of assignments ;
-; SW[2] ; Incomplete set of assignments ;
-; KEY[1] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-; SW[3] ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+-------------+--------------+
-; |Mux4_1Demo ; 2 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; |Mux4_1Demo ; Mux4_1Demo ; work ;
-; |Mux4_1:inst| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |Mux4_1Demo|Mux4_1:inst ; Mux4_1 ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-----------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; LEDG[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[1] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; KEY[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; KEY[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[3] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+------------------------------+-------------------+---------+
-; SW[1] ; ; ;
-; - Mux4_1:inst|dataOut~1 ; 1 ; 6 ;
-; KEY[0] ; ; ;
-; - Mux4_1:inst|dataOut~0 ; 1 ; 6 ;
-; - Mux4_1:inst|dataOut~1 ; 1 ; 6 ;
-; SW[2] ; ; ;
-; - Mux4_1:inst|dataOut~0 ; 1 ; 6 ;
-; KEY[1] ; ; ;
-; - Mux4_1:inst|dataOut~0 ; 0 ; 6 ;
-; SW[0] ; ; ;
-; - Mux4_1:inst|dataOut~0 ; 0 ; 6 ;
-; SW[3] ; ; ;
-; - Mux4_1:inst|dataOut~1 ; 0 ; 6 ;
-+------------------------------+-------------------+---------+
-
-
-+------------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+------------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+------------------------+
-; Block interconnects ; 7 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 3 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 20 / 209,544 ( < 1 % ) ;
-; Direct links ; 0 / 342,891 ( 0 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 1 / 119,088 ( < 1 % ) ;
-; R24 interconnects ; 2 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 2 / 289,782 ( < 1 % ) ;
-+-----------------------+------------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 2.00) ; Number of LABs (Total = 1) ;
-+--------------------------------------------+-----------------------------+
-; 1 ; 0 ;
-; 2 ; 1 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-+--------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 2.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 1) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 1 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 6.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 7 ; 7 ; 0 ; 0 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 6 ; 1 ; 0 ; 6 ; 0 ; 0 ; 1 ; 0 ; 7 ; 7 ; 7 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 7 ; 0 ; 0 ; 7 ; 7 ; 0 ; 0 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 6 ; 7 ; 7 ; 7 ; 1 ; 6 ; 7 ; 1 ; 7 ; 7 ; 6 ; 7 ; 0 ; 0 ; 0 ; 7 ; 7 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; LEDG[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "Mux4_1Demo"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'Mux4_1Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 519 warnings
- Info: Peak virtual memory: 1144 megabytes
- Info: Processing ended: Tue Mar 7 22:48:22 2023
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:09
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.fit.smsg b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.fit.summary b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.fit.summary
deleted file mode 100644
index f6060b5..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Tue Mar 7 22:48:22 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : Mux4_1Demo
-Top-level Entity Name : Mux4_1Demo
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 2 / 114,480 ( < 1 % )
- Total combinational functions : 2 / 114,480 ( < 1 % )
- Dedicated logic registers : 0 / 114,480 ( 0 % )
-Total registers : 0
-Total pins : 7 / 529 ( 1 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.flow.rpt b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.flow.rpt
deleted file mode 100644
index 1ee5ae5..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.flow.rpt
+++ /dev/null
@@ -1,134 +0,0 @@
-Flow report for Mux4_1Demo
-Tue Mar 7 22:48:27 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Tue Mar 7 22:48:27 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; Mux4_1Demo ;
-; Top-level Entity Name ; Mux4_1Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 2 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 2 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 7 / 529 ( 1 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/07/2023 22:48:10 ;
-; Main task ; Compilation ;
-; Revision Name ; Mux4_1Demo ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 2690080394329.167822929019749 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 428 MB ; 00:00:15 ;
-; Fitter ; 00:00:06 ; 1.0 ; 1144 MB ; 00:00:09 ;
-; Assembler ; 00:00:02 ; 1.0 ; 364 MB ; 00:00:02 ;
-; Timing Analyzer ; 00:00:01 ; 1.0 ; 537 MB ; 00:00:01 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 612 MB ; 00:00:00 ;
-; Total ; 00:00:16 ; -- ; -- ; 00:00:27 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off Mux4_1Demo -c Mux4_1Demo
-quartus_fit --read_settings_files=off --write_settings_files=off Mux4_1Demo -c Mux4_1Demo
-quartus_asm --read_settings_files=off --write_settings_files=off Mux4_1Demo -c Mux4_1Demo
-quartus_sta Mux4_1Demo -c Mux4_1Demo
-quartus_eda --read_settings_files=off --write_settings_files=off Mux4_1Demo -c Mux4_1Demo
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.jdi b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.jdi
deleted file mode 100644
index 2b6c94e..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.map.rpt b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.map.rpt
deleted file mode 100644
index 4ff1b46..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.map.rpt
+++ /dev/null
@@ -1,287 +0,0 @@
-Analysis & Synthesis report for Mux4_1Demo
-Tue Mar 7 22:48:16 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Post-Synthesis Netlist Statistics for Top Partition
- 10. Elapsed Time Per Partition
- 11. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Tue Mar 7 22:48:16 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; Mux4_1Demo ;
-; Top-level Entity Name ; Mux4_1Demo ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 2 ;
-; Total combinational functions ; 2 ;
-; Dedicated logic registers ; 0 ;
-; Total registers ; 0 ;
-; Total pins ; 7 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; Mux4_1Demo ; Mux4_1Demo ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------+---------+
-; Mux4_1.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vhd ; ;
-; Mux4_1Demo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1Demo.bdf ; ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------+---------+
-
-
-+------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+--------------+
-; Resource ; Usage ;
-+---------------------------------------------+--------------+
-; Estimated Total logic elements ; 2 ;
-; ; ;
-; Total combinational functions ; 2 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 2 ;
-; -- 3 input functions ; 0 ;
-; -- <=2 input functions ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 2 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers ; 0 ;
-; -- Dedicated logic registers ; 0 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 7 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; KEY[0]~input ;
-; Maximum fan-out ; 2 ;
-; Total fan-out ; 16 ;
-; Average fan-out ; 1.00 ;
-+---------------------------------------------+--------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+-------------+--------------+
-; |Mux4_1Demo ; 2 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; |Mux4_1Demo ; Mux4_1Demo ; work ;
-; |Mux4_1:inst| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Mux4_1Demo|Mux4_1:inst ; Mux4_1 ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 0 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 7 ;
-; cycloneiii_lcell_comb ; 2 ;
-; normal ; 2 ;
-; 4 data inputs ; 2 ;
-; ; ;
-; Max LUT depth ; 2.00 ;
-; Average LUT depth ; 1.75 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 22:48:10 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Mux4_1Demo -c Mux4_1Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 2 design units, including 1 entities, in source file Mux4_1.vhd
- Info (12022): Found design unit 1: Mux4_1-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vhd Line: 16
- Info (12023): Found entity 1: Mux4_1 File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vhd Line: 4
-Info (12021): Found 1 design units, including 1 entities, in source file Mux4_1Demo.bdf
- Info (12023): Found entity 1: Mux4_1Demo
-Info (12127): Elaborating entity "Mux4_1Demo" for the top level hierarchy
-Info (12128): Elaborating entity "Mux4_1" for hierarchy "Mux4_1:inst"
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 9 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 6 input pins
- Info (21059): Implemented 1 output pins
- Info (21061): Implemented 2 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 428 megabytes
- Info: Processing ended: Tue Mar 7 22:48:16 2023
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:15
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.map.summary b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.map.summary
deleted file mode 100644
index 4cc5486..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Tue Mar 7 22:48:16 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : Mux4_1Demo
-Top-level Entity Name : Mux4_1Demo
-Family : Cyclone IV E
-Total logic elements : 2
- Total combinational functions : 2
- Dedicated logic registers : 0
-Total registers : 0
-Total pins : 7
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.pin b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.pin
deleted file mode 100644
index 53ab844..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "Mux4_1Demo" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5 :
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC26 : : : : 5 :
-SW[2] : AC27 : input : 2.5 V : : 5 : Y
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5 :
-SW[3] : AD27 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7 :
-VCCIO7 : E20 : power : : 2.5V : 7 :
-LEDG[0] : E21 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
-VCCIO7 : E23 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7 :
-GND : F20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
-VCCIO7 : H18 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7 :
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-KEY[1] : M21 : input : 2.5 V : : 6 : Y
-MSEL2 : M22 : : : : 6 :
-KEY[0] : M23 : input : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-GND+ : Y2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.sld b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.sta.rpt b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.sta.rpt
deleted file mode 100644
index ca1c34a..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.sta.rpt
+++ /dev/null
@@ -1,443 +0,0 @@
-Timing Analyzer report for Mux4_1Demo
-Tue Mar 7 22:48:26 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Unconstrained Input Ports
- 37. Unconstrained Output Ports
- 38. Unconstrained Input Ports
- 39. Unconstrained Output Ports
- 40. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; Mux4_1Demo ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.1% ;
-+----------------------------+-------------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 6 ; 6 ;
-; Unconstrained Input Port Paths ; 6 ; 6 ;
-; Unconstrained Output Ports ; 1 ; 1 ;
-; Unconstrained Output Port Paths ; 6 ; 6 ;
-+---------------------------------+-------+------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 7 22:48:25 2023
-Info: Command: quartus_sta Mux4_1Demo -c Mux4_1Demo
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'Mux4_1Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 537 megabytes
- Info: Processing ended: Tue Mar 7 22:48:26 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.sta.summary b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.sta.summary
deleted file mode 100644
index aa5b327..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/output_files/Mux4_1Demo.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/modelsim/Mux4_1Demo.sft b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/modelsim/Mux4_1Demo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/modelsim/Mux4_1Demo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/modelsim/Mux4_1Demo.vho b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/modelsim/Mux4_1Demo.vho
deleted file mode 100644
index 0d65605..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/modelsim/Mux4_1Demo.vho
+++ /dev/null
@@ -1,255 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/07/2023 22:48:27"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY Mux4_1Demo IS
- PORT (
- LEDG : OUT std_logic_vector(0 DOWNTO 0);
- SW : IN std_logic_vector(3 DOWNTO 0);
- KEY : IN std_logic_vector(1 DOWNTO 0)
- );
-END Mux4_1Demo;
-
--- Design Ports Information
--- LEDG[0] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF Mux4_1Demo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDG : std_logic_vector(0 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(3 DOWNTO 0);
-SIGNAL ww_KEY : std_logic_vector(1 DOWNTO 0);
-SIGNAL \LEDG[0]~output_o\ : std_logic;
-SIGNAL \SW[3]~input_o\ : std_logic;
-SIGNAL \KEY[0]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \SW[2]~input_o\ : std_logic;
-SIGNAL \KEY[1]~input_o\ : std_logic;
-SIGNAL \inst|dataOut~0_combout\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \inst|dataOut~1_combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-LEDG <= ww_LEDG;
-ww_SW <= SW;
-ww_KEY <= KEY;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X107_Y73_N9
-\LEDG[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|dataOut~1_combout\,
- devoe => ww_devoe,
- o => \LEDG[0]~output_o\);
-
--- Location: IOIBUF_X115_Y13_N8
-\SW[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(3),
- o => \SW[3]~input_o\);
-
--- Location: IOIBUF_X115_Y40_N8
-\KEY[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY(0),
- o => \KEY[0]~input_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N8
-\SW[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(2),
- o => \SW[2]~input_o\);
-
--- Location: IOIBUF_X115_Y53_N15
-\KEY[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY(1),
- o => \KEY[1]~input_o\);
-
--- Location: LCCOMB_X114_Y17_N24
-\inst|dataOut~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|dataOut~0_combout\ = (\KEY[0]~input_o\ & (((\KEY[1]~input_o\)))) # (!\KEY[0]~input_o\ & ((\KEY[1]~input_o\ & ((\SW[2]~input_o\))) # (!\KEY[1]~input_o\ & (\SW[0]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111101001000100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \KEY[0]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[2]~input_o\,
- datad => \KEY[1]~input_o\,
- combout => \inst|dataOut~0_combout\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: LCCOMB_X114_Y17_N10
-\inst|dataOut~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|dataOut~1_combout\ = (\inst|dataOut~0_combout\ & ((\SW[3]~input_o\) # ((!\KEY[0]~input_o\)))) # (!\inst|dataOut~0_combout\ & (((\SW[1]~input_o\ & \KEY[0]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1011100011001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \inst|dataOut~0_combout\,
- datac => \SW[1]~input_o\,
- datad => \KEY[0]~input_o\,
- combout => \inst|dataOut~1_combout\);
-
-ww_LEDG(0) <= \LEDG[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/modelsim/Mux4_1Demo_modelsim.xrf b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/modelsim/Mux4_1Demo_modelsim.xrf
deleted file mode 100644
index 568acd0..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/modelsim/Mux4_1Demo_modelsim.xrf
+++ /dev/null
@@ -1,20 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vwf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1Demo.bdf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cbx.xml
-design_name = hard_block
-design_name = Mux4_1Demo
-instance = comp, \LEDG[0]~output\, LEDG[0]~output, Mux4_1Demo, 1
-instance = comp, \SW[3]~input\, SW[3]~input, Mux4_1Demo, 1
-instance = comp, \KEY[0]~input\, KEY[0]~input, Mux4_1Demo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, Mux4_1Demo, 1
-instance = comp, \SW[2]~input\, SW[2]~input, Mux4_1Demo, 1
-instance = comp, \KEY[1]~input\, KEY[1]~input, Mux4_1Demo, 1
-instance = comp, \inst|dataOut~0\, inst|dataOut~0, Mux4_1Demo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, Mux4_1Demo, 1
-instance = comp, \inst|dataOut~1\, inst|dataOut~1, Mux4_1Demo, 1
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1.vwf.vht b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1.vwf.vht
deleted file mode 100644
index 3706178..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1.vwf.vht
+++ /dev/null
@@ -1,135 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- *****************************************************************************
--- This file contains a Vhdl test bench with test vectors .The test vectors
--- are exported from a vector file in the Quartus Waveform Editor and apply to
--- the top level entity of the current Quartus project .The user can use this
--- testbench to simulate his design using a third-party simulation tool .
--- *****************************************************************************
--- Generated on "03/07/2023 22:35:03"
-
--- Vhdl Test Bench(with test vectors) for design : Mux4_1
---
--- Simulation tool : 3rd Party
---
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY Mux4_1_vhd_vec_tst IS
-END Mux4_1_vhd_vec_tst;
-ARCHITECTURE Mux4_1_arch OF Mux4_1_vhd_vec_tst IS
--- constants
--- signals
-SIGNAL dataIn0 : STD_LOGIC;
-SIGNAL dataIn1 : STD_LOGIC;
-SIGNAL dataIn2 : STD_LOGIC;
-SIGNAL dataIn3 : STD_LOGIC;
-SIGNAL dataOut : STD_LOGIC;
-SIGNAL sel : STD_LOGIC_VECTOR(1 DOWNTO 0);
-COMPONENT Mux4_1
- PORT (
- dataIn0 : IN STD_LOGIC;
- dataIn1 : IN STD_LOGIC;
- dataIn2 : IN STD_LOGIC;
- dataIn3 : IN STD_LOGIC;
- dataOut : OUT STD_LOGIC;
- sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
- );
-END COMPONENT;
-BEGIN
- i1 : Mux4_1
- PORT MAP (
--- list connections between master ports and signals
- dataIn0 => dataIn0,
- dataIn1 => dataIn1,
- dataIn2 => dataIn2,
- dataIn3 => dataIn3,
- dataOut => dataOut,
- sel => sel
- );
-
--- dataIn3
-t_prcs_dataIn3: PROCESS
-BEGIN
-LOOP
- dataIn3 <= '0';
- WAIT FOR 100000 ps;
- dataIn3 <= '1';
- WAIT FOR 100000 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_dataIn3;
-
--- dataIn2
-t_prcs_dataIn2: PROCESS
-BEGIN
-LOOP
- dataIn2 <= '0';
- WAIT FOR 50000 ps;
- dataIn2 <= '1';
- WAIT FOR 50000 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_dataIn2;
-
--- dataIn1
-t_prcs_dataIn1: PROCESS
-BEGIN
-LOOP
- dataIn1 <= '0';
- WAIT FOR 25000 ps;
- dataIn1 <= '1';
- WAIT FOR 25000 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_dataIn1;
-
--- dataIn0
-t_prcs_dataIn0: PROCESS
-BEGIN
-LOOP
- dataIn0 <= '0';
- WAIT FOR 12500 ps;
- dataIn0 <= '1';
- WAIT FOR 12500 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_dataIn0;
--- sel[1]
-t_prcs_sel_1: PROCESS
-BEGIN
- sel(1) <= '0';
- WAIT FOR 400000 ps;
- sel(1) <= '1';
- WAIT FOR 400000 ps;
- sel(1) <= '0';
-WAIT;
-END PROCESS t_prcs_sel_1;
--- sel[0]
-t_prcs_sel_0: PROCESS
-BEGIN
- FOR i IN 1 TO 2
- LOOP
- sel(0) <= '0';
- WAIT FOR 200000 ps;
- sel(0) <= '1';
- WAIT FOR 200000 ps;
- END LOOP;
- sel(0) <= '0';
-WAIT;
-END PROCESS t_prcs_sel_0;
-END Mux4_1_arch;
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.do b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.do
deleted file mode 100644
index 58854de..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.do
+++ /dev/null
@@ -1,17 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vcom -work work Mux4_1Demo.vho
-vcom -work work Mux4_1.vwf.vht
-vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux4_1_vhd_vec_tst
-vcd file -direction Mux4_1Demo.msim.vcd
-vcd add -internal Mux4_1_vhd_vec_tst/*
-vcd add -internal Mux4_1_vhd_vec_tst/i1/*
-proc simTimestamp {} {
- echo "Simulation time: $::now ps"
- if { [string equal running [runStatus]] } {
- after 2500 simTimestamp
- }
-}
-after 2500 simTimestamp
-run -all
-quit -f
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.msim.vcd b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.msim.vcd
deleted file mode 100644
index e3d42b9..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.msim.vcd
+++ /dev/null
@@ -1,844 +0,0 @@
-$comment
- File created using the following command:
- vcd file Mux4_1Demo.msim.vcd -direction
-$end
-$date
- Tue Mar 7 22:35:05 2023
-$end
-$version
- ModelSim Version 2020.1
-$end
-$timescale
- 1ps
-$end
-
-$scope module mux4_1_vhd_vec_tst $end
-$var wire 1 ! dataIn0 $end
-$var wire 1 " dataIn1 $end
-$var wire 1 # dataIn2 $end
-$var wire 1 $ dataIn3 $end
-$var wire 1 % dataOut $end
-$var wire 1 & sel [1] $end
-$var wire 1 ' sel [0] $end
-
-$scope module i1 $end
-$var wire 1 ( gnd $end
-$var wire 1 ) vcc $end
-$var wire 1 * unknown $end
-$var wire 1 + devoe $end
-$var wire 1 , devclrn $end
-$var wire 1 - devpor $end
-$var wire 1 . ww_devoe $end
-$var wire 1 / ww_devclrn $end
-$var wire 1 0 ww_devpor $end
-$var wire 1 1 ww_dataIn0 $end
-$var wire 1 2 ww_dataIn1 $end
-$var wire 1 3 ww_dataIn2 $end
-$var wire 1 4 ww_dataIn3 $end
-$var wire 1 5 ww_sel [1] $end
-$var wire 1 6 ww_sel [0] $end
-$var wire 1 7 ww_dataOut $end
-$var wire 1 8 \dataOut~output_o\ $end
-$var wire 1 9 \dataIn2~input_o\ $end
-$var wire 1 : \sel[1]~input_o\ $end
-$var wire 1 ; \dataIn1~input_o\ $end
-$var wire 1 < \sel[0]~input_o\ $end
-$var wire 1 = \dataIn0~input_o\ $end
-$var wire 1 > \dataOut~0_combout\ $end
-$var wire 1 ? \dataIn3~input_o\ $end
-$var wire 1 @ \dataOut~1_combout\ $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0!
-0"
-0#
-0$
-0%
-0(
-1)
-x*
-1+
-1,
-1-
-1.
-1/
-10
-01
-02
-03
-04
-07
-08
-09
-0:
-0;
-0<
-0=
-0>
-0?
-0@
-0&
-0'
-05
-06
-$end
-#12500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#25000
-0!
-1"
-01
-12
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-0=
-0>
-0@
-08
-07
-0%
-#37500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#50000
-0!
-0"
-1#
-01
-02
-13
-19
-0;
-0=
-0>
-0@
-08
-07
-0%
-#62500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#75000
-0!
-1"
-01
-12
-1;
-0=
-0>
-0@
-08
-07
-0%
-#87500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#100000
-0!
-0"
-0#
-1$
-01
-02
-03
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-1?
-09
-0;
-0=
-0>
-0@
-08
-07
-0%
-#112500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#125000
-0!
-1"
-01
-12
-1;
-0=
-0>
-0@
-08
-07
-0%
-#137500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#150000
-0!
-0"
-1#
-01
-02
-13
-19
-0;
-0=
-0>
-0@
-08
-07
-0%
-#162500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#175000
-0!
-1"
-01
-12
-1;
-0=
-0>
-0@
-08
-07
-0%
-#187500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#200000
-0!
-0"
-0#
-0$
-1'
-01
-02
-03
-04
-16
-1<
-0?
-09
-0;
-0=
-0>
-0@
-08
-07
-0%
-#212500
-1!
-11
-1=
-#225000
-0!
-1"
-01
-12
-1;
-0=
-1>
-1@
-18
-17
-1%
-#237500
-1!
-11
-1=
-#250000
-0!
-0"
-1#
-01
-02
-13
-19
-0;
-0=
-0>
-0@
-08
-07
-0%
-#262500
-1!
-11
-1=
-#275000
-0!
-1"
-01
-12
-1;
-0=
-1>
-1@
-18
-17
-1%
-#287500
-1!
-11
-1=
-#300000
-0!
-0"
-0#
-1$
-01
-02
-03
-14
-1?
-09
-0;
-0=
-0>
-0@
-08
-07
-0%
-#312500
-1!
-11
-1=
-#325000
-0!
-1"
-01
-12
-1;
-0=
-1>
-1@
-18
-17
-1%
-#337500
-1!
-11
-1=
-#350000
-0!
-0"
-1#
-01
-02
-13
-19
-0;
-0=
-0>
-0@
-08
-07
-0%
-#362500
-1!
-11
-1=
-#375000
-0!
-1"
-01
-12
-1;
-0=
-1>
-1@
-18
-17
-1%
-#387500
-1!
-11
-1=
-#400000
-0!
-0"
-0#
-0$
-0'
-1&
-01
-02
-03
-04
-06
-15
-1:
-0<
-0?
-09
-0;
-0=
-0>
-0@
-08
-07
-0%
-#412500
-1!
-11
-1=
-#425000
-0!
-1"
-01
-12
-1;
-0=
-#437500
-1!
-11
-1=
-#450000
-0!
-0"
-1#
-01
-02
-13
-19
-0;
-0=
-1@
-18
-17
-1%
-#462500
-1!
-11
-1=
-#475000
-0!
-1"
-01
-12
-1;
-0=
-#487500
-1!
-11
-1=
-#500000
-0!
-0"
-0#
-1$
-01
-02
-03
-14
-1?
-09
-0;
-0=
-0@
-08
-07
-0%
-#512500
-1!
-11
-1=
-#525000
-0!
-1"
-01
-12
-1;
-0=
-#537500
-1!
-11
-1=
-#550000
-0!
-0"
-1#
-01
-02
-13
-19
-0;
-0=
-1@
-18
-17
-1%
-#562500
-1!
-11
-1=
-#575000
-0!
-1"
-01
-12
-1;
-0=
-#587500
-1!
-11
-1=
-#600000
-0!
-0"
-0#
-0$
-1'
-01
-02
-03
-04
-16
-1<
-0?
-09
-0;
-0=
-0@
-1>
-08
-07
-0%
-#612500
-1!
-11
-1=
-#625000
-0!
-1"
-01
-12
-1;
-0=
-#637500
-1!
-11
-1=
-#650000
-0!
-0"
-1#
-01
-02
-13
-19
-0;
-0=
-#662500
-1!
-11
-1=
-#675000
-0!
-1"
-01
-12
-1;
-0=
-#687500
-1!
-11
-1=
-#700000
-0!
-0"
-0#
-1$
-01
-02
-03
-14
-1?
-09
-0;
-0=
-1@
-18
-17
-1%
-#712500
-1!
-11
-1=
-#725000
-0!
-1"
-01
-12
-1;
-0=
-#737500
-1!
-11
-1=
-#750000
-0!
-0"
-1#
-01
-02
-13
-19
-0;
-0=
-#762500
-1!
-11
-1=
-#775000
-0!
-1"
-01
-12
-1;
-0=
-#787500
-1!
-11
-1=
-#800000
-0!
-0"
-0#
-0$
-0'
-0&
-01
-02
-03
-04
-06
-05
-0:
-0<
-0?
-09
-0;
-0=
-0>
-0@
-08
-07
-0%
-#812500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#825000
-0!
-1"
-01
-12
-1;
-0=
-0>
-0@
-08
-07
-0%
-#837500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#850000
-0!
-0"
-1#
-01
-02
-13
-19
-0;
-0=
-0>
-0@
-08
-07
-0%
-#862500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#875000
-0!
-1"
-01
-12
-1;
-0=
-0>
-0@
-08
-07
-0%
-#887500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#900000
-0!
-0"
-0#
-1$
-01
-02
-03
-14
-1?
-09
-0;
-0=
-0>
-0@
-08
-07
-0%
-#912500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#925000
-0!
-1"
-01
-12
-1;
-0=
-0>
-0@
-08
-07
-0%
-#937500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#950000
-0!
-0"
-1#
-01
-02
-13
-19
-0;
-0=
-0>
-0@
-08
-07
-0%
-#962500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#975000
-0!
-1"
-01
-12
-1;
-0=
-0>
-0@
-08
-07
-0%
-#987500
-1!
-11
-1=
-1>
-1@
-18
-17
-1%
-#1000000
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.sft b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.vho b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.vho
deleted file mode 100644
index 8cf6928..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.vho
+++ /dev/null
@@ -1,190 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/07/2023 22:35:04"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY Mux4_1 IS
- PORT (
- dataIn0 : IN std_logic;
- dataIn1 : IN std_logic;
- dataIn2 : IN std_logic;
- dataIn3 : IN std_logic;
- sel : IN std_logic_vector(1 DOWNTO 0);
- dataOut : OUT std_logic
- );
-END Mux4_1;
-
-ARCHITECTURE structure OF Mux4_1 IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_dataIn0 : std_logic;
-SIGNAL ww_dataIn1 : std_logic;
-SIGNAL ww_dataIn2 : std_logic;
-SIGNAL ww_dataIn3 : std_logic;
-SIGNAL ww_sel : std_logic_vector(1 DOWNTO 0);
-SIGNAL ww_dataOut : std_logic;
-SIGNAL \dataOut~output_o\ : std_logic;
-SIGNAL \dataIn2~input_o\ : std_logic;
-SIGNAL \sel[1]~input_o\ : std_logic;
-SIGNAL \dataIn1~input_o\ : std_logic;
-SIGNAL \sel[0]~input_o\ : std_logic;
-SIGNAL \dataIn0~input_o\ : std_logic;
-SIGNAL \dataOut~0_combout\ : std_logic;
-SIGNAL \dataIn3~input_o\ : std_logic;
-SIGNAL \dataOut~1_combout\ : std_logic;
-
-BEGIN
-
-ww_dataIn0 <= dataIn0;
-ww_dataIn1 <= dataIn1;
-ww_dataIn2 <= dataIn2;
-ww_dataIn3 <= dataIn3;
-ww_sel <= sel;
-dataOut <= ww_dataOut;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
-\dataOut~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \dataOut~1_combout\,
- devoe => ww_devoe,
- o => \dataOut~output_o\);
-
-\dataIn2~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_dataIn2,
- o => \dataIn2~input_o\);
-
-\sel[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_sel(1),
- o => \sel[1]~input_o\);
-
-\dataIn1~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_dataIn1,
- o => \dataIn1~input_o\);
-
-\sel[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_sel(0),
- o => \sel[0]~input_o\);
-
-\dataIn0~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_dataIn0,
- o => \dataIn0~input_o\);
-
-\dataOut~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \dataOut~0_combout\ = (\sel[1]~input_o\ & (((\sel[0]~input_o\)))) # (!\sel[1]~input_o\ & ((\sel[0]~input_o\ & (\dataIn1~input_o\)) # (!\sel[0]~input_o\ & ((\dataIn0~input_o\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1110010111100000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \sel[1]~input_o\,
- datab => \dataIn1~input_o\,
- datac => \sel[0]~input_o\,
- datad => \dataIn0~input_o\,
- combout => \dataOut~0_combout\);
-
-\dataIn3~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_dataIn3,
- o => \dataIn3~input_o\);
-
-\dataOut~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \dataOut~1_combout\ = (\sel[1]~input_o\ & ((\dataOut~0_combout\ & ((\dataIn3~input_o\))) # (!\dataOut~0_combout\ & (\dataIn2~input_o\)))) # (!\sel[1]~input_o\ & (((\dataOut~0_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111100000111000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \dataIn2~input_o\,
- datab => \sel[1]~input_o\,
- datac => \dataOut~0_combout\,
- datad => \dataIn3~input_o\,
- combout => \dataOut~1_combout\);
-
-ww_dataOut <= \dataOut~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo_20230307223505.sim.vwf b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo_20230307223505.sim.vwf
deleted file mode 100644
index a49568e..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo_20230307223505.sim.vwf
+++ /dev/null
@@ -1,484 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("dataIn0")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("dataIn1")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("dataIn2")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("dataIn3")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("dataOut")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("sel")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 2;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("sel[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "sel";
-}
-
-SIGNAL("sel[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "sel";
-}
-
-TRANSITION_LIST("dataIn0")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- }
- }
-}
-
-TRANSITION_LIST("dataIn1")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- }
- }
-}
-
-TRANSITION_LIST("dataIn2")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- }
- }
-}
-
-TRANSITION_LIST("dataIn3")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- }
- }
-}
-
-TRANSITION_LIST("dataOut")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 50.0;
- LEVEL 0 FOR 100.0;
- LEVEL 1 FOR 100.0;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- LEVEL 0 FOR 12.5;
- LEVEL 1 FOR 12.5;
- }
- }
-}
-
-TRANSITION_LIST("sel[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 400.0;
- LEVEL 1 FOR 400.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-TRANSITION_LIST("sel[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn3";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn2";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn1";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn0";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "sel";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 0;
- CHILDREN = 5, 6;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "sel[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 5;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "sel[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 6;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataOut";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 7;
- TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo_modelsim.xrf b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo_modelsim.xrf
deleted file mode 100644
index 29c6b93..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo_modelsim.xrf
+++ /dev/null
@@ -1,17 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/db/Mux4_1Demo.cbx.xml
-design_name = Mux4_1
-instance = comp, \dataOut~output\, dataOut~output, Mux4_1, 1
-instance = comp, \dataIn2~input\, dataIn2~input, Mux4_1, 1
-instance = comp, \sel[1]~input\, sel[1]~input, Mux4_1, 1
-instance = comp, \dataIn1~input\, dataIn1~input, Mux4_1, 1
-instance = comp, \sel[0]~input\, sel[0]~input, Mux4_1, 1
-instance = comp, \dataIn0~input\, dataIn0~input, Mux4_1, 1
-instance = comp, \dataOut~0\, dataOut~0, Mux4_1, 1
-instance = comp, \dataIn3~input\, dataIn3~input, Mux4_1, 1
-instance = comp, \dataOut~1\, dataOut~1, Mux4_1, 1
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/transcript
deleted file mode 100644
index 391ee0d..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/transcript
+++ /dev/null
@@ -1,43 +0,0 @@
-# do Mux4_1Demo.do
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 22:35:04 on Mar 07,2023
-# vcom -work work Mux4_1Demo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity Mux4_1
-# -- Compiling architecture structure of Mux4_1
-# End time: 22:35:05 on Mar 07,2023, Elapsed time: 0:00:01
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 22:35:05 on Mar 07,2023
-# vcom -work work Mux4_1.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity Mux4_1_vhd_vec_tst
-# -- Compiling architecture Mux4_1_arch of Mux4_1_vhd_vec_tst
-# End time: 22:35:05 on Mar 07,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux4_1_vhd_vec_tst
-# Start time: 22:35:05 on Mar 07,2023
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading work.mux4_1_vhd_vec_tst(mux4_1_arch)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading cycloneive.cycloneive_atom_pack(body)
-# Loading cycloneive.cycloneive_components
-# Loading work.mux4_1(structure)
-# Loading ieee.std_logic_arith(body)
-# Loading cycloneive.cycloneive_io_obuf(arch)
-# Loading cycloneive.cycloneive_io_ibuf(arch)
-# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#29
-# End time: 22:35:05 on Mar 07,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/vwf_sim_transcript
deleted file mode 100644
index 1edc505..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/vwf_sim_transcript
+++ /dev/null
@@ -1,69 +0,0 @@
-Determining the location of the ModelSim executable...
-
-Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
-
-To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
-Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
-
-**** Generating the ModelSim Testbench ****
-
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux4_1Demo -c Mux4_1Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1.vwf.vht"
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Mar 7 22:35:03 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux4_1Demo -c Mux4_1Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1.vwf.vhtInfo (119006): Selected device EP4CE115F29C7 for design "Mux4_1Demo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Completed successfully.
-
-**** Generating the functional simulation netlist ****
-
-quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/" Mux4_1Demo -c Mux4_1Demo
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Mar 7 22:35:04 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/ Mux4_1Demo -c Mux4_1DemoInfo (119006): Selected device EP4CE115F29C7 for design "Mux4_1Demo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file Mux4_1Demo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 615 megabytes Info: Processing ended: Tue Mar 7 22:35:04 2023 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00
-Completed successfully.
-
-**** Generating the ModelSim .do script ****
-
-/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.do generated.
-
-Completed successfully.
-
-**** Running the ModelSim simulation ****
-
-/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do Mux4_1Demo.do
-
-Reading pref.tcl
-# 2020.1
-# do Mux4_1Demo.do
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 22:35:04 on Mar 07,2023# vcom -work work Mux4_1Demo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity Mux4_1
-# -- Compiling architecture structure of Mux4_1
-# End time: 22:35:05 on Mar 07,2023, Elapsed time: 0:00:01# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020# Start time: 22:35:05 on Mar 07,2023# vcom -work work Mux4_1.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO# -- Loading package std_logic_1164
-# -- Compiling entity Mux4_1_vhd_vec_tst# -- Compiling architecture Mux4_1_arch of Mux4_1_vhd_vec_tst
-# End time: 22:35:05 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux4_1_vhd_vec_tst # Start time: 22:35:05 on Mar 07,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.mux4_1_vhd_vec_tst(mux4_1_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.mux4_1(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#29
-# End time: 22:35:05 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-Completed successfully.
-
-**** Converting ModelSim VCD to vector waveform ****
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vwf...
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo.msim.vcd...
-
-Processing channel transitions...
-
-Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1Demo_20230307223505.sim.vwf
-
-Finished VCD to VWF conversion.
-
-Completed successfully.
-
-All completed.
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_info
deleted file mode 100644
index 4318504..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_info
+++ /dev/null
@@ -1,101 +0,0 @@
-m255
-K4
-z2
-!s11e vcom 2020.1 2020.02, Feb 28 2020
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-Z0 d/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim
-Emux4_1
-Z1 w1678228504
-Z2 DPx4 ieee 16 vital_primitives 0 22 G>kiXP8Q9dRClKfK1Zn7j1
-Z3 DPx10 cycloneive 20 cycloneive_atom_pack 0 22 WOh:M[al;oVzG5c`D0
-Z4 DPx4 ieee 12 vital_timing 0 22 J>EBealN09f8GzldA[z2>3
-Z5 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
-Z6 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
-Z7 DPx10 cycloneive 21 cycloneive_components 0 22 zGMDhP>8e@2k@f0eVT0<1@8J8[1
-Z10 OV;C;2020.1;71
-32
-Z11 !s110 1678228505
-!i10b 1
-Z12 !s108 1678228504.000000
-Z13 !s90 -work|work|Mux4_1Demo.vho|
-Z14 !s107 Mux4_1Demo.vho|
-!i113 1
-Z15 o-work work
-Z16 tExplicit 1 CvgOpt 0
-Astructure
-R2
-R3
-R4
-R5
-R6
-R7
-DEx4 work 6 mux4_1 0 22 YGI@ZjnT?zOD0EbzH5`8Q2
-!i122 0
-l72
-L46 143
-VGNNck749CA77`k@XZfiFO0
-!s100 [@8K?0cdjMn]9]4oaM;=@1
-R10
-32
-R11
-!i10b 1
-R12
-R13
-R14
-!i113 1
-R15
-R16
-Emux4_1_vhd_vec_tst
-Z17 w1678228503
-R5
-R6
-!i122 1
-R0
-Z18 8Mux4_1.vwf.vht
-Z19 FMux4_1.vwf.vht
-l0
-L32 1
-V@Szo0?X_FVCMARINhh;MZ2
-!s100 WSV9]BM1S][3HCkaB[Rn42
-R10
-32
-R11
-!i10b 1
-Z20 !s108 1678228505.000000
-Z21 !s90 -work|work|Mux4_1.vwf.vht|
-!s107 Mux4_1.vwf.vht|
-!i113 1
-R15
-R16
-Amux4_1_arch
-R5
-R6
-DEx4 work 18 mux4_1_vhd_vec_tst 0 22 @Szo0?X_FVCMARINhh;MZ2
-!i122 1
-l53
-L34 102
-VKFXM<1;?4UNO7U6?CIAck2
-!s100 1Mcb^KAPDbIdHeX29oSzB3
-R10
-32
-R11
-!i10b 1
-R20
-R21
-Z22 !s107 Mux4_1.vwf.vht|
-!i113 1
-R15
-R16
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_lib.qdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_lib.qdb
deleted file mode 100644
index 32df8a1..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_lib.qdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_lib1_0.qdb b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_lib1_0.qdb
deleted file mode 100644
index f2e93d8..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_lib1_0.qdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_lib1_0.qpg b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_lib1_0.qpg
deleted file mode 100644
index 69d833c..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_lib1_0.qpg and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_lib1_0.qtl b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_lib1_0.qtl
deleted file mode 100644
index 66cbb00..0000000
Binary files a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_lib1_0.qtl and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_vmake b/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_vmake
deleted file mode 100644
index 37aa36a..0000000
--- a/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/work/_vmake
+++ /dev/null
@@ -1,4 +0,0 @@
-m255
-K4
-z0
-cModel Technology
diff --git a/1ano/2semestre/lsd/pratica02/part1/Dec2_4En.vhd.bak b/1ano/2semestre/lsd/pratica02/part1/Dec2_4En.vhd.bak
deleted file mode 100644
index 2063208..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/Dec2_4En.vhd.bak
+++ /dev/null
@@ -1,18 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity Dec2_4En is
- port (
- enable : in std_logic;
- inputs : in std_logic_vector(1 downto 0);
- outputs : out std_logic_vector(3 downto 0)
- );
-end Dec2_4En;
-
-architecture BehavEquations of Dec2_4En is
-begin
- outputs(0) <= enable and (not inputs(1)) and (not inputs(1));
- outputs(1) <= enable and (not inputs(1)) and ( inputs(1));
- outputs(2) <= enable and ( inputs(1)) and (not inputs(1));
- outputs(3) <= enable and ( inputs(1)) and ( inputs(1));
-end BehavEquations;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.qpf b/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.qpf
deleted file mode 100644
index be06e6c..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 10:11:24 March 01, 2023
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "20.1"
-DATE = "10:11:24 March 01, 2023"
-
-# Revisions
-
-PROJECT_REVISION = "Dec2_4EnDemo"
diff --git a/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.qsf b/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.qsf
deleted file mode 100644
index 27361bd..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.qsf
+++ /dev/null
@@ -1,583 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 10:11:24 March 01, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# Dec2_4EnDemo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY Dec2_4EnDemo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:11:24 MARCH 01, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VHDL_FILE Dec2_4En.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE Dec2_4En_1.vwf
-set_global_assignment -name VHDL_FILE Dec2_4EnDemo.vhd
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.qsf.bak b/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.qsf.bak
deleted file mode 100644
index 6ed420c..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.qsf.bak
+++ /dev/null
@@ -1,64 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 10:11:24 March 01, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# Dec2_4EnDemo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY Dec2_4EnDemo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:11:24 MARCH 01, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VHDL_FILE Dec2_4En.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE Dec2_4En_1.vwf
-set_global_assignment -name VHDL_FILE Dec2_4EnDemo.vhd
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.qws b/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.qws
deleted file mode 100644
index 3234fa2..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.qws and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.vhd.bak b/1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.vhd.bak
deleted file mode 100644
index e69de29..0000000
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.(0).cnf.cdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.(0).cnf.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.(0).cnf.hdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.(0).cnf.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.(1).cnf.cdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.(1).cnf.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.(1).cnf.hdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.(1).cnf.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.(2).cnf.cdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.(2).cnf.cdb
deleted file mode 100644
index 0001095..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.(2).cnf.hdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.(2).cnf.hdb
deleted file mode 100644
index b9f21c8..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.asm.qmsg b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.asm.qmsg
deleted file mode 100644
index fbc04ab..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.asm.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677674792716 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677674792717 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 1 12:46:32 2023 " "Processing started: Wed Mar 1 12:46:32 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677674792717 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1677674792717 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1677674792717 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1677674792844 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1677674794308 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1677674794372 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "368 " "Peak virtual memory: 368 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677674794552 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 1 12:46:34 2023 " "Processing ended: Wed Mar 1 12:46:34 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677674794552 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677674794552 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677674794552 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1677674794552 ""}
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.asm.rdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.asm.rdb
deleted file mode 100644
index 8ec0fd5..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.asm_labs.ddb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.asm_labs.ddb
deleted file mode 100644
index e3423ca..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.atom_map.nvd b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.atom_map.nvd
deleted file mode 100644
index 9e621db..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cbx.xml b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cbx.xml
deleted file mode 100644
index a660433..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp.bpm b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp.bpm
deleted file mode 100644
index 9297398..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp.cdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp.cdb
deleted file mode 100644
index 1064580..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp.hdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp.hdb
deleted file mode 100644
index a2997a6..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp.idb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp.idb
deleted file mode 100644
index 69ffd1f..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp.logdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp.logdb
deleted file mode 100644
index c55c56a..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp.logdb
+++ /dev/null
@@ -1,49 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;7;7;0;0;7;7;0;0;0;0;0;0;4;0;0;0;3;4;0;3;0;0;4;0;7;7;7;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,7;0;0;7;7;0;0;7;7;7;7;7;7;3;7;7;7;4;3;7;4;7;7;3;7;0;0;0;7;7,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp.rdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp.rdb
deleted file mode 100644
index 49bbe3f..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp_merge.kpt b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cmp_merge.kpt
deleted file mode 100644
index 7a3d115..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index 12d57d7..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
deleted file mode 100644
index 218eca7..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
deleted file mode 100644
index bea9e20..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.db_info b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.db_info
deleted file mode 100644
index 8b1f192..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Wed Mar 1 12:23:48 2023
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.eda.qmsg b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.eda.qmsg
deleted file mode 100644
index 98bb985..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677674796824 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677674796824 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 1 12:46:36 2023 " "Processing started: Wed Mar 1 12:46:36 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677674796824 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1677674796824 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1677674796824 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1677674796970 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "Dec2_4EnDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/modelsim/ simulation " "Generated file Dec2_4EnDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1677674796993 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677674797003 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 1 12:46:36 2023 " "Processing ended: Wed Mar 1 12:46:36 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677674797003 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677674797003 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677674797003 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1677674797003 ""}
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.fit.qmsg b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.fit.qmsg
deleted file mode 100644
index 3b152ee..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.fit.qmsg
+++ /dev/null
@@ -1,48 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1677674786457 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1677674786457 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "Dec2_4EnDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"Dec2_4EnDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1677674786459 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1677674786501 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1677674786501 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1677674786716 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1677674786718 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677674786749 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677674786749 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677674786749 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677674786749 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677674786749 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677674786749 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677674786749 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677674786749 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677674786749 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1677674786749 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/" { { 0 { 0 ""} 0 583 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677674786750 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/" { { 0 { 0 ""} 0 585 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677674786750 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/" { { 0 { 0 ""} 0 587 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677674786750 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/" { { 0 { 0 ""} 0 589 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677674786750 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/" { { 0 { 0 ""} 0 591 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1677674786750 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1677674786750 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1677674786751 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Dec2_4EnDemo.sdc " "Synopsys Design Constraints File file not found: 'Dec2_4EnDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1677674787200 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1677674787200 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1677674787201 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1677674787201 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1677674787201 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1677674787201 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1677674787202 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1677674787203 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1677674787203 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1677674787203 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1677674787204 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1677674787204 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1677674787204 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1677674787204 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1677674787204 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1677674787204 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1677674787204 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1677674787204 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1677674787213 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1677674787213 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677674787220 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1677674787222 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1677674788552 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677674788617 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1677674788642 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1677674788784 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677674788784 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1677674788893 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y61 X115_Y73 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y61 to location X115_Y73" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y61 to location X115_Y73"} { { 12 { 0 ""} 104 61 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1677674790760 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1677674790760 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1677674790864 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1677674790864 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1677674790864 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677674790865 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1677674790931 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1677674790936 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1677674791080 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1677674791080 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1677674791213 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677674791424 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1677674791572 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/output_files/Dec2_4EnDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/output_files/Dec2_4EnDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1677674791603 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 519 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 519 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1148 " "Peak virtual memory: 1148 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677674791715 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 1 12:46:31 2023 " "Processing ended: Wed Mar 1 12:46:31 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677674791715 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677674791715 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677674791715 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1677674791715 ""}
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.hier_info b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.hier_info
deleted file mode 100644
index 07261ac..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.hier_info
+++ /dev/null
@@ -1,27 +0,0 @@
-|Dec2_4EnDemo
-SW[0] => dec2_4en:system_core.inputs[0]
-SW[1] => dec2_4en:system_core.inputs[1]
-SW[2] => dec2_4en:system_core.enable
-LEDR[0] <= dec2_4en:system_core.outputs[0]
-LEDR[1] <= dec2_4en:system_core.outputs[1]
-LEDR[2] <= dec2_4en:system_core.outputs[2]
-LEDR[3] <= dec2_4en:system_core.outputs[3]
-
-
-|Dec2_4EnDemo|Dec2_4En:system_core
-enable => outputs.OUTPUTSELECT
-enable => outputs.OUTPUTSELECT
-enable => outputs.OUTPUTSELECT
-enable => outputs.OUTPUTSELECT
-inputs[0] => Equal0.IN1
-inputs[0] => Equal1.IN1
-inputs[0] => Equal2.IN0
-inputs[1] => Equal0.IN0
-inputs[1] => Equal1.IN0
-inputs[1] => Equal2.IN1
-outputs[0] <= outputs.DB_MAX_OUTPUT_PORT_TYPE
-outputs[1] <= outputs.DB_MAX_OUTPUT_PORT_TYPE
-outputs[2] <= outputs.DB_MAX_OUTPUT_PORT_TYPE
-outputs[3] <= outputs.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.hif b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.hif
deleted file mode 100644
index cbcd7e1..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.lpc.html b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.lpc.html
deleted file mode 100644
index c24705c..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.lpc.html
+++ /dev/null
@@ -1,34 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| system_core |
-3 |
-0 |
-0 |
-0 |
-4 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.lpc.rdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.lpc.rdb
deleted file mode 100644
index b75fec1..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.lpc.txt b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.lpc.txt
deleted file mode 100644
index 2398c0e..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.lpc.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; system_core ; 3 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.ammdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.ammdb
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.bpm b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.bpm
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.cdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.cdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.hdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.hdb
deleted file mode 100644
index 91f0563..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.kpt b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.kpt
deleted file mode 100644
index 37121ff..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.logdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.qmsg b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.qmsg
deleted file mode 100644
index dc436fe..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.qmsg
+++ /dev/null
@@ -1,13 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677674780626 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677674780626 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 1 12:46:20 2023 " "Processing started: Wed Mar 1 12:46:20 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677674780626 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674780626 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674780626 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1677674780758 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1677674780758 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Dec2_4En.vhd 4 1 " "Found 4 design units, including 1 entities, in source file Dec2_4En.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Dec2_4En-BehavEquations " "Found design unit 1: Dec2_4En-BehavEquations" { } { { "Dec2_4En.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674785314 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 Dec2_4En-BehavAssign " "Found design unit 2: Dec2_4En-BehavAssign" { } { { "Dec2_4En.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd" 20 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674785314 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 Dec2_4En-BehavProc " "Found design unit 3: Dec2_4En-BehavProc" { } { { "Dec2_4En.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd" 29 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674785314 ""} { "Info" "ISGN_ENTITY_NAME" "1 Dec2_4En " "Found entity 1: Dec2_4En" { } { { "Dec2_4En.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674785314 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674785314 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Dec2_4EnDemo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Dec2_4EnDemo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Dec2_4EnDemo-Shell " "Found design unit 1: Dec2_4EnDemo-Shell" { } { { "Dec2_4EnDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674785315 ""} { "Info" "ISGN_ENTITY_NAME" "1 Dec2_4EnDemo " "Found entity 1: Dec2_4EnDemo" { } { { "Dec2_4EnDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674785315 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674785315 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "Dec2_4EnDemo " "Elaborating entity \"Dec2_4EnDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1677674785339 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "Dec2_4En Dec2_4En:system_core A:behavproc " "Elaborating entity \"Dec2_4En\" using architecture \"A:behavproc\" for hierarchy \"Dec2_4En:system_core\"" { } { { "Dec2_4EnDemo.vhd" "system_core" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd" 14 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1677674785342 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1677674785652 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1677674785940 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1677674785940 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "11 " "Implemented 11 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1677674785955 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1677674785955 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1677674785955 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1677674785955 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "429 " "Peak virtual memory: 429 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677674785958 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 1 12:46:25 2023 " "Processing ended: Wed Mar 1 12:46:25 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677674785958 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677674785958 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677674785958 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674785958 ""}
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.rdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map.rdb
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index c613549..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map_bb.cdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map_bb.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map_bb.hdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map_bb.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map_bb.logdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.npp.qmsg b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.npp.qmsg
deleted file mode 100644
index 878beb7..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.npp.qmsg
+++ /dev/null
@@ -1,5 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677673736306 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677673736306 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 1 12:28:56 2023 " "Processing started: Wed Mar 1 12:28:56 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677673736306 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1677673736306 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp Dec2_4EnDemo -c Dec2_4EnDemo --netlist_type=atom_map " "Command: quartus_npp Dec2_4EnDemo -c Dec2_4EnDemo --netlist_type=atom_map" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1677673736306 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1677673736355 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1 Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "522 " "Peak virtual memory: 522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677673736373 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 1 12:28:56 2023 " "Processing ended: Wed Mar 1 12:28:56 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677673736373 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677673736373 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677673736373 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1677673736373 ""}
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.pre_map.hdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.root_partition.map.reg_db.cdb
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.routing.rdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.rtlv.hdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sgate.nvd b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sgate.nvd
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sld_design_entry.sci b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.smart_action.txt b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.smart_action.txt
deleted file mode 100644
index c8e8a13..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sta.qmsg b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sta.qmsg
deleted file mode 100644
index fc64e9f..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677674795501 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677674795502 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 1 12:46:35 2023 " "Processing started: Wed Mar 1 12:46:35 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677674795502 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1677674795502 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Dec2_4EnDemo -c Dec2_4EnDemo " "Command: quartus_sta Dec2_4EnDemo -c Dec2_4EnDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1677674795502 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1677674795523 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1677674795579 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1677674795579 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677674795621 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677674795621 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Dec2_4EnDemo.sdc " "Synopsys Design Constraints File file not found: 'Dec2_4EnDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1677674795925 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1677674795925 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1677674795925 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1677674795925 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1677674795925 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1677674795925 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1677674795926 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1677674795928 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1677674795929 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674795929 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674795931 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674795931 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674795931 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674795932 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674795932 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1677674795933 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1677674795947 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1677674796101 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1677674796112 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1677674796112 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1677674796112 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1677674796112 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674796113 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674796113 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674796114 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674796114 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674796114 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674796114 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1677674796116 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1677674796152 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1677674796152 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1677674796152 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1677674796152 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674796153 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674796153 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674796153 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674796154 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677674796154 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677674796358 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677674796358 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "537 " "Peak virtual memory: 537 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677674796367 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 1 12:46:36 2023 " "Processing ended: Wed Mar 1 12:46:36 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677674796367 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677674796367 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677674796367 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1677674796367 ""}
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sta.rdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sta.rdb
deleted file mode 100644
index 223438b..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sta_cmp.7_slow_1200mv_85c.tdb
deleted file mode 100644
index e0baa4e..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.sta_cmp.7_slow_1200mv_85c.tdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.tis_db_list.ddb
deleted file mode 100644
index 73e5ec9..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.tis_db_list.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index e4931d7..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index ed88ab2..0000000
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diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index e8a59d9..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.tmw_info b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.tmw_info
deleted file mode 100644
index 3079a8b..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.tmw_info
+++ /dev/null
@@ -1,7 +0,0 @@
-start_full_compilation:s:00:00:17
-start_analysis_synthesis:s:00:00:06-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:06-start_full_compilation
-start_assembler:s:00:00:03-start_full_compilation
-start_timing_analyzer:s:00:00:01-start_full_compilation
-start_eda_netlist_writer:s:00:00:01-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.vpr.ammdb b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.vpr.ammdb
deleted file mode 100644
index bb97875..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo_partition_pins.json b/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo_partition_pins.json
deleted file mode 100644
index f61408d..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/Dec2_4EnDemo_partition_pins.json
+++ /dev/null
@@ -1,37 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "LEDR[0]",
- "strict" : false
- },
- {
- "name" : "LEDR[1]",
- "strict" : false
- },
- {
- "name" : "LEDR[2]",
- "strict" : false
- },
- {
- "name" : "LEDR[3]",
- "strict" : false
- },
- {
- "name" : "SW[2]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/part1/db/prev_cmp_Dec2_4EnDemo.qmsg b/1ano/2semestre/lsd/pratica02/part1/db/prev_cmp_Dec2_4EnDemo.qmsg
deleted file mode 100644
index 8caefed..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/db/prev_cmp_Dec2_4EnDemo.qmsg
+++ /dev/null
@@ -1,12 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677674699092 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677674699092 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 1 12:44:59 2023 " "Processing started: Wed Mar 1 12:44:59 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677674699092 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674699092 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674699092 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1677674699213 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1677674699213 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Dec2_4En.vhd 4 1 " "Found 4 design units, including 1 entities, in source file Dec2_4En.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Dec2_4En-BehavEquations " "Found design unit 1: Dec2_4En-BehavEquations" { } { { "Dec2_4En.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674703821 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 Dec2_4En-BehavAssign " "Found design unit 2: Dec2_4En-BehavAssign" { } { { "Dec2_4En.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd" 20 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674703821 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 Dec2_4En-BehavProc " "Found design unit 3: Dec2_4En-BehavProc" { } { { "Dec2_4En.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd" 29 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674703821 ""} { "Info" "ISGN_ENTITY_NAME" "1 Dec2_4En " "Found entity 1: Dec2_4En" { } { { "Dec2_4En.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674703821 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674703821 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Dec2_4EnDemo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Dec2_4EnDemo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Dec2_4EnDemo-Shell " "Found design unit 1: Dec2_4EnDemo-Shell" { } { { "Dec2_4EnDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674703821 ""} { "Info" "ISGN_ENTITY_NAME" "1 Dec2_4EnDemo " "Found entity 1: Dec2_4EnDemo" { } { { "Dec2_4EnDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674703821 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674703821 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "Dec2_4En " "Elaborating entity \"Dec2_4En\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1677674703846 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1677674704159 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1677674704444 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1677674704444 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "11 " "Implemented 11 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1677674704459 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1677674704459 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1677674704459 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1677674704459 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "428 " "Peak virtual memory: 428 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677674704462 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 1 12:45:04 2023 " "Processing ended: Wed Mar 1 12:45:04 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677674704462 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677674704462 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677674704462 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674704462 ""}
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/README b/1ano/2semestre/lsd/pratica02/part1/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.db_info b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.db_info
deleted file mode 100644
index 908b4f6..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Wed Mar 1 10:20:48 2023
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.ammdb
deleted file mode 100644
index 16f63d9..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.cdb
deleted file mode 100644
index fef9c7c..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.dfp and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.hdb
deleted file mode 100644
index 5b6725d..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.rcfdb
deleted file mode 100644
index 042f3ec..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.cmp.rcfdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.cdb
deleted file mode 100644
index f136701..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.dpi
deleted file mode 100644
index d473ae2..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.dpi and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hbdb.cdb
deleted file mode 100644
index 32b7e90..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hbdb.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hbdb.hdb
deleted file mode 100644
index cf004cb..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hdb
deleted file mode 100644
index ea27aeb..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.kpt
deleted file mode 100644
index 25db0ec..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.root_partition.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.rrp.hdb b/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.rrp.hdb
deleted file mode 100644
index c090208..0000000
Binary files a/1ano/2semestre/lsd/pratica02/part1/incremental_db/compiled_partitions/Dec2_4EnDemo.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.asm.rpt b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.asm.rpt
deleted file mode 100644
index 85c9a4b..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for Dec2_4EnDemo
-Wed Mar 1 12:46:34 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: Dec2_4EnDemo.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Wed Mar 1 12:46:34 2023 ;
-; Revision Name ; Dec2_4EnDemo ;
-; Top-level Entity Name ; Dec2_4EnDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+------------------------------------------------------------------------------------------------+
-; File Name ;
-+------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/output_files/Dec2_4EnDemo.sof ;
-+------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------+
-; Assembler Device Options: Dec2_4EnDemo.sof ;
-+----------------+---------------------------+
-; Option ; Setting ;
-+----------------+---------------------------+
-; JTAG usercode ; 0x00563B4C ;
-; Checksum ; 0x00563B4C ;
-+----------------+---------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 1 12:46:32 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 368 megabytes
- Info: Processing ended: Wed Mar 1 12:46:34 2023
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.done b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.done
deleted file mode 100644
index 787fd5f..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.done
+++ /dev/null
@@ -1 +0,0 @@
-Wed Mar 1 12:46:37 2023
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.eda.rpt b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.eda.rpt
deleted file mode 100644
index 804683f..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.eda.rpt
+++ /dev/null
@@ -1,94 +0,0 @@
-EDA Netlist Writer report for Dec2_4EnDemo
-Wed Mar 1 12:46:36 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Wed Mar 1 12:46:36 2023 ;
-; Revision Name ; Dec2_4EnDemo ;
-; Top-level Entity Name ; Dec2_4EnDemo ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+-------------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+-------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/modelsim/Dec2_4EnDemo.vho ;
-+-------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 1 12:46:36 2023
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file Dec2_4EnDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 612 megabytes
- Info: Processing ended: Wed Mar 1 12:46:36 2023
- Info: Elapsed time: 00:00:00
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.fit.rpt b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.fit.rpt
deleted file mode 100644
index c594e82..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.fit.rpt
+++ /dev/null
@@ -1,2528 +0,0 @@
-Fitter report for Dec2_4EnDemo
-Wed Mar 1 12:46:31 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Wed Mar 1 12:46:31 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; Dec2_4EnDemo ;
-; Top-level Entity Name ; Dec2_4EnDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 4 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 4 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 7 / 529 ( 1 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; CLOCK_50 ; PIN_Y2 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
-; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
-; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
-; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
-; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
-; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
-; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[0] ; PIN_M23 ; QSF Assignment ;
-; Location ; ; ; KEY[1] ; PIN_M21 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[0] ; PIN_E21 ; QSF Assignment ;
-; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
-; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
-; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[4] ; PIN_F18 ; QSF Assignment ;
-; Location ; ; ; LEDR[5] ; PIN_E18 ; QSF Assignment ;
-; Location ; ; ; LEDR[6] ; PIN_J19 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_H19 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; SW[10] ; PIN_AC24 ; QSF Assignment ;
-; Location ; ; ; SW[11] ; PIN_AB24 ; QSF Assignment ;
-; Location ; ; ; SW[12] ; PIN_AB23 ; QSF Assignment ;
-; Location ; ; ; SW[13] ; PIN_AA24 ; QSF Assignment ;
-; Location ; ; ; SW[14] ; PIN_AA23 ; QSF Assignment ;
-; Location ; ; ; SW[15] ; PIN_AA22 ; QSF Assignment ;
-; Location ; ; ; SW[16] ; PIN_Y24 ; QSF Assignment ;
-; Location ; ; ; SW[17] ; PIN_Y23 ; QSF Assignment ;
-; Location ; ; ; SW[3] ; PIN_AD27 ; QSF Assignment ;
-; Location ; ; ; SW[4] ; PIN_AB27 ; QSF Assignment ;
-; Location ; ; ; SW[5] ; PIN_AC26 ; QSF Assignment ;
-; Location ; ; ; SW[6] ; PIN_AD26 ; QSF Assignment ;
-; Location ; ; ; SW[7] ; PIN_AB26 ; QSF Assignment ;
-; Location ; ; ; SW[8] ; PIN_AC25 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AB25 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 29 ) ; 0.00 % ( 0 / 29 ) ; 0.00 % ( 0 / 29 ) ;
-; -- Achieved ; 0.00 % ( 0 / 29 ) ; 0.00 % ( 0 / 29 ) ; 0.00 % ( 0 / 29 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 19 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/output_files/Dec2_4EnDemo.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+-----------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-----------------------+
-; Total logic elements ; 4 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 4 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 4 ;
-; -- <=2 input functions ; 0 ;
-; -- Register only ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 4 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers* ; 0 / 117,053 ( 0 % ) ;
-; -- Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 1 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 7 / 529 ( 1 % ) ;
-; -- Clock pins ; 0 / 7 ( 0 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.3% ;
-; Maximum fan-out ; 4 ;
-; Highest non-global fan-out ; 4 ;
-; Total fan-out ; 28 ;
-; Average fan-out ; 1.00 ;
-+---------------------------------------------+-----------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 4 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 4 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 0 ; 0 ;
-; -- 3 input functions ; 4 ; 0 ;
-; -- <=2 input functions ; 0 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 4 ; 0 ;
-; -- arithmetic mode ; 0 ; 0 ;
-; ; ; ;
-; Total registers ; 0 ; 0 ;
-; -- Dedicated logic registers ; 0 / 114480 ( 0 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 1 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 7 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 23 ; 5 ;
-; -- Registered Connections ; 0 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 3 ; 0 ;
-; -- Output Ports ; 4 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+----------------------+--------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[2] ; E19 ; 7 ; 94 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[3] ; F21 ; 7 ; 107 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+----------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+----------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+----------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 0 / 63 ( 0 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 3 / 65 ( 5 % ) ; 2.5V ; -- ;
-; 6 ; 1 / 58 ( 2 % ) ; 2.5V ; -- ;
-; 7 ; 4 / 72 ( 6 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+----------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA23 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA24 ; 279 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB24 ; 274 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB25 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB26 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB27 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC25 ; 272 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC26 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD27 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 421 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y24 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; LEDR[0] ; Incomplete set of assignments ;
-; LEDR[1] ; Incomplete set of assignments ;
-; LEDR[2] ; Incomplete set of assignments ;
-; LEDR[3] ; Incomplete set of assignments ;
-; SW[2] ; Incomplete set of assignments ;
-; SW[1] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------+--------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------+--------------+--------------+
-; |Dec2_4EnDemo ; 4 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 4 (0) ; 0 (0) ; 0 (0) ; |Dec2_4EnDemo ; Dec2_4EnDemo ; work ;
-; |Dec2_4En:system_core| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; |Dec2_4EnDemo|Dec2_4En:system_core ; Dec2_4En ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------+--------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-----------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+------------------------------------------+-------------------+---------+
-; SW[2] ; ; ;
-; - Dec2_4En:system_core|outputs[0]~0 ; 1 ; 6 ;
-; - Dec2_4En:system_core|outputs[1]~1 ; 1 ; 6 ;
-; - Dec2_4En:system_core|outputs[2]~2 ; 1 ; 6 ;
-; - Dec2_4En:system_core|outputs[3]~3 ; 1 ; 6 ;
-; SW[1] ; ; ;
-; - Dec2_4En:system_core|outputs[0]~0 ; 0 ; 6 ;
-; - Dec2_4En:system_core|outputs[1]~1 ; 0 ; 6 ;
-; - Dec2_4En:system_core|outputs[2]~2 ; 0 ; 6 ;
-; - Dec2_4En:system_core|outputs[3]~3 ; 0 ; 6 ;
-; SW[0] ; ; ;
-; - Dec2_4En:system_core|outputs[0]~0 ; 0 ; 6 ;
-; - Dec2_4En:system_core|outputs[1]~1 ; 0 ; 6 ;
-; - Dec2_4En:system_core|outputs[2]~2 ; 0 ; 6 ;
-; - Dec2_4En:system_core|outputs[3]~3 ; 0 ; 6 ;
-+------------------------------------------+-------------------+---------+
-
-
-+------------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+------------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+------------------------+
-; Block interconnects ; 7 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 12 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 4 / 209,544 ( < 1 % ) ;
-; Direct links ; 0 / 342,891 ( 0 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 0 / 119,088 ( 0 % ) ;
-; R24 interconnects ; 5 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 12 / 289,782 ( < 1 % ) ;
-+-----------------------+------------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 4.00) ; Number of LABs (Total = 1) ;
-+--------------------------------------------+-----------------------------+
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 1 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-+--------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 4.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 4.00) ; Number of LABs (Total = 1) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 1 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 3.00) ; Number of LABs (Total = 1) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 7 ; 7 ; 0 ; 0 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 3 ; 4 ; 0 ; 3 ; 0 ; 0 ; 4 ; 0 ; 7 ; 7 ; 7 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 7 ; 0 ; 0 ; 7 ; 7 ; 0 ; 0 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 3 ; 7 ; 7 ; 7 ; 4 ; 3 ; 7 ; 4 ; 7 ; 7 ; 3 ; 7 ; 0 ; 0 ; 0 ; 7 ; 7 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "Dec2_4EnDemo"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'Dec2_4EnDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y61 to location X115_Y73
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/output_files/Dec2_4EnDemo.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 519 warnings
- Info: Peak virtual memory: 1148 megabytes
- Info: Processing ended: Wed Mar 1 12:46:31 2023
- Info: Elapsed time: 00:00:05
- Info: Total CPU time (on all processors): 00:00:08
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/output_files/Dec2_4EnDemo.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.fit.smsg b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.fit.summary b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.fit.summary
deleted file mode 100644
index 77fdb5f..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Wed Mar 1 12:46:31 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : Dec2_4EnDemo
-Top-level Entity Name : Dec2_4EnDemo
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 4 / 114,480 ( < 1 % )
- Total combinational functions : 4 / 114,480 ( < 1 % )
- Dedicated logic registers : 0 / 114,480 ( 0 % )
-Total registers : 0
-Total pins : 7 / 529 ( 1 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.flow.rpt b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.flow.rpt
deleted file mode 100644
index 5b1d289..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.flow.rpt
+++ /dev/null
@@ -1,134 +0,0 @@
-Flow report for Dec2_4EnDemo
-Wed Mar 1 12:46:36 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Wed Mar 1 12:46:36 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; Dec2_4EnDemo ;
-; Top-level Entity Name ; Dec2_4EnDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 4 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 4 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 7 / 529 ( 1 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/01/2023 12:46:20 ;
-; Main task ; Compilation ;
-; Revision Name ; Dec2_4EnDemo ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 198516037997543.167767478011951 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 429 MB ; 00:00:12 ;
-; Fitter ; 00:00:05 ; 1.0 ; 1148 MB ; 00:00:08 ;
-; Assembler ; 00:00:02 ; 1.0 ; 368 MB ; 00:00:02 ;
-; Timing Analyzer ; 00:00:01 ; 1.0 ; 537 MB ; 00:00:01 ;
-; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 612 MB ; 00:00:00 ;
-; Total ; 00:00:13 ; -- ; -- ; 00:00:23 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo
-quartus_fit --read_settings_files=off --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo
-quartus_asm --read_settings_files=off --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo
-quartus_sta Dec2_4EnDemo -c Dec2_4EnDemo
-quartus_eda --read_settings_files=off --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.jdi b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.jdi
deleted file mode 100644
index 692c04f..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.map.rpt b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.map.rpt
deleted file mode 100644
index 29f4f9a..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.map.rpt
+++ /dev/null
@@ -1,290 +0,0 @@
-Analysis & Synthesis report for Dec2_4EnDemo
-Wed Mar 1 12:46:25 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Post-Synthesis Netlist Statistics for Top Partition
- 10. Elapsed Time Per Partition
- 11. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Wed Mar 1 12:46:25 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; Dec2_4EnDemo ;
-; Top-level Entity Name ; Dec2_4EnDemo ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 4 ;
-; Total combinational functions ; 4 ;
-; Dedicated logic registers ; 0 ;
-; Total registers ; 0 ;
-; Total pins ; 7 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; Dec2_4EnDemo ; Dec2_4EnDemo ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+---------+
-; Dec2_4En.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd ; ;
-; Dec2_4EnDemo.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd ; ;
-+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+---------+
-
-
-+-----------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+-------------+
-; Resource ; Usage ;
-+---------------------------------------------+-------------+
-; Estimated Total logic elements ; 4 ;
-; ; ;
-; Total combinational functions ; 4 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 4 ;
-; -- <=2 input functions ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 4 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers ; 0 ;
-; -- Dedicated logic registers ; 0 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 7 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; SW[2]~input ;
-; Maximum fan-out ; 4 ;
-; Total fan-out ; 23 ;
-; Average fan-out ; 1.28 ;
-+---------------------------------------------+-------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------+--------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------+--------------+--------------+
-; |Dec2_4EnDemo ; 4 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; |Dec2_4EnDemo ; Dec2_4EnDemo ; work ;
-; |Dec2_4En:system_core| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Dec2_4EnDemo|Dec2_4En:system_core ; Dec2_4En ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------+--------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 0 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 7 ;
-; cycloneiii_lcell_comb ; 4 ;
-; normal ; 4 ;
-; 3 data inputs ; 4 ;
-; ; ;
-; Max LUT depth ; 1.00 ;
-; Average LUT depth ; 1.00 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 1 12:46:20 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 4 design units, including 1 entities, in source file Dec2_4En.vhd
- Info (12022): Found design unit 1: Dec2_4En-BehavEquations File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd Line: 12
- Info (12022): Found design unit 2: Dec2_4En-BehavAssign File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd Line: 20
- Info (12022): Found design unit 3: Dec2_4En-BehavProc File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd Line: 29
- Info (12023): Found entity 1: Dec2_4En File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd Line: 4
-Info (12021): Found 2 design units, including 1 entities, in source file Dec2_4EnDemo.vhd
- Info (12022): Found design unit 1: Dec2_4EnDemo-Shell File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd Line: 12
- Info (12023): Found entity 1: Dec2_4EnDemo File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd Line: 4
-Info (12127): Elaborating entity "Dec2_4EnDemo" for the top level hierarchy
-Info (12129): Elaborating entity "Dec2_4En" using architecture "A:behavproc" for hierarchy "Dec2_4En:system_core" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd Line: 14
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 11 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 3 input pins
- Info (21059): Implemented 4 output pins
- Info (21061): Implemented 4 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 429 megabytes
- Info: Processing ended: Wed Mar 1 12:46:25 2023
- Info: Elapsed time: 00:00:05
- Info: Total CPU time (on all processors): 00:00:12
-
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.map.summary b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.map.summary
deleted file mode 100644
index 1b4fcdd..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Wed Mar 1 12:46:25 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : Dec2_4EnDemo
-Top-level Entity Name : Dec2_4EnDemo
-Family : Cyclone IV E
-Total logic elements : 4
- Total combinational functions : 4
- Dedicated logic registers : 0
-Total registers : 0
-Total pins : 7
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.pin b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.pin
deleted file mode 100644
index f5dbfa2..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "Dec2_4EnDemo" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5 :
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC26 : : : : 5 :
-SW[2] : AC27 : input : 2.5 V : : 5 : Y
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7 :
-LEDR[2] : E19 : output : 2.5 V : : 7 : Y
-VCCIO7 : E20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
-VCCIO7 : E23 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7 :
-LEDR[1] : F19 : output : 2.5 V : : 7 : Y
-GND : F20 : gnd : : : :
-LEDR[3] : F21 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
-LEDR[0] : G19 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
-VCCIO7 : H18 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7 :
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6 :
-MSEL2 : M22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-GND+ : Y2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.sld b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.sta.rpt b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.sta.rpt
deleted file mode 100644
index fd08a50..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.sta.rpt
+++ /dev/null
@@ -1,452 +0,0 @@
-Timing Analyzer report for Dec2_4EnDemo
-Wed Mar 1 12:46:36 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Unconstrained Input Ports
- 37. Unconstrained Output Ports
- 38. Unconstrained Input Ports
- 39. Unconstrained Output Ports
- 40. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; Dec2_4EnDemo ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.1% ;
-+----------------------------+-------------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 3 ; 3 ;
-; Unconstrained Input Port Paths ; 12 ; 12 ;
-; Unconstrained Output Ports ; 4 ; 4 ;
-; Unconstrained Output Port Paths ; 12 ; 12 ;
-+---------------------------------+-------+------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 1 12:46:35 2023
-Info: Command: quartus_sta Dec2_4EnDemo -c Dec2_4EnDemo
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'Dec2_4EnDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 537 megabytes
- Info: Processing ended: Wed Mar 1 12:46:36 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.sta.summary b/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.sta.summary
deleted file mode 100644
index aa5b327..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/output_files/Dec2_4EnDemo.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/modelsim/Dec2_4EnDemo.sft b/1ano/2semestre/lsd/pratica02/part1/simulation/modelsim/Dec2_4EnDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/modelsim/Dec2_4EnDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/modelsim/Dec2_4EnDemo.vho b/1ano/2semestre/lsd/pratica02/part1/simulation/modelsim/Dec2_4EnDemo.vho
deleted file mode 100644
index b389016..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/modelsim/Dec2_4EnDemo.vho
+++ /dev/null
@@ -1,293 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/01/2023 12:46:36"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY Dec2_4EnDemo IS
- PORT (
- SW : IN std_logic_vector(2 DOWNTO 0);
- LEDR : OUT std_logic_vector(3 DOWNTO 0)
- );
-END Dec2_4EnDemo;
-
--- Design Ports Information
--- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF Dec2_4EnDemo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_SW : std_logic_vector(2 DOWNTO 0);
-SIGNAL ww_LEDR : std_logic_vector(3 DOWNTO 0);
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \LEDR[1]~output_o\ : std_logic;
-SIGNAL \LEDR[2]~output_o\ : std_logic;
-SIGNAL \LEDR[3]~output_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[2]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \system_core|outputs[0]~0_combout\ : std_logic;
-SIGNAL \system_core|outputs[1]~1_combout\ : std_logic;
-SIGNAL \system_core|outputs[2]~2_combout\ : std_logic;
-SIGNAL \system_core|outputs[3]~3_combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-ww_SW <= SW;
-LEDR <= ww_LEDR;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X69_Y73_N16
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|outputs[0]~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N2
-\LEDR[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|outputs[1]~1_combout\,
- devoe => ww_devoe,
- o => \LEDR[1]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N9
-\LEDR[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|outputs[2]~2_combout\,
- devoe => ww_devoe,
- o => \LEDR[2]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N16
-\LEDR[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \system_core|outputs[3]~3_combout\,
- devoe => ww_devoe,
- o => \LEDR[3]~output_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N8
-\SW[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(2),
- o => \SW[2]~input_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: LCCOMB_X107_Y69_N0
-\system_core|outputs[0]~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|outputs[0]~0_combout\ = (!\SW[1]~input_o\ & (\SW[2]~input_o\ & !\SW[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[1]~input_o\,
- datac => \SW[2]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \system_core|outputs[0]~0_combout\);
-
--- Location: LCCOMB_X107_Y69_N2
-\system_core|outputs[1]~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|outputs[1]~1_combout\ = (!\SW[1]~input_o\ & (\SW[2]~input_o\ & \SW[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[1]~input_o\,
- datac => \SW[2]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \system_core|outputs[1]~1_combout\);
-
--- Location: LCCOMB_X107_Y69_N4
-\system_core|outputs[2]~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|outputs[2]~2_combout\ = (\SW[1]~input_o\ & (\SW[2]~input_o\ & !\SW[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000011000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[1]~input_o\,
- datac => \SW[2]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \system_core|outputs[2]~2_combout\);
-
--- Location: LCCOMB_X107_Y69_N14
-\system_core|outputs[3]~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \system_core|outputs[3]~3_combout\ = (\SW[1]~input_o\ & (\SW[2]~input_o\ & \SW[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[1]~input_o\,
- datac => \SW[2]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \system_core|outputs[3]~3_combout\);
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-
-ww_LEDR(1) <= \LEDR[1]~output_o\;
-
-ww_LEDR(2) <= \LEDR[2]~output_o\;
-
-ww_LEDR(3) <= \LEDR[3]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/modelsim/Dec2_4EnDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica02/part1/simulation/modelsim/Dec2_4EnDemo_modelsim.xrf
deleted file mode 100644
index 746fcd7..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/modelsim/Dec2_4EnDemo_modelsim.xrf
+++ /dev/null
@@ -1,22 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En_1.vwf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/db/Dec2_4EnDemo.cbx.xml
-design_name = hard_block
-design_name = Dec2_4EnDemo
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, Dec2_4EnDemo, 1
-instance = comp, \LEDR[1]~output\, LEDR[1]~output, Dec2_4EnDemo, 1
-instance = comp, \LEDR[2]~output\, LEDR[2]~output, Dec2_4EnDemo, 1
-instance = comp, \LEDR[3]~output\, LEDR[3]~output, Dec2_4EnDemo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, Dec2_4EnDemo, 1
-instance = comp, \SW[2]~input\, SW[2]~input, Dec2_4EnDemo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, Dec2_4EnDemo, 1
-instance = comp, \system_core|outputs[0]~0\, system_core|outputs[0]~0, Dec2_4EnDemo, 1
-instance = comp, \system_core|outputs[1]~1\, system_core|outputs[1]~1, Dec2_4EnDemo, 1
-instance = comp, \system_core|outputs[2]~2\, system_core|outputs[2]~2, Dec2_4EnDemo, 1
-instance = comp, \system_core|outputs[3]~3\, system_core|outputs[3]~3, Dec2_4EnDemo, 1
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo.do b/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo.do
deleted file mode 100644
index 6fec0fa..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo.do
+++ /dev/null
@@ -1,17 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vcom -work work Dec2_4EnDemo.vho
-vcom -work work Dec2_4En_1.vwf.vht
-vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4En_vhd_vec_tst
-vcd file -direction Dec2_4EnDemo.msim.vcd
-vcd add -internal Dec2_4En_vhd_vec_tst/*
-vcd add -internal Dec2_4En_vhd_vec_tst/i1/*
-proc simTimestamp {} {
- echo "Simulation time: $::now ps"
- if { [string equal running [runStatus]] } {
- after 2500 simTimestamp
- }
-}
-after 2500 simTimestamp
-run -all
-quit -f
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo.msim.vcd b/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo.msim.vcd
deleted file mode 100644
index 117f441..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo.msim.vcd
+++ /dev/null
@@ -1,1091 +0,0 @@
-$comment
- File created using the following command:
- vcd file Dec2_4EnDemo.msim.vcd -direction
-$end
-$date
- Wed Mar 1 10:28:41 2023
-$end
-$version
- ModelSim Version 2020.1
-$end
-$timescale
- 1ps
-$end
-
-$scope module dec2_4en_vhd_vec_tst $end
-$var wire 1 ! enable $end
-$var wire 1 " inputs [1] $end
-$var wire 1 # inputs [0] $end
-$var wire 1 $ outputs [3] $end
-$var wire 1 % outputs [2] $end
-$var wire 1 & outputs [1] $end
-$var wire 1 ' outputs [0] $end
-
-$scope module i1 $end
-$var wire 1 ( gnd $end
-$var wire 1 ) vcc $end
-$var wire 1 * unknown $end
-$var wire 1 + devoe $end
-$var wire 1 , devclrn $end
-$var wire 1 - devpor $end
-$var wire 1 . ww_devoe $end
-$var wire 1 / ww_devclrn $end
-$var wire 1 0 ww_devpor $end
-$var wire 1 1 ww_enable $end
-$var wire 1 2 ww_inputs [1] $end
-$var wire 1 3 ww_inputs [0] $end
-$var wire 1 4 ww_outputs [3] $end
-$var wire 1 5 ww_outputs [2] $end
-$var wire 1 6 ww_outputs [1] $end
-$var wire 1 7 ww_outputs [0] $end
-$var wire 1 8 \outputs[0]~output_o\ $end
-$var wire 1 9 \outputs[1]~output_o\ $end
-$var wire 1 : \outputs[2]~output_o\ $end
-$var wire 1 ; \outputs[3]~output_o\ $end
-$var wire 1 < \enable~input_o\ $end
-$var wire 1 = \inputs[1]~input_o\ $end
-$var wire 1 > \inputs[0]~input_o\ $end
-$var wire 1 ? \outputs~0_combout\ $end
-$var wire 1 @ \outputs~1_combout\ $end
-$var wire 1 A \outputs~2_combout\ $end
-$var wire 1 B \outputs~3_combout\ $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0!
-0(
-1)
-x*
-1+
-1,
-1-
-1.
-1/
-10
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-08
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-0"
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-0$
-0%
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-$end
-#10000
-1#
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-#20000
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-0#
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-0#
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-0:
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-0%
-1$
-#240000
-0#
-0"
-0!
-03
-02
-01
-0<
-0=
-0>
-0B
-0;
-04
-0$
-#250000
-1#
-13
-1>
-#260000
-0#
-1"
-03
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-1=
-0>
-#270000
-1#
-13
-1>
-#280000
-0#
-0"
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diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo.sft b/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo.vho b/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo.vho
deleted file mode 100644
index bc26b99..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo.vho
+++ /dev/null
@@ -1,220 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/01/2023 10:28:40"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY Dec2_4En IS
- PORT (
- enable : IN std_logic;
- inputs : IN std_logic_vector(1 DOWNTO 0);
- outputs : OUT std_logic_vector(3 DOWNTO 0)
- );
-END Dec2_4En;
-
-ARCHITECTURE structure OF Dec2_4En IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_enable : std_logic;
-SIGNAL ww_inputs : std_logic_vector(1 DOWNTO 0);
-SIGNAL ww_outputs : std_logic_vector(3 DOWNTO 0);
-SIGNAL \outputs[0]~output_o\ : std_logic;
-SIGNAL \outputs[1]~output_o\ : std_logic;
-SIGNAL \outputs[2]~output_o\ : std_logic;
-SIGNAL \outputs[3]~output_o\ : std_logic;
-SIGNAL \enable~input_o\ : std_logic;
-SIGNAL \inputs[1]~input_o\ : std_logic;
-SIGNAL \inputs[0]~input_o\ : std_logic;
-SIGNAL \outputs~0_combout\ : std_logic;
-SIGNAL \outputs~1_combout\ : std_logic;
-SIGNAL \outputs~2_combout\ : std_logic;
-SIGNAL \outputs~3_combout\ : std_logic;
-
-BEGIN
-
-ww_enable <= enable;
-ww_inputs <= inputs;
-outputs <= ww_outputs;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
-\outputs[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \outputs~0_combout\,
- devoe => ww_devoe,
- o => \outputs[0]~output_o\);
-
-\outputs[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \outputs~1_combout\,
- devoe => ww_devoe,
- o => \outputs[1]~output_o\);
-
-\outputs[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \outputs~2_combout\,
- devoe => ww_devoe,
- o => \outputs[2]~output_o\);
-
-\outputs[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \outputs~3_combout\,
- devoe => ww_devoe,
- o => \outputs[3]~output_o\);
-
-\enable~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_enable,
- o => \enable~input_o\);
-
-\inputs[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_inputs(1),
- o => \inputs[1]~input_o\);
-
-\inputs[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_inputs(0),
- o => \inputs[0]~input_o\);
-
-\outputs~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \outputs~0_combout\ = (\enable~input_o\ & (!\inputs[1]~input_o\ & !\inputs[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000001010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \enable~input_o\,
- datac => \inputs[1]~input_o\,
- datad => \inputs[0]~input_o\,
- combout => \outputs~0_combout\);
-
-\outputs~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \outputs~1_combout\ = (\enable~input_o\ & (\inputs[0]~input_o\ & !\inputs[1]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000010001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \enable~input_o\,
- datab => \inputs[0]~input_o\,
- datad => \inputs[1]~input_o\,
- combout => \outputs~1_combout\);
-
-\outputs~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \outputs~2_combout\ = (\inputs[1]~input_o\ & (\enable~input_o\ & !\inputs[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000010001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inputs[1]~input_o\,
- datab => \enable~input_o\,
- datad => \inputs[0]~input_o\,
- combout => \outputs~2_combout\);
-
-\outputs~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \outputs~3_combout\ = (\inputs[1]~input_o\ & (\enable~input_o\ & \inputs[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000000010000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inputs[1]~input_o\,
- datab => \enable~input_o\,
- datac => \inputs[0]~input_o\,
- combout => \outputs~3_combout\);
-
-ww_outputs(0) <= \outputs[0]~output_o\;
-
-ww_outputs(1) <= \outputs[1]~output_o\;
-
-ww_outputs(2) <= \outputs[2]~output_o\;
-
-ww_outputs(3) <= \outputs[3]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo_20230301102618.sim.vwf b/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo_20230301102618.sim.vwf
deleted file mode 100644
index 5cf9e7c..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo_20230301102618.sim.vwf
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("enable")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("inputs")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 2;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("inputs[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "inputs";
-}
-
-SIGNAL("inputs[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "inputs";
-}
-
-SIGNAL("outputs")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 4;
- LSB_INDEX = 0;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("outputs[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "outputs";
-}
-
-SIGNAL("outputs[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "outputs";
-}
-
-SIGNAL("outputs[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "outputs";
-}
-
-SIGNAL("outputs[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "outputs";
-}
-
-TRANSITION_LIST("enable")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("inputs[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("inputs[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 160.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("outputs[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("outputs[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 1000.0;
- }
- }
-}
-
-TRANSITION_LIST("outputs[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 1000.0;
- }
- }
-}
-
-TRANSITION_LIST("outputs[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "enable";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "inputs";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 0;
- CHILDREN = 2, 3;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "inputs[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 1;
- PARENT = 1;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "inputs[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 1;
- PARENT = 1;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 0;
- CHILDREN = 5, 6, 7, 8;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 5;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 6;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 7;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 8;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo_20230301102750.sim.vwf b/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo_20230301102750.sim.vwf
deleted file mode 100644
index 5d14f5a..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo_20230301102750.sim.vwf
+++ /dev/null
@@ -1,531 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("enable")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("inputs")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 2;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("inputs[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "inputs";
-}
-
-SIGNAL("inputs[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "inputs";
-}
-
-SIGNAL("outputs")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 4;
- LSB_INDEX = 0;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("outputs[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "outputs";
-}
-
-SIGNAL("outputs[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "outputs";
-}
-
-SIGNAL("outputs[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "outputs";
-}
-
-SIGNAL("outputs[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "outputs";
-}
-
-TRANSITION_LIST("enable")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("inputs[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- }
- }
-}
-
-TRANSITION_LIST("inputs[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- }
- }
-}
-
-TRANSITION_LIST("outputs[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("outputs[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 1000.0;
- }
- }
-}
-
-TRANSITION_LIST("outputs[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 1000.0;
- }
- }
-}
-
-TRANSITION_LIST("outputs[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 60.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "enable";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "inputs";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 0;
- CHILDREN = 2, 3;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "inputs[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 1;
- PARENT = 1;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "inputs[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 1;
- PARENT = 1;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 0;
- CHILDREN = 5, 6, 7, 8;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 5;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 6;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 7;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 8;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo_20230301102841.sim.vwf b/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo_20230301102841.sim.vwf
deleted file mode 100644
index a18184f..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo_20230301102841.sim.vwf
+++ /dev/null
@@ -1,579 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("enable")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("inputs")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 2;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("inputs[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "inputs";
-}
-
-SIGNAL("inputs[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "inputs";
-}
-
-SIGNAL("outputs")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 4;
- LSB_INDEX = 0;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("outputs[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "outputs";
-}
-
-SIGNAL("outputs[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "outputs";
-}
-
-SIGNAL("outputs[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "outputs";
-}
-
-SIGNAL("outputs[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "outputs";
-}
-
-TRANSITION_LIST("enable")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("inputs[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
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- LEVEL 0 FOR 20.0;
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- LEVEL 0 FOR 20.0;
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- LEVEL 0 FOR 20.0;
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- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
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- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- }
- }
-}
-
-TRANSITION_LIST("inputs[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
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- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
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- LEVEL 0 FOR 10.0;
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- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
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- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
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- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
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- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- }
- }
-}
-
-TRANSITION_LIST("outputs[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("outputs[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 60.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 50.0;
- }
- }
-}
-
-TRANSITION_LIST("outputs[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 60.0;
- }
- }
-}
-
-TRANSITION_LIST("outputs[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 70.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "enable";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "inputs";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 0;
- CHILDREN = 2, 3;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "inputs[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 1;
- PARENT = 1;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "inputs[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 1;
- PARENT = 1;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 0;
- CHILDREN = 5, 6, 7, 8;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 5;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 6;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 7;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "outputs[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 8;
- TREE_LEVEL = 1;
- PARENT = 4;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo_modelsim.xrf
deleted file mode 100644
index 5eba859..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4EnDemo_modelsim.xrf
+++ /dev/null
@@ -1,20 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En_1.vwf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/db/Dec2_4EnDemo.cbx.xml
-design_name = Dec2_4En
-instance = comp, \outputs[0]~output\, outputs[0]~output, Dec2_4En, 1
-instance = comp, \outputs[1]~output\, outputs[1]~output, Dec2_4En, 1
-instance = comp, \outputs[2]~output\, outputs[2]~output, Dec2_4En, 1
-instance = comp, \outputs[3]~output\, outputs[3]~output, Dec2_4En, 1
-instance = comp, \enable~input\, enable~input, Dec2_4En, 1
-instance = comp, \inputs[1]~input\, inputs[1]~input, Dec2_4En, 1
-instance = comp, \inputs[0]~input\, inputs[0]~input, Dec2_4En, 1
-instance = comp, \outputs~0\, outputs~0, Dec2_4En, 1
-instance = comp, \outputs~1\, outputs~1, Dec2_4En, 1
-instance = comp, \outputs~2\, outputs~2, Dec2_4En, 1
-instance = comp, \outputs~3\, outputs~3, Dec2_4En, 1
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4En_1.vwf.vht b/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4En_1.vwf.vht
deleted file mode 100644
index 938ac20..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/Dec2_4En_1.vwf.vht
+++ /dev/null
@@ -1,91 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- *****************************************************************************
--- This file contains a Vhdl test bench with test vectors .The test vectors
--- are exported from a vector file in the Quartus Waveform Editor and apply to
--- the top level entity of the current Quartus project .The user can use this
--- testbench to simulate his design using a third-party simulation tool .
--- *****************************************************************************
--- Generated on "03/01/2023 10:28:40"
-
--- Vhdl Test Bench(with test vectors) for design : Dec2_4En
---
--- Simulation tool : 3rd Party
---
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY Dec2_4En_vhd_vec_tst IS
-END Dec2_4En_vhd_vec_tst;
-ARCHITECTURE Dec2_4En_arch OF Dec2_4En_vhd_vec_tst IS
--- constants
--- signals
-SIGNAL enable : STD_LOGIC;
-SIGNAL inputs : STD_LOGIC_VECTOR(1 DOWNTO 0);
-SIGNAL outputs : STD_LOGIC_VECTOR(3 DOWNTO 0);
-COMPONENT Dec2_4En
- PORT (
- enable : IN STD_LOGIC;
- inputs : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- outputs : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
- );
-END COMPONENT;
-BEGIN
- i1 : Dec2_4En
- PORT MAP (
--- list connections between master ports and signals
- enable => enable,
- inputs => inputs,
- outputs => outputs
- );
-
--- enable
-t_prcs_enable: PROCESS
-BEGIN
- FOR i IN 1 TO 12
- LOOP
- enable <= '0';
- WAIT FOR 40000 ps;
- enable <= '1';
- WAIT FOR 40000 ps;
- END LOOP;
- enable <= '0';
-WAIT;
-END PROCESS t_prcs_enable;
--- inputs[1]
-t_prcs_inputs_1: PROCESS
-BEGIN
-LOOP
- inputs(1) <= '0';
- WAIT FOR 20000 ps;
- inputs(1) <= '1';
- WAIT FOR 20000 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_inputs_1;
--- inputs[0]
-t_prcs_inputs_0: PROCESS
-BEGIN
-LOOP
- inputs(0) <= '0';
- WAIT FOR 10000 ps;
- inputs(0) <= '1';
- WAIT FOR 10000 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_inputs_0;
-END Dec2_4En_arch;
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/transcript
deleted file mode 100644
index 0b57b75..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/transcript
+++ /dev/null
@@ -1,44 +0,0 @@
-# do Dec2_4EnDemo.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 10:28:41 on Mar 01,2023
-# vcom -work work Dec2_4EnDemo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity Dec2_4En
-# -- Compiling architecture structure of Dec2_4En
-# End time: 10:28:41 on Mar 01,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 10:28:41 on Mar 01,2023
-# vcom -work work Dec2_4En_1.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity Dec2_4En_vhd_vec_tst
-# -- Compiling architecture Dec2_4En_arch of Dec2_4En_vhd_vec_tst
-# End time: 10:28:41 on Mar 01,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4En_vhd_vec_tst
-# Start time: 10:28:41 on Mar 01,2023
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading work.dec2_4en_vhd_vec_tst(dec2_4en_arch)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading cycloneive.cycloneive_atom_pack(body)
-# Loading cycloneive.cycloneive_components
-# Loading work.dec2_4en(structure)
-# Loading ieee.std_logic_arith(body)
-# Loading cycloneive.cycloneive_io_obuf(arch)
-# Loading cycloneive.cycloneive_io_ibuf(arch)
-# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#31
-# End time: 10:28:41 on Mar 01,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/vwf_sim_transcript
deleted file mode 100644
index 20f337c..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/vwf_sim_transcript
+++ /dev/null
@@ -1,75 +0,0 @@
-Determining the location of the ModelSim executable...
-
-Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
-
-To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
-Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
-
-**** Generating the ModelSim Testbench ****
-
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En_1.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/Dec2_4En_1.vwf.vht"
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Mar 1 10:28:39 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/Dec2_4En_1.vwf.vhtInfo (119006): Selected device EP4CE115F29C7 for design "Dec2_4EnDemo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Completed successfully.
-
-**** Generating the functional simulation netlist ****
-
-quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/" Dec2_4EnDemo -c Dec2_4EnDemo
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Mar 1 10:28:40 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/ Dec2_4EnDemo -c Dec2_4EnDemoInfo (119006): Selected device EP4CE115F29C7 for design "Dec2_4EnDemo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file Dec2_4EnDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 615 megabytes Info: Processing ended: Wed Mar 1 10:28:40 2023 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00
-Completed successfully.
-
-**** Generating the ModelSim .do script ****
-
-/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/Dec2_4EnDemo.do generated.
-
-Completed successfully.
-
-**** Running the ModelSim simulation ****
-
-/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do Dec2_4EnDemo.do
-
-Reading pref.tcl
-# 2020.1
-# do Dec2_4EnDemo.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020# Start time: 10:28:41 on Mar 01,2023# vcom -work work Dec2_4EnDemo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity Dec2_4En
-# -- Compiling architecture structure of Dec2_4En
-# End time: 10:28:41 on Mar 01,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020# Start time: 10:28:41 on Mar 01,2023# vcom -work work Dec2_4En_1.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity Dec2_4En_vhd_vec_tst
-# -- Compiling architecture Dec2_4En_arch of Dec2_4En_vhd_vec_tst
-# End time: 10:28:41 on Mar 01,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4En_vhd_vec_tst # Start time: 10:28:41 on Mar 01,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.dec2_4en_vhd_vec_tst(dec2_4en_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.dec2_4en(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#31
-# End time: 10:28:41 on Mar 01,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-Completed successfully.
-
-**** Converting ModelSim VCD to vector waveform ****
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En_1.vwf...
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/Dec2_4EnDemo.msim.vcd...
-
-Processing channel transitions...
-
-Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/Dec2_4EnDemo_20230301102841.sim.vwf
-
-Finished VCD to VWF conversion.
-
-Completed successfully.
-
-All completed.
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/work/_info
deleted file mode 100644
index 1cc7001..0000000
--- a/1ano/2semestre/lsd/pratica02/part1/simulation/qsim/work/_info
+++ /dev/null
@@ -1,101 +0,0 @@
-m255
-K4
-z2
-!s11e vcom 2020.1 2020.02, Feb 28 2020
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-Z0 d/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim
-Edec2_4en
-Z1 w1677666520
-Z2 DPx4 ieee 16 vital_primitives 0 22 G>kiXP8Q9dRClKfK1Zn7j1
-Z3 DPx10 cycloneive 20 cycloneive_atom_pack 0 22 WOh:M[al;oVzG5c`D0
-Z4 DPx4 ieee 12 vital_timing 0 22 J>EBealN09f8GzldA[z2>3
-Z5 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
-Z6 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
-Z7 DPx10 cycloneive 21 cycloneive_components 0 22 zGMDhP>8e@2k@f0e]PHE^LYlhac8AckR3
-!s100 9V=00o4DVJBA>dMeWQQPZ0
-R10
-32
-R11
-!i10b 1
-R12
-R13
-R14
-!i113 1
-R15
-R16
-Edec2_4en_vhd_vec_tst
-R1
-R5
-R6
-!i122 5
-R0
-Z17 8Dec2_4En_1.vwf.vht
-Z18 FDec2_4En_1.vwf.vht
-l0
-L32 1
-V=Fcz1LPO@dQF_NOg:L9622
-!s100 GGLn?lDEfWOgHJjmo`
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp.bpm b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp.bpm
deleted file mode 100644
index b2f7721..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp.cdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp.cdb
deleted file mode 100644
index 7acfe6c..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp.hdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp.hdb
deleted file mode 100644
index a8cefe2..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp.idb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp.idb
deleted file mode 100644
index b9a8b56..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp.logdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp.logdb
deleted file mode 100644
index 1233b1a..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp.logdb
+++ /dev/null
@@ -1,61 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;0;0;0;0;19;0;0;0;0;0;0;0;8;0;0;0;11;8;0;11;0;0;8;0;19;19;19;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,19;19;19;19;19;0;19;19;19;19;19;19;19;11;19;19;19;8;11;19;8;19;19;11;19;0;0;0;19;19,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,r[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,r[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,r[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,r[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,m[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,m[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,m[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,m[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,b[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,a[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,op[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,op[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,a[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,b[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,b[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,b[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,a[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,a[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,op[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp.rdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp.rdb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp_merge.kpt b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.cmp_merge.kpt
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.db_info b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.db_info
deleted file mode 100644
index 4cbc8cd..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Thu Mar 16 16:27:41 2023
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.eda.qmsg b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.eda.qmsg
deleted file mode 100644
index 4869c50..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678984411293 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678984411293 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 16 16:33:31 2023 " "Processing started: Thu Mar 16 16:33:31 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678984411293 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678984411293 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off ALUDemo -c ALUDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off ALUDemo -c ALUDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678984411293 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678984411445 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "ALUDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/simulation/modelsim/ simulation " "Generated file ALUDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678984411484 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678984411496 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 16 16:33:31 2023 " "Processing ended: Thu Mar 16 16:33:31 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678984411496 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678984411496 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678984411496 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678984411496 ""}
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.fit.qmsg b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.fit.qmsg
deleted file mode 100644
index a5c3fa8..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.fit.qmsg
+++ /dev/null
@@ -1,51 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678984399297 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678984399298 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ALUDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"ALUDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678984399300 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678984399344 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678984399344 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678984399642 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678984399660 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678984399883 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678984399883 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678984399883 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678984399883 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678984399883 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678984399883 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678984399883 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678984399883 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678984399883 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678984399883 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/" { { 0 { 0 ""} 0 808 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678984399888 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/" { { 0 { 0 ""} 0 810 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678984399888 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/" { { 0 { 0 ""} 0 812 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678984399888 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/" { { 0 { 0 ""} 0 814 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678984399888 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/" { { 0 { 0 ""} 0 816 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678984399888 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678984399888 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678984399899 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "19 19 " "No exact pin location assignment(s) for 19 pins of 19 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1678984400364 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ALUDemo.sdc " "Synopsys Design Constraints File file not found: 'ALUDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678984400604 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678984400605 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678984400605 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678984400605 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678984400607 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678984400607 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678984400607 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678984400615 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678984400615 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678984400615 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678984400615 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678984400616 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678984400616 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678984400616 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678984400616 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678984400616 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678984400616 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678984400616 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "19 unused 2.5V 11 8 0 " "Number of I/O pins in group: 19 (unused VREF, 2.5V VCCIO, 11 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1678984400627 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1678984400627 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1678984400627 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 52 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 52 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1678984400628 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 63 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 63 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1678984400628 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 73 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 73 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1678984400628 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 71 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 71 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1678984400628 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 65 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 65 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1678984400628 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 57 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 57 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1678984400628 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 72 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 72 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1678984400628 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 71 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 71 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1678984400628 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1678984400628 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1678984400628 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678984400652 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678984400652 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678984400660 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678984400665 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678984402052 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678984402143 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678984402169 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678984402584 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678984402584 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678984402818 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X58_Y61 X68_Y73 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X58_Y61 to location X68_Y73" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X58_Y61 to location X68_Y73"} { { 12 { 0 ""} 58 61 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678984404837 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678984404837 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678984404960 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678984404960 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678984404960 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678984404962 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678984405044 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678984405051 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678984405244 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678984405244 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678984405388 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678984405623 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678984405819 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678984405864 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 527 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 527 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1154 " "Peak virtual memory: 1154 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678984406021 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 16 16:33:26 2023 " "Processing ended: Thu Mar 16 16:33:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678984406021 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678984406021 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678984406021 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678984406021 ""}
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.hier_info b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.hier_info
deleted file mode 100644
index 8f0420b..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.hier_info
+++ /dev/null
@@ -1,90 +0,0 @@
-|ALU4
-a[0] => Mult0.IN3
-a[0] => Add0.IN4
-a[0] => Add1.IN8
-a[0] => Div0.IN3
-a[0] => Mod0.IN3
-a[0] => RESULT.IN0
-a[0] => RESULT.IN0
-a[0] => RESULT.IN0
-a[1] => Mult0.IN2
-a[1] => Add0.IN3
-a[1] => Add1.IN7
-a[1] => Div0.IN2
-a[1] => Mod0.IN2
-a[1] => RESULT.IN0
-a[1] => RESULT.IN0
-a[1] => RESULT.IN0
-a[2] => Mult0.IN1
-a[2] => Add0.IN2
-a[2] => Add1.IN6
-a[2] => Div0.IN1
-a[2] => Mod0.IN1
-a[2] => RESULT.IN0
-a[2] => RESULT.IN0
-a[2] => RESULT.IN0
-a[3] => Mult0.IN0
-a[3] => Add0.IN1
-a[3] => Add1.IN5
-a[3] => Div0.IN0
-a[3] => Mod0.IN0
-a[3] => RESULT.IN0
-a[3] => RESULT.IN0
-a[3] => RESULT.IN0
-b[0] => Mult0.IN7
-b[0] => Add0.IN8
-b[0] => Div0.IN7
-b[0] => Mod0.IN7
-b[0] => RESULT.IN1
-b[0] => RESULT.IN1
-b[0] => RESULT.IN1
-b[0] => Add1.IN4
-b[1] => Mult0.IN6
-b[1] => Add0.IN7
-b[1] => Div0.IN6
-b[1] => Mod0.IN6
-b[1] => RESULT.IN1
-b[1] => RESULT.IN1
-b[1] => RESULT.IN1
-b[1] => Add1.IN3
-b[2] => Mult0.IN5
-b[2] => Add0.IN6
-b[2] => Div0.IN5
-b[2] => Mod0.IN5
-b[2] => RESULT.IN1
-b[2] => RESULT.IN1
-b[2] => RESULT.IN1
-b[2] => Add1.IN2
-b[3] => Mult0.IN4
-b[3] => Add0.IN5
-b[3] => Div0.IN4
-b[3] => Mod0.IN4
-b[3] => RESULT.IN1
-b[3] => RESULT.IN1
-b[3] => RESULT.IN1
-b[3] => Add1.IN1
-op[0] => Mux0.IN9
-op[0] => Mux1.IN9
-op[0] => Mux2.IN9
-op[0] => Mux3.IN9
-op[0] => Equal0.IN1
-op[1] => Mux0.IN8
-op[1] => Mux1.IN8
-op[1] => Mux2.IN8
-op[1] => Mux3.IN8
-op[1] => Equal0.IN2
-op[2] => Mux0.IN7
-op[2] => Mux1.IN7
-op[2] => Mux2.IN7
-op[2] => Mux3.IN7
-op[2] => Equal0.IN0
-r[0] << Mux3.DB_MAX_OUTPUT_PORT_TYPE
-r[1] << Mux2.DB_MAX_OUTPUT_PORT_TYPE
-r[2] << Mux1.DB_MAX_OUTPUT_PORT_TYPE
-r[3] << Mux0.DB_MAX_OUTPUT_PORT_TYPE
-m[0] << m.DB_MAX_OUTPUT_PORT_TYPE
-m[1] << m.DB_MAX_OUTPUT_PORT_TYPE
-m[2] << m.DB_MAX_OUTPUT_PORT_TYPE
-m[3] << m.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.hif b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.hif
deleted file mode 100644
index 958b9f5..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.hif and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.lpc.html b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.lpc.html
deleted file mode 100644
index fbc5ab5..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.lpc.html
+++ /dev/null
@@ -1,18 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.lpc.rdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.lpc.rdb
deleted file mode 100644
index b1e0351..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.lpc.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.lpc.txt b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.lpc.txt
deleted file mode 100644
index a463804..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.lpc.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map.ammdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map.ammdb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map.bpm b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map.bpm
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map.cdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map.cdb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map.hdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map.hdb
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-v1
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map.qmsg b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map.qmsg
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-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678984391496 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678984391496 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 16 16:33:11 2023 " "Processing started: Thu Mar 16 16:33:11 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678984391496 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984391496 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ALUDemo -c ALUDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off ALUDemo -c ALUDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984391497 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678984391632 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678984391632 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALU4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ALU4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALU4-Behavioral " "Found design unit 1: ALU4-Behavioral" { } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397129 ""} { "Info" "ISGN_ENTITY_NAME" "1 ALU4 " "Found entity 1: ALU4" { } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397129 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397129 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALUDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ALUDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ALUDemo " "Found entity 1: ALUDemo" { } { { "ALUDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALUDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397130 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397130 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ALU4 " "Elaborating entity \"ALU4\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678984397199 ""}
-{ "Info" "ILPMS_INFERENCING_SUMMARY" "3 " "Inferred 3 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Mod0\"" { } { { "ALU4.vhd" "Mod0" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 28 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1678984397492 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult0\"" { } { { "ALU4.vhd" "Mult0" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 21 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1678984397492 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Div0\"" { } { { "ALU4.vhd" "Div0" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 27 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1678984397492 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1678984397492 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Mod0 " "Elaborated megafunction instantiation \"lpm_divide:Mod0\"" { } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 28 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678984397531 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_divide:Mod0 " "Instantiated megafunction \"lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 4 " "Parameter \"LPM_WIDTHN\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397531 ""} } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 28 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1678984397531 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_i9m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_i9m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_i9m " "Found entity 1: lpm_divide_i9m" { } { { "db/lpm_divide_i9m.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_i9m.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397551 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397551 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_7kh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_7kh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_7kh " "Found entity 1: sign_div_unsign_7kh" { } { { "db/sign_div_unsign_7kh.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/sign_div_unsign_7kh.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397553 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397553 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_24f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_24f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_24f " "Found entity 1: alt_u_div_24f" { } { { "db/alt_u_div_24f.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/alt_u_div_24f.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397555 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397555 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_7pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_7pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_7pc " "Found entity 1: add_sub_7pc" { } { { "db/add_sub_7pc.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_7pc.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397575 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397575 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_8pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_8pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_8pc " "Found entity 1: add_sub_8pc" { } { { "db/add_sub_8pc.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_8pc.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397596 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397596 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\"" { } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 21 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678984397622 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult0 " "Instantiated megafunction \"lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 4 " "Parameter \"LPM_WIDTHB\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 8 " "Parameter \"LPM_WIDTHP\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 8 " "Parameter \"LPM_WIDTHR\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 21 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1678984397622 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_j8t.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_j8t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_j8t " "Found entity 1: mult_j8t" { } { { "db/mult_j8t.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf" 29 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397642 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397642 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Div0 " "Elaborated megafunction instantiation \"lpm_divide:Div0\"" { } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 27 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678984397645 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_divide:Div0 " "Instantiated megafunction \"lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 4 " "Parameter \"LPM_WIDTHN\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397645 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397645 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397645 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397645 ""} } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 27 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1678984397645 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_fhm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_fhm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_fhm " "Found entity 1: lpm_divide_fhm" { } { { "db/lpm_divide_fhm.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_fhm.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397663 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397663 ""}
-{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "LCELL buffer " "Synthesized away the following LCELL buffer node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "lpm_mult:Mult0\|mult_j8t:auto_generated\|le5a\[4\] " "Synthesized away node \"lpm_mult:Mult0\|mult_j8t:auto_generated\|le5a\[4\]\"" { } { { "db/mult_j8t.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf" 43 6 0 } } { "lpm_mult.tdf" "" { Text "/home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_mult.tdf" 377 4 0 } } { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 21 -1 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1678984397689 "|ALU4|lpm_mult:Mult0|mult_j8t:auto_generated|le5a[4]"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1678984397689 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1678984397689 ""}
-{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "48 " "Ignored 48 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_CARRY_SUM" "4 " "Ignored 4 CARRY_SUM buffer(s)" { } { } 0 13016 "Ignored %1!d! CARRY_SUM buffer(s)" 0 0 "Design Software" 0 -1 1678984397817 ""} { "Info" "IMLS_MLS_IGNORED_SOFT" "44 " "Ignored 44 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Design Software" 0 -1 1678984397817 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Analysis & Synthesis" 0 -1 1678984397817 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678984397906 ""}
-{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "lpm_mult:Mult0\|mult_j8t:auto_generated\|le3a\[5\] " "Logic cell \"lpm_mult:Mult0\|mult_j8t:auto_generated\|le3a\[5\]\"" { } { { "db/mult_j8t.tdf" "le3a\[5\]" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf" 41 6 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1678984398272 ""} } { } 0 17016 "Found the following redundant logic cells in design" 0 0 "Analysis & Synthesis" 0 -1 1678984398272 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678984398362 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678984398362 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "117 " "Implemented 117 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678984398564 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678984398564 ""} { "Info" "ICUT_CUT_TM_LCELLS" "98 " "Implemented 98 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678984398564 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678984398564 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678984398569 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 16 16:33:18 2023 " "Processing ended: Thu Mar 16 16:33:18 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678984398569 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678984398569 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678984398569 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984398569 ""}
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map.rdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map.rdb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map_bb.hdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map_bb.hdb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map_bb.logdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.pre_map.hdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.root_partition.map.reg_db.cdb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.routing.rdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.rtlv.hdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.rtlv_sg.cdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.rtlv_sg.cdb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.rtlv_sg_swap.cdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.rtlv_sg_swap.cdb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.sld_design_entry.sci b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.smart_action.txt b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.smart_action.txt
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--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.sta.qmsg b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.sta.qmsg
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--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678984409278 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678984409278 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 16 16:33:29 2023 " "Processing started: Thu Mar 16 16:33:29 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678984409278 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678984409278 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ALUDemo -c ALUDemo " "Command: quartus_sta ALUDemo -c ALUDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678984409278 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678984409300 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678984409358 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678984409358 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678984409403 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678984409403 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ALUDemo.sdc " "Synopsys Design Constraints File file not found: 'ALUDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678984409699 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678984409699 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678984409699 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678984409700 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678984409700 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678984409700 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678984409700 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678984409703 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678984409704 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984409705 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984409707 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984409707 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984409707 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984409708 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984409708 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678984409709 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678984409723 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678984409977 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678984409991 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678984409991 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678984409992 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678984409992 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984409992 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984409993 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984409993 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984409994 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984409994 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984409994 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678984409995 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678984410032 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678984410032 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678984410032 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678984410032 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984410033 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984410033 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984410034 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984410034 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678984410034 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678984410247 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678984410248 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "536 " "Peak virtual memory: 536 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678984410258 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 16 16:33:30 2023 " "Processing ended: Thu Mar 16 16:33:30 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678984410258 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678984410258 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678984410258 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678984410258 ""}
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.sta.rdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.sta.rdb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.sta_cmp.7_slow_1200mv_85c.tdb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.tis_db_list.ddb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.tiscmp.fast_1200mv_0c.ddb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.tiscmp.slow_1200mv_0c.ddb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.tiscmp.slow_1200mv_85c.ddb
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diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.vpr.ammdb b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.vpr.ammdb
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index 4f15663..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo_partition_pins.json b/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo_partition_pins.json
deleted file mode 100644
index d9b037f..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/ALUDemo_partition_pins.json
+++ /dev/null
@@ -1,85 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "r[0]",
- "strict" : false
- },
- {
- "name" : "r[1]",
- "strict" : false
- },
- {
- "name" : "r[2]",
- "strict" : false
- },
- {
- "name" : "r[3]",
- "strict" : false
- },
- {
- "name" : "m[0]",
- "strict" : false
- },
- {
- "name" : "m[1]",
- "strict" : false
- },
- {
- "name" : "m[2]",
- "strict" : false
- },
- {
- "name" : "m[3]",
- "strict" : false
- },
- {
- "name" : "b[0]",
- "strict" : false
- },
- {
- "name" : "a[0]",
- "strict" : false
- },
- {
- "name" : "op[1]",
- "strict" : false
- },
- {
- "name" : "op[0]",
- "strict" : false
- },
- {
- "name" : "a[3]",
- "strict" : false
- },
- {
- "name" : "b[3]",
- "strict" : false
- },
- {
- "name" : "b[2]",
- "strict" : false
- },
- {
- "name" : "b[1]",
- "strict" : false
- },
- {
- "name" : "a[2]",
- "strict" : false
- },
- {
- "name" : "a[1]",
- "strict" : false
- },
- {
- "name" : "op[2]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_7pc.tdf b/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_7pc.tdf
deleted file mode 100644
index c23d628..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_7pc.tdf
+++ /dev/null
@@ -1,44 +0,0 @@
---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="SUB" LPM_WIDTH=1 cout dataa datab result
---VERSION_BEGIN 20.1 cbx_cycloneii 2020:11:11:17:03:37:SJ cbx_lpm_add_sub 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ cbx_nadder 2020:11:11:17:03:37:SJ cbx_stratix 2020:11:11:17:03:37:SJ cbx_stratixii 2020:11:11:17:03:37:SJ VERSION_END
-
-
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
-
-
---synthesis_resources =
-SUBDESIGN add_sub_7pc
-(
- cout : output;
- dataa[0..0] : input;
- datab[0..0] : input;
- result[0..0] : output;
-)
-VARIABLE
- carry_eqn[0..0] : WIRE;
- cin_wire : WIRE;
- datab_node[0..0] : WIRE;
- sum_eqn[0..0] : WIRE;
-
-BEGIN
- carry_eqn[] = ( ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
- cin_wire = B"1";
- cout = carry_eqn[0..0];
- datab_node[] = (! datab[]);
- result[] = sum_eqn[];
- sum_eqn[] = ( ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
-END;
---VALID FILE
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_8pc.tdf b/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_8pc.tdf
deleted file mode 100644
index d5b8dea..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_8pc.tdf
+++ /dev/null
@@ -1,44 +0,0 @@
---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="SUB" LPM_WIDTH=2 cout dataa datab result
---VERSION_BEGIN 20.1 cbx_cycloneii 2020:11:11:17:03:37:SJ cbx_lpm_add_sub 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ cbx_nadder 2020:11:11:17:03:37:SJ cbx_stratix 2020:11:11:17:03:37:SJ cbx_stratixii 2020:11:11:17:03:37:SJ VERSION_END
-
-
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
-
-
---synthesis_resources =
-SUBDESIGN add_sub_8pc
-(
- cout : output;
- dataa[1..0] : input;
- datab[1..0] : input;
- result[1..0] : output;
-)
-VARIABLE
- carry_eqn[1..0] : WIRE;
- cin_wire : WIRE;
- datab_node[1..0] : WIRE;
- sum_eqn[1..0] : WIRE;
-
-BEGIN
- carry_eqn[] = ( ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & carry_eqn[0..0])), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
- cin_wire = B"1";
- cout = carry_eqn[1..1];
- datab_node[] = (! datab[]);
- result[] = sum_eqn[];
- sum_eqn[] = ( ((dataa[1..1] $ datab_node[1..1]) $ carry_eqn[0..0]), ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
-END;
---VALID FILE
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/alt_u_div_24f.tdf b/1ano/2semestre/lsd/pratica03/ALUDemo/db/alt_u_div_24f.tdf
deleted file mode 100644
index d90fcdc..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/alt_u_div_24f.tdf
+++ /dev/null
@@ -1,92 +0,0 @@
---alt_u_div DEVICE_FAMILY="Cyclone IV E" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=4 WIDTH_N=4 WIDTH_Q=4 WIDTH_R=4 denominator numerator quotient remainder
---VERSION_BEGIN 20.1 cbx_cycloneii 2020:11:11:17:03:37:SJ cbx_lpm_abs 2020:11:11:17:03:37:SJ cbx_lpm_add_sub 2020:11:11:17:03:37:SJ cbx_lpm_divide 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ cbx_nadder 2020:11:11:17:03:37:SJ cbx_stratix 2020:11:11:17:03:37:SJ cbx_stratixii 2020:11:11:17:03:37:SJ cbx_util_mgl 2020:11:11:17:03:37:SJ VERSION_END
-
-
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
-
-FUNCTION add_sub_7pc (dataa[0..0], datab[0..0])
-RETURNS ( cout, result[0..0]);
-FUNCTION add_sub_8pc (dataa[1..0], datab[1..0])
-RETURNS ( cout, result[1..0]);
-
---synthesis_resources = lut 9
-SUBDESIGN alt_u_div_24f
-(
- denominator[3..0] : input;
- numerator[3..0] : input;
- quotient[3..0] : output;
- remainder[3..0] : output;
-)
-VARIABLE
- add_sub_0 : add_sub_7pc;
- add_sub_1 : add_sub_8pc;
- add_sub_2_result_int[3..0] : WIRE;
- add_sub_2_cout : WIRE;
- add_sub_2_dataa[2..0] : WIRE;
- add_sub_2_datab[2..0] : WIRE;
- add_sub_2_result[2..0] : WIRE;
- add_sub_3_result_int[4..0] : WIRE;
- add_sub_3_cout : WIRE;
- add_sub_3_dataa[3..0] : WIRE;
- add_sub_3_datab[3..0] : WIRE;
- add_sub_3_result[3..0] : WIRE;
- DenominatorIn[24..0] : WIRE;
- DenominatorIn_tmp[24..0] : WIRE;
- gnd_wire : WIRE;
- nose[19..0] : WIRE;
- NumeratorIn[19..0] : WIRE;
- NumeratorIn_tmp[19..0] : WIRE;
- prestg[15..0] : WIRE;
- quotient_tmp[3..0] : WIRE;
- sel[19..0] : WIRE;
- selnose[19..0] : WIRE;
- StageIn[19..0] : WIRE;
- StageIn_tmp[19..0] : WIRE;
- StageOut[15..0] : WIRE;
-
-BEGIN
- add_sub_0.dataa[0..0] = NumeratorIn[3..3];
- add_sub_0.datab[0..0] = DenominatorIn[0..0];
- add_sub_1.dataa[] = ( StageIn[4..4], NumeratorIn[6..6]);
- add_sub_1.datab[1..0] = DenominatorIn[6..5];
- add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
- add_sub_2_result[] = add_sub_2_result_int[2..0];
- add_sub_2_cout = !add_sub_2_result_int[3];
- add_sub_2_dataa[] = ( StageIn[9..8], NumeratorIn[9..9]);
- add_sub_2_datab[] = DenominatorIn[12..10];
- add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
- add_sub_3_result[] = add_sub_3_result_int[3..0];
- add_sub_3_cout = !add_sub_3_result_int[4];
- add_sub_3_dataa[] = ( StageIn[14..12], NumeratorIn[12..12]);
- add_sub_3_datab[] = DenominatorIn[18..15];
- DenominatorIn[] = DenominatorIn_tmp[];
- DenominatorIn_tmp[] = ( DenominatorIn[19..0], ( gnd_wire, denominator[]));
- gnd_wire = B"0";
- nose[] = ( B"0000", add_sub_3_cout, B"0000", add_sub_2_cout, B"0000", add_sub_1.cout, B"0000", add_sub_0.cout);
- NumeratorIn[] = NumeratorIn_tmp[];
- NumeratorIn_tmp[] = ( NumeratorIn[15..0], numerator[]);
- prestg[] = ( add_sub_3_result[], GND, add_sub_2_result[], B"00", add_sub_1.result[], B"000", add_sub_0.result[]);
- quotient[] = quotient_tmp[];
- quotient_tmp[] = ( (! selnose[0..0]), (! selnose[5..5]), (! selnose[10..10]), (! selnose[15..15]));
- remainder[3..0] = StageIn[19..16];
- sel[] = ( gnd_wire, (sel[19..19] # DenominatorIn[23..23]), (sel[18..18] # DenominatorIn[22..22]), (sel[17..17] # DenominatorIn[21..21]), gnd_wire, (sel[15..15] # DenominatorIn[18..18]), (sel[14..14] # DenominatorIn[17..17]), (sel[13..13] # DenominatorIn[16..16]), gnd_wire, (sel[11..11] # DenominatorIn[13..13]), (sel[10..10] # DenominatorIn[12..12]), (sel[9..9] # DenominatorIn[11..11]), gnd_wire, (sel[7..7] # DenominatorIn[8..8]), (sel[6..6] # DenominatorIn[7..7]), (sel[5..5] # DenominatorIn[6..6]), gnd_wire, (sel[3..3] # DenominatorIn[3..3]), (sel[2..2] # DenominatorIn[2..2]), (sel[1..1] # DenominatorIn[1..1]));
- selnose[] = ( ((! nose[19..19]) # sel[19..19]), ((! nose[18..18]) # sel[18..18]), ((! nose[17..17]) # sel[17..17]), ((! nose[16..16]) # sel[16..16]), ((! nose[15..15]) # sel[15..15]), ((! nose[14..14]) # sel[14..14]), ((! nose[13..13]) # sel[13..13]), ((! nose[12..12]) # sel[12..12]), ((! nose[11..11]) # sel[11..11]), ((! nose[10..10]) # sel[10..10]), ((! nose[9..9]) # sel[9..9]), ((! nose[8..8]) # sel[8..8]), ((! nose[7..7]) # sel[7..7]), ((! nose[6..6]) # sel[6..6]), ((! nose[5..5]) # sel[5..5]), ((! nose[4..4]) # sel[4..4]), ((! nose[3..3]) # sel[3..3]), ((! nose[2..2]) # sel[2..2]), ((! nose[1..1]) # sel[1..1]), ((! nose[0..0]) # sel[0..0]));
- StageIn[] = StageIn_tmp[];
- StageIn_tmp[] = ( StageOut[15..0], B"0000");
- StageOut[] = ( ((( StageIn[14..12], NumeratorIn[12..12]) & selnose[15..15]) # (prestg[15..12] & (! selnose[15..15]))), ((( StageIn[10..8], NumeratorIn[9..9]) & selnose[10..10]) # (prestg[11..8] & (! selnose[10..10]))), ((( StageIn[6..4], NumeratorIn[6..6]) & selnose[5..5]) # (prestg[7..4] & (! selnose[5..5]))), ((( StageIn[2..0], NumeratorIn[3..3]) & selnose[0..0]) # (prestg[3..0] & (! selnose[0..0]))));
-END;
---VALID FILE
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_fhm.tdf b/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_fhm.tdf
deleted file mode 100644
index 2de8c8d..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_fhm.tdf
+++ /dev/null
@@ -1,43 +0,0 @@
---lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=4 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
---VERSION_BEGIN 20.1 cbx_cycloneii 2020:11:11:17:03:37:SJ cbx_lpm_abs 2020:11:11:17:03:37:SJ cbx_lpm_add_sub 2020:11:11:17:03:37:SJ cbx_lpm_divide 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ cbx_nadder 2020:11:11:17:03:37:SJ cbx_stratix 2020:11:11:17:03:37:SJ cbx_stratixii 2020:11:11:17:03:37:SJ cbx_util_mgl 2020:11:11:17:03:37:SJ VERSION_END
-
-
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
-
-FUNCTION sign_div_unsign_7kh (denominator[3..0], numerator[3..0])
-RETURNS ( quotient[3..0], remainder[3..0]);
-
---synthesis_resources =
-SUBDESIGN lpm_divide_fhm
-(
- denom[3..0] : input;
- numer[3..0] : input;
- quotient[3..0] : output;
- remain[3..0] : output;
-)
-VARIABLE
- divider : sign_div_unsign_7kh;
- numer_tmp[3..0] : WIRE;
-
-BEGIN
- divider.denominator[] = denom[];
- divider.numerator[] = numer_tmp[];
- numer_tmp[] = numer[];
- quotient[] = divider.quotient[];
- remain[] = divider.remainder[];
-END;
---VALID FILE
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_i9m.tdf b/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_i9m.tdf
deleted file mode 100644
index aafe12a..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_i9m.tdf
+++ /dev/null
@@ -1,43 +0,0 @@
---lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=4 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
---VERSION_BEGIN 20.1 cbx_cycloneii 2020:11:11:17:03:37:SJ cbx_lpm_abs 2020:11:11:17:03:37:SJ cbx_lpm_add_sub 2020:11:11:17:03:37:SJ cbx_lpm_divide 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ cbx_nadder 2020:11:11:17:03:37:SJ cbx_stratix 2020:11:11:17:03:37:SJ cbx_stratixii 2020:11:11:17:03:37:SJ cbx_util_mgl 2020:11:11:17:03:37:SJ VERSION_END
-
-
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
-
-FUNCTION sign_div_unsign_7kh (denominator[3..0], numerator[3..0])
-RETURNS ( quotient[3..0], remainder[3..0]);
-
---synthesis_resources = lut 9
-SUBDESIGN lpm_divide_i9m
-(
- denom[3..0] : input;
- numer[3..0] : input;
- quotient[3..0] : output;
- remain[3..0] : output;
-)
-VARIABLE
- divider : sign_div_unsign_7kh;
- numer_tmp[3..0] : WIRE;
-
-BEGIN
- divider.denominator[] = denom[];
- divider.numerator[] = numer_tmp[];
- numer_tmp[] = numer[];
- quotient[] = divider.quotient[];
- remain[] = divider.remainder[];
-END;
---VALID FILE
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf b/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf
deleted file mode 100644
index 636142c..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf
+++ /dev/null
@@ -1,94 +0,0 @@
---lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" INPUT_A_IS_CONSTANT="NO" INPUT_B_IS_CONSTANT="NO" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTHA=4 LPM_WIDTHB=4 LPM_WIDTHP=8 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
---VERSION_BEGIN 20.1 cbx_cycloneii 2020:11:11:17:03:37:SJ cbx_lpm_add_sub 2020:11:11:17:03:37:SJ cbx_lpm_mult 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ cbx_nadder 2020:11:11:17:03:37:SJ cbx_padd 2020:11:11:17:03:37:SJ cbx_stratix 2020:11:11:17:03:37:SJ cbx_stratixii 2020:11:11:17:03:37:SJ cbx_util_mgl 2020:11:11:17:03:37:SJ VERSION_END
-
-
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
-
-FUNCTION carry_sum (cin, sin)
-RETURNS ( cout, sout);
-FUNCTION lcell (in)
-RETURNS ( out);
-FUNCTION soft (in)
-RETURNS ( out);
-
---synthesis_resources = lut 45
-SUBDESIGN mult_j8t
-(
- dataa[3..0] : input;
- datab[3..0] : input;
- result[7..0] : output;
-)
-VARIABLE
- add10_result[7..0] : WIRE;
- add14_result[2..0] : WIRE;
- add6_result[10..0] : WIRE;
- cs1a[2..0] : carry_sum;
- cs2a[2..0] : carry_sum;
- le3a[5..0] : lcell;
- le4a[5..0] : lcell;
- le5a[4..0] : lcell;
- sft11a[7..0] : soft;
- sft12a[7..0] : soft;
- sft13a[7..0] : soft;
- sft15a[2..0] : soft;
- sft16a[2..0] : soft;
- sft17a[2..0] : soft;
- sft7a[10..0] : soft;
- sft8a[10..0] : soft;
- sft9a[10..0] : soft;
- dataa_node[3..0] : WIRE;
- datab_node[3..0] : WIRE;
- final_result_node[7..0] : WIRE;
- w117w[5..0] : WIRE;
- w183w : WIRE;
- w196w : WIRE;
- w257w[10..0] : WIRE;
- w70w[5..0] : WIRE;
- w7w[5..0] : WIRE;
-
-BEGIN
- add10_result[] = sft11a[].out + sft12a[].out;
- add14_result[] = sft15a[].out + sft16a[].out;
- add6_result[] = sft7a[].out + sft8a[].out;
- cs1a[].cin = ( ((w7w[4..4] & cs1a[1].cout) # w7w[5..5]), ((w7w[2..2] & cs1a[0].cout) # w7w[3..3]), w7w[1..1]);
- cs1a[].sin = ( ((((((! w7w[5..5]) & w7w[4..4]) & cs1a[1].cout) # ((w7w[5..5] & w7w[4..4]) & (! cs1a[1].cout))) # ((w7w[5..5] & (! w7w[4..4])) & cs1a[1].cout)) # ((w7w[5..5] & (! w7w[4..4])) & (! cs1a[1].cout))), ((((((! w7w[3..3]) & w7w[2..2]) & cs1a[0].cout) # ((w7w[3..3] & w7w[2..2]) & (! cs1a[0].cout))) # ((w7w[3..3] & (! w7w[2..2])) & cs1a[0].cout)) # ((w7w[3..3] & (! w7w[2..2])) & (! cs1a[0].cout))), w7w[1..1]);
- cs2a[].cin = ( ((w7w[4..4] & cs2a[1].cout) # w7w[5..5]), ((w7w[2..2] & cs2a[0].cout) # w7w[3..3]), w7w[1..1]);
- cs2a[].sin = ( ((((((! w7w[5..5]) & (! w7w[4..4])) & cs2a[1].cout) # (((! w7w[5..5]) & w7w[4..4]) & (! cs2a[1].cout))) # ((w7w[5..5] & w7w[4..4]) & (! cs2a[1].cout))) # ((w7w[5..5] & (! w7w[4..4])) & cs2a[1].cout)), ((((((! w7w[3..3]) & (! w7w[2..2])) & cs2a[0].cout) # (((! w7w[3..3]) & w7w[2..2]) & (! cs2a[0].cout))) # ((w7w[3..3] & w7w[2..2]) & (! cs2a[0].cout))) # ((w7w[3..3] & (! w7w[2..2])) & cs2a[0].cout)), w7w[0..0]);
- le3a[].in = (! ((! (((! ( B"0", dataa_node[], B"0")) & cs1a[0].sout) & (! cs2a[0].sout))) & (! ((((! ( B"0", B"0", dataa_node[])) & cs1a[0].sout) & cs2a[0].sout) # ((( B"0", B"0", dataa_node[]) & (! cs1a[0].sout)) & cs2a[0].sout)))));
- le4a[].in = (! ((! (((! ( B"0", dataa_node[], B"0")) & cs1a[1].sout) & (! cs2a[1].sout))) & (! ((((! ( B"0", B"0", dataa_node[])) & cs1a[1].sout) & cs2a[1].sout) # ((( B"0", B"0", dataa_node[]) & (! cs1a[1].sout)) & cs2a[1].sout)))));
- le5a[].in = ((cs1a[2].sout & ( dataa_node[], B"0")) # (cs2a[2].sout & ( B"0", dataa_node[])));
- sft11a[].in = ( w196w, ( w183w, ( le5a[3..3].out, ( le5a[2..2].out, ( le5a[1..1].out, ( le4a[2..2].out, ( le3a[3..2].out)))))));
- sft12a[].in = ( w196w, ( w196w, ( (! w117w[5..5]), ( le4a[4..4].out, ( le4a[3..3].out, ( le3a[4..4].out, ( w196w, cs1a[1].sout)))))));
- sft13a[].in = add10_result[];
- sft15a[].in = ( w196w, ( w183w, w183w));
- sft16a[].in = ( w196w, ( w196w, (! w70w[5..5])));
- sft17a[].in = add14_result[];
- sft7a[].in = ( w183w, ( w183w, ( le5a[4..4].out, ( sft13a[5..5].out, ( sft13a[4..4].out, ( sft13a[3..3].out, ( le5a[0..0].out, ( le4a[1..1].out, ( le4a[0..0].out, ( le3a[1..0].out))))))))));
- sft8a[].in = ( w196w, ( sft13a[7..7].out, ( sft13a[6..6].out, ( sft17a[2..2].out, ( sft17a[1..1].out, ( sft17a[0..0].out, ( sft13a[2..2].out, ( sft13a[1..1].out, ( sft13a[0..0].out, ( w196w, cs1a[0].sout))))))))));
- sft9a[].in = add6_result[];
- dataa_node[] = ( dataa[3..0]);
- datab_node[] = ( datab[3..0]);
- final_result_node[] = ( w257w[7..0]);
- result[] = ( final_result_node[7..0]);
- w117w[] = le4a[].out;
- w183w = B"1";
- w196w = B"0";
- w257w[] = ( sft9a[10..9].out, sft9a[8..7].out, sft9a[6..5].out, sft9a[4..3].out, sft9a[2..1].out, sft9a[0..0].out);
- w70w[] = le3a[].out;
- w7w[] = ( B"00", datab_node[]);
-END;
---VALID FILE
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/prev_cmp_ALUDemo.qmsg b/1ano/2semestre/lsd/pratica03/ALUDemo/db/prev_cmp_ALUDemo.qmsg
deleted file mode 100644
index 21006cb..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/prev_cmp_ALUDemo.qmsg
+++ /dev/null
@@ -1,28 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678792558545 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678792558545 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 14 11:15:58 2023 " "Processing started: Tue Mar 14 11:15:58 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678792558545 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678792558545 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ALUDemo -c ALUDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off ALUDemo -c ALUDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678792558545 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678792558643 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678792558643 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALU4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ALU4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALU4-Behavioral " "Found design unit 1: ALU4-Behavioral" { } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678792563739 ""} { "Info" "ISGN_ENTITY_NAME" "1 ALU4 " "Found entity 1: ALU4" { } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678792563739 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678792563739 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ALU4 " "Elaborating entity \"ALU4\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678792563764 ""}
-{ "Info" "ILPMS_INFERENCING_SUMMARY" "3 " "Inferred 3 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Mod0\"" { } { { "ALU4.vhd" "Mod0" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 28 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1678792564045 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult0\"" { } { { "ALU4.vhd" "Mult0" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 21 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1678792564045 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Div0\"" { } { { "ALU4.vhd" "Div0" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 27 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1678792564045 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1678792564045 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Mod0 " "Elaborated megafunction instantiation \"lpm_divide:Mod0\"" { } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 28 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678792564104 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_divide:Mod0 " "Instantiated megafunction \"lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 4 " "Parameter \"LPM_WIDTHN\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564104 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564104 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564104 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564104 ""} } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 28 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1678792564104 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_i9m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_i9m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_i9m " "Found entity 1: lpm_divide_i9m" { } { { "db/lpm_divide_i9m.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_i9m.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678792564127 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678792564127 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_7kh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_7kh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_7kh " "Found entity 1: sign_div_unsign_7kh" { } { { "db/sign_div_unsign_7kh.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/sign_div_unsign_7kh.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678792564129 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678792564129 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_24f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_24f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_24f " "Found entity 1: alt_u_div_24f" { } { { "db/alt_u_div_24f.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/alt_u_div_24f.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678792564132 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678792564132 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_7pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_7pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_7pc " "Found entity 1: add_sub_7pc" { } { { "db/add_sub_7pc.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_7pc.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678792564154 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678792564154 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_8pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_8pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_8pc " "Found entity 1: add_sub_8pc" { } { { "db/add_sub_8pc.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_8pc.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678792564176 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678792564176 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\"" { } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 21 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678792564211 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult0 " "Instantiated megafunction \"lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564211 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 4 " "Parameter \"LPM_WIDTHB\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564211 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 8 " "Parameter \"LPM_WIDTHP\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564211 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 8 " "Parameter \"LPM_WIDTHR\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564211 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564211 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564211 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564211 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564211 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564211 ""} } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 21 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1678792564211 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_j8t.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_j8t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_j8t " "Found entity 1: mult_j8t" { } { { "db/mult_j8t.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf" 29 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678792564231 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678792564231 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Div0 " "Elaborated megafunction instantiation \"lpm_divide:Div0\"" { } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 27 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678792564237 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_divide:Div0 " "Instantiated megafunction \"lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 4 " "Parameter \"LPM_WIDTHN\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678792564237 ""} } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 27 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1678792564237 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_fhm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_fhm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_fhm " "Found entity 1: lpm_divide_fhm" { } { { "db/lpm_divide_fhm.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_fhm.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678792564258 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678792564258 ""}
-{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "LCELL buffer " "Synthesized away the following LCELL buffer node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "lpm_mult:Mult0\|mult_j8t:auto_generated\|le5a\[4\] " "Synthesized away node \"lpm_mult:Mult0\|mult_j8t:auto_generated\|le5a\[4\]\"" { } { { "db/mult_j8t.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf" 43 6 0 } } { "lpm_mult.tdf" "" { Text "/home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_mult.tdf" 377 4 0 } } { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 21 -1 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1678792564280 "|ALU4|lpm_mult:Mult0|mult_j8t:auto_generated|le5a[4]"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1678792564280 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1678792564280 ""}
-{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "48 " "Ignored 48 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_CARRY_SUM" "4 " "Ignored 4 CARRY_SUM buffer(s)" { } { } 0 13016 "Ignored %1!d! CARRY_SUM buffer(s)" 0 0 "Design Software" 0 -1 1678792564417 ""} { "Info" "IMLS_MLS_IGNORED_SOFT" "44 " "Ignored 44 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Design Software" 0 -1 1678792564417 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Analysis & Synthesis" 0 -1 1678792564417 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678792564513 ""}
-{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "lpm_mult:Mult0\|mult_j8t:auto_generated\|le3a\[5\] " "Logic cell \"lpm_mult:Mult0\|mult_j8t:auto_generated\|le3a\[5\]\"" { } { { "db/mult_j8t.tdf" "le3a\[5\]" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf" 41 6 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1678792564905 ""} } { } 0 17016 "Found the following redundant logic cells in design" 0 0 "Analysis & Synthesis" 0 -1 1678792564905 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678792564966 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678792564966 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "117 " "Implemented 117 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678792565177 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678792565177 ""} { "Info" "ICUT_CUT_TM_LCELLS" "98 " "Implemented 98 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678792565177 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678792565177 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "438 " "Peak virtual memory: 438 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678792565181 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 14 11:16:05 2023 " "Processing ended: Tue Mar 14 11:16:05 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678792565181 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678792565181 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678792565181 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678792565181 ""}
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/db/sign_div_unsign_7kh.tdf b/1ano/2semestre/lsd/pratica03/ALUDemo/db/sign_div_unsign_7kh.tdf
deleted file mode 100644
index 3ac594b..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/db/sign_div_unsign_7kh.tdf
+++ /dev/null
@@ -1,47 +0,0 @@
---sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=4 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=4 SKIP_BITS=0 denominator numerator quotient remainder
---VERSION_BEGIN 20.1 cbx_cycloneii 2020:11:11:17:03:37:SJ cbx_lpm_abs 2020:11:11:17:03:37:SJ cbx_lpm_add_sub 2020:11:11:17:03:37:SJ cbx_lpm_divide 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ cbx_nadder 2020:11:11:17:03:37:SJ cbx_stratix 2020:11:11:17:03:37:SJ cbx_stratixii 2020:11:11:17:03:37:SJ cbx_util_mgl 2020:11:11:17:03:37:SJ VERSION_END
-
-
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
-
-FUNCTION alt_u_div_24f (denominator[3..0], numerator[3..0])
-RETURNS ( quotient[3..0], remainder[3..0]);
-
---synthesis_resources = lut 9
-SUBDESIGN sign_div_unsign_7kh
-(
- denominator[3..0] : input;
- numerator[3..0] : input;
- quotient[3..0] : output;
- remainder[3..0] : output;
-)
-VARIABLE
- divider : alt_u_div_24f;
- norm_num[3..0] : WIRE;
- protect_quotient[3..0] : WIRE;
- protect_remainder[3..0] : WIRE;
-
-BEGIN
- divider.denominator[] = denominator[];
- divider.numerator[] = norm_num[];
- norm_num[] = numerator[];
- protect_quotient[] = divider.quotient[];
- protect_remainder[] = divider.remainder[];
- quotient[] = protect_quotient[];
- remainder[] = protect_remainder[];
-END;
---VALID FILE
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/README b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.db_info b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.db_info
deleted file mode 100644
index 7944e35..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Tue Mar 14 11:16:03 2023
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.ammdb
deleted file mode 100644
index 97ee03e..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.cdb
deleted file mode 100644
index 9d3e216..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.dfp and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.hdb
deleted file mode 100644
index f4917f3..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.rcfdb
deleted file mode 100644
index 18d5624..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.cmp.rcfdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.cdb
deleted file mode 100644
index 89a408d..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.dpi
deleted file mode 100644
index 05c9b05..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.dpi and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hbdb.cdb
deleted file mode 100644
index ddbdf05..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hbdb.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hbdb.hdb
deleted file mode 100644
index 0e056be..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hdb
deleted file mode 100644
index 657534f..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.kpt
deleted file mode 100644
index 757f897..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.root_partition.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.rrp.hdb b/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.rrp.hdb
deleted file mode 100644
index b1e2b79..0000000
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/incremental_db/compiled_partitions/ALUDemo.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.asm.rpt b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.asm.rpt
deleted file mode 100644
index 54f8f7d..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for ALUDemo
-Thu Mar 16 16:33:28 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: ALUDemo.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Thu Mar 16 16:33:28 2023 ;
-; Revision Name ; ALUDemo ;
-; Top-level Entity Name ; ALU4 ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+------------------------------------------------------------------------------------------------+
-; File Name ;
-+------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sof ;
-+------------------------------------------------------------------------------------------------+
-
-
-+---------------------------------------+
-; Assembler Device Options: ALUDemo.sof ;
-+----------------+----------------------+
-; Option ; Setting ;
-+----------------+----------------------+
-; JTAG usercode ; 0x00570543 ;
-; Checksum ; 0x00570543 ;
-+----------------+----------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Thu Mar 16 16:33:26 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ALUDemo -c ALUDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 369 megabytes
- Info: Processing ended: Thu Mar 16 16:33:28 2023
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.done b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.done
deleted file mode 100644
index b7e8f1d..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.done
+++ /dev/null
@@ -1 +0,0 @@
-Thu Mar 16 16:33:31 2023
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.eda.rpt b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.eda.rpt
deleted file mode 100644
index 55bb543..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.eda.rpt
+++ /dev/null
@@ -1,94 +0,0 @@
-EDA Netlist Writer report for ALUDemo
-Thu Mar 16 16:33:31 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Thu Mar 16 16:33:31 2023 ;
-; Revision Name ; ALUDemo ;
-; Top-level Entity Name ; ALU4 ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+-------------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+-------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/simulation/modelsim/ALUDemo.vho ;
-+-------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Thu Mar 16 16:33:31 2023
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ALUDemo -c ALUDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file ALUDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 612 megabytes
- Info: Processing ended: Thu Mar 16 16:33:31 2023
- Info: Elapsed time: 00:00:00
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.fit.rpt b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.fit.rpt
deleted file mode 100644
index e2aca89..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.fit.rpt
+++ /dev/null
@@ -1,2826 +0,0 @@
-Fitter report for ALUDemo
-Thu Mar 16 16:33:25 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Thu Mar 16 16:33:25 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; ALUDemo ;
-; Top-level Entity Name ; ALU4 ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 98 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 98 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 19 / 529 ( 4 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.2% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; CLOCK_50 ; PIN_Y2 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
-; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
-; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
-; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
-; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
-; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
-; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[0] ; PIN_M23 ; QSF Assignment ;
-; Location ; ; ; KEY[1] ; PIN_M21 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[0] ; PIN_E21 ; QSF Assignment ;
-; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
-; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
-; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[0] ; PIN_G19 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[1] ; PIN_F19 ; QSF Assignment ;
-; Location ; ; ; LEDR[2] ; PIN_E19 ; QSF Assignment ;
-; Location ; ; ; LEDR[3] ; PIN_F21 ; QSF Assignment ;
-; Location ; ; ; LEDR[4] ; PIN_F18 ; QSF Assignment ;
-; Location ; ; ; LEDR[5] ; PIN_E18 ; QSF Assignment ;
-; Location ; ; ; LEDR[6] ; PIN_J19 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_H19 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; SW[0] ; PIN_AB28 ; QSF Assignment ;
-; Location ; ; ; SW[10] ; PIN_AC24 ; QSF Assignment ;
-; Location ; ; ; SW[11] ; PIN_AB24 ; QSF Assignment ;
-; Location ; ; ; SW[12] ; PIN_AB23 ; QSF Assignment ;
-; Location ; ; ; SW[13] ; PIN_AA24 ; QSF Assignment ;
-; Location ; ; ; SW[14] ; PIN_AA23 ; QSF Assignment ;
-; Location ; ; ; SW[15] ; PIN_AA22 ; QSF Assignment ;
-; Location ; ; ; SW[16] ; PIN_Y24 ; QSF Assignment ;
-; Location ; ; ; SW[17] ; PIN_Y23 ; QSF Assignment ;
-; Location ; ; ; SW[1] ; PIN_AC28 ; QSF Assignment ;
-; Location ; ; ; SW[2] ; PIN_AC27 ; QSF Assignment ;
-; Location ; ; ; SW[3] ; PIN_AD27 ; QSF Assignment ;
-; Location ; ; ; SW[4] ; PIN_AB27 ; QSF Assignment ;
-; Location ; ; ; SW[5] ; PIN_AC26 ; QSF Assignment ;
-; Location ; ; ; SW[6] ; PIN_AD26 ; QSF Assignment ;
-; Location ; ; ; SW[7] ; PIN_AB26 ; QSF Assignment ;
-; Location ; ; ; SW[8] ; PIN_AC25 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AB25 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 147 ) ; 0.00 % ( 0 / 147 ) ; 0.00 % ( 0 / 147 ) ;
-; -- Achieved ; 0.00 % ( 0 / 147 ) ; 0.00 % ( 0 / 147 ) ; 0.00 % ( 0 / 147 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+--------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 137 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.pin.
-
-
-+----------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+------------------------+
-; Total logic elements ; 98 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 98 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 42 ;
-; -- 3 input functions ; 37 ;
-; -- <=2 input functions ; 19 ;
-; -- Register only ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 68 ;
-; -- arithmetic mode ; 30 ;
-; ; ;
-; Total registers* ; 0 / 117,053 ( 0 % ) ;
-; -- Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 7 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 19 / 529 ( 4 % ) ;
-; -- Clock pins ; 0 / 7 ( 0 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.7% / 0.7% / 0.6% ;
-; Maximum fan-out ; 24 ;
-; Highest non-global fan-out ; 24 ;
-; Total fan-out ; 340 ;
-; Average fan-out ; 2.33 ;
-+---------------------------------------------+------------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 98 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 98 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 42 ; 0 ;
-; -- 3 input functions ; 37 ; 0 ;
-; -- <=2 input functions ; 19 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 68 ; 0 ;
-; -- arithmetic mode ; 30 ; 0 ;
-; ; ; ;
-; Total registers ; 0 ; 0 ;
-; -- Dedicated logic registers ; 0 / 114480 ( 0 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 7 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 19 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 335 ; 5 ;
-; -- Registered Connections ; 0 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 11 ; 0 ;
-; -- Output Ports ; 8 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+-----------------------+--------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; a[0] ; H17 ; 7 ; 67 ; 73 ; 7 ; 10 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; a[1] ; G15 ; 7 ; 65 ; 73 ; 7 ; 11 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; a[2] ; C16 ; 7 ; 62 ; 73 ; 14 ; 10 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; a[3] ; J16 ; 7 ; 65 ; 73 ; 14 ; 10 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; b[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; 16 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; b[1] ; J17 ; 7 ; 69 ; 73 ; 0 ; 24 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; b[2] ; H16 ; 7 ; 65 ; 73 ; 21 ; 17 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; b[3] ; G18 ; 7 ; 69 ; 73 ; 21 ; 21 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; op[0] ; G22 ; 7 ; 72 ; 73 ; 21 ; 18 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; op[1] ; G16 ; 7 ; 67 ; 73 ; 0 ; 14 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; op[2] ; H19 ; 7 ; 72 ; 73 ; 0 ; 6 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; m[0] ; J19 ; 7 ; 72 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
-; m[1] ; E17 ; 7 ; 67 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
-; m[2] ; F17 ; 7 ; 67 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
-; m[3] ; B17 ; 7 ; 60 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
-; r[0] ; J15 ; 7 ; 60 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
-; r[1] ; D16 ; 7 ; 62 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
-; r[2] ; H21 ; 7 ; 72 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
-; r[3] ; A17 ; 7 ; 60 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
-+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-; C16 ; DIFFIO_T36n, PADD9 ; Use as regular IO ; a[2] ; Dual Purpose Pin ;
-; D16 ; DIFFIO_T36p, PADD10 ; Use as regular IO ; r[1] ; Dual Purpose Pin ;
-; A17 ; DIFFIO_T35n, PADD11 ; Use as regular IO ; r[3] ; Dual Purpose Pin ;
-; B17 ; DIFFIO_T35p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO ; m[3] ; Dual Purpose Pin ;
-+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 0 / 63 ( 0 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 0 / 65 ( 0 % ) ; 2.5V ; -- ;
-; 6 ; 1 / 58 ( 2 % ) ; 2.5V ; -- ;
-; 7 ; 19 / 72 ( 26 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; r[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA23 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA24 ; 279 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB24 ; 274 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB25 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB26 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB27 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB28 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC25 ; 272 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC26 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC27 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC28 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD27 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; m[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; a[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; r[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; m[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; E18 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; m[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; F18 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; a[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; G16 ; 453 ; 7 ; op[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; b[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; G19 ; 451 ; 7 ; b[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; op[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; b[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; H17 ; 454 ; 7 ; a[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; op[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; r[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; r[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; J16 ; 458 ; 7 ; a[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; J17 ; 450 ; 7 ; b[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; m[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y24 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; r[0] ; Incomplete set of assignments ;
-; r[1] ; Incomplete set of assignments ;
-; r[2] ; Incomplete set of assignments ;
-; r[3] ; Incomplete set of assignments ;
-; m[0] ; Incomplete set of assignments ;
-; m[1] ; Incomplete set of assignments ;
-; m[2] ; Incomplete set of assignments ;
-; m[3] ; Incomplete set of assignments ;
-; b[0] ; Incomplete set of assignments ;
-; a[0] ; Incomplete set of assignments ;
-; op[1] ; Incomplete set of assignments ;
-; op[0] ; Incomplete set of assignments ;
-; a[3] ; Incomplete set of assignments ;
-; b[3] ; Incomplete set of assignments ;
-; b[2] ; Incomplete set of assignments ;
-; b[1] ; Incomplete set of assignments ;
-; a[2] ; Incomplete set of assignments ;
-; a[1] ; Incomplete set of assignments ;
-; op[2] ; Incomplete set of assignments ;
-; r[0] ; Missing location assignment ;
-; r[1] ; Missing location assignment ;
-; r[2] ; Missing location assignment ;
-; r[3] ; Missing location assignment ;
-; m[0] ; Missing location assignment ;
-; m[1] ; Missing location assignment ;
-; m[2] ; Missing location assignment ;
-; m[3] ; Missing location assignment ;
-; b[0] ; Missing location assignment ;
-; a[0] ; Missing location assignment ;
-; op[1] ; Missing location assignment ;
-; op[0] ; Missing location assignment ;
-; a[3] ; Missing location assignment ;
-; b[3] ; Missing location assignment ;
-; b[2] ; Missing location assignment ;
-; b[1] ; Missing location assignment ;
-; a[2] ; Missing location assignment ;
-; a[1] ; Missing location assignment ;
-; op[2] ; Missing location assignment ;
-+----------+-------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------+---------------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------+---------------------+--------------+
-; |ALU4 ; 98 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; 98 (32) ; 0 (0) ; 0 (0) ; |ALU4 ; ALU4 ; work ;
-; |lpm_divide:Div0| ; 13 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (0) ; 0 (0) ; 0 (0) ; |ALU4|lpm_divide:Div0 ; lpm_divide ; work ;
-; |lpm_divide_fhm:auto_generated| ; 13 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (0) ; 0 (0) ; 0 (0) ; |ALU4|lpm_divide:Div0|lpm_divide_fhm:auto_generated ; lpm_divide_fhm ; work ;
-; |sign_div_unsign_7kh:divider| ; 13 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (0) ; 0 (0) ; 0 (0) ; |ALU4|lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider ; sign_div_unsign_7kh ; work ;
-; |alt_u_div_24f:divider| ; 13 (13) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 0 (0) ; |ALU4|lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider ; alt_u_div_24f ; work ;
-; |lpm_divide:Mod0| ; 22 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (0) ; 0 (0) ; 0 (0) ; |ALU4|lpm_divide:Mod0 ; lpm_divide ; work ;
-; |lpm_divide_i9m:auto_generated| ; 22 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (0) ; 0 (0) ; 0 (0) ; |ALU4|lpm_divide:Mod0|lpm_divide_i9m:auto_generated ; lpm_divide_i9m ; work ;
-; |sign_div_unsign_7kh:divider| ; 22 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (0) ; 0 (0) ; 0 (0) ; |ALU4|lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider ; sign_div_unsign_7kh ; work ;
-; |alt_u_div_24f:divider| ; 22 (22) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (22) ; 0 (0) ; 0 (0) ; |ALU4|lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider ; alt_u_div_24f ; work ;
-; |lpm_mult:Mult0| ; 31 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (0) ; 0 (0) ; 0 (0) ; |ALU4|lpm_mult:Mult0 ; lpm_mult ; work ;
-; |mult_j8t:auto_generated| ; 31 (31) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 0 (0) ; 0 (0) ; |ALU4|lpm_mult:Mult0|mult_j8t:auto_generated ; mult_j8t ; work ;
-+----------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------+---------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+---------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+-------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+-------+----------+---------------+---------------+-----------------------+-----+------+
-; r[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; r[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; r[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; r[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; m[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; m[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; m[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; m[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; b[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; a[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; op[1] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; op[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; a[3] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; b[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; b[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; b[1] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; a[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; a[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; op[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-+-------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+----------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+----------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
-; b[0] ; ; ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_3_result_int[0]~0 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_2_result_int[0]~0 ; 0 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_2_result_int[0]~0 ; 0 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_3_result_int[0]~1 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[5]~0 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[4]~2 ; 0 ; 6 ;
-; - Mux3~1 ; 0 ; 6 ;
-; - Mux3~2 ; 0 ; 6 ;
-; - Add0~0 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|selnose[5]~1 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|selnose[0] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[0] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[1] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[2] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[3] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[4] ; 0 ; 6 ;
-; a[0] ; ; ;
-; - Add0~3 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_3_result_int[0]~0 ; 0 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_3_result_int[0]~1 ; 0 ; 6 ;
-; - Mux3~0 ; 0 ; 6 ;
-; - Mux3~2 ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[0] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[1] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[0] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[1] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[0] ; 0 ; 6 ;
-; op[1] ; ; ;
-; - Mux3~1 ; 1 ; 6 ;
-; - Mux3~2 ; 1 ; 6 ;
-; - Mux3~3 ; 1 ; 6 ;
-; - Mux3~4 ; 1 ; 6 ;
-; - m~8 ; 1 ; 6 ;
-; - m~9 ; 1 ; 6 ;
-; - m~10 ; 1 ; 6 ;
-; - m~11 ; 1 ; 6 ;
-; - Mux0~2 ; 1 ; 6 ;
-; - Mux0~3 ; 1 ; 6 ;
-; - Mux1~2 ; 1 ; 6 ;
-; - Mux1~3 ; 1 ; 6 ;
-; - Mux2~2 ; 1 ; 6 ;
-; - Mux2~3 ; 1 ; 6 ;
-; op[0] ; ; ;
-; - Add0~2 ; 1 ; 6 ;
-; - Mux3~0 ; 1 ; 6 ;
-; - Mux3~1 ; 1 ; 6 ;
-; - Mux3~3 ; 1 ; 6 ;
-; - Add0~0 ; 1 ; 6 ;
-; - Add0~5 ; 1 ; 6 ;
-; - Add0~8 ; 1 ; 6 ;
-; - Add0~11 ; 1 ; 6 ;
-; - m~8 ; 1 ; 6 ;
-; - m~9 ; 1 ; 6 ;
-; - m~10 ; 1 ; 6 ;
-; - m~11 ; 1 ; 6 ;
-; - Mux0~2 ; 1 ; 6 ;
-; - Mux0~3 ; 1 ; 6 ;
-; - Mux1~2 ; 1 ; 6 ;
-; - Mux1~3 ; 1 ; 6 ;
-; - Mux2~2 ; 1 ; 6 ;
-; - Mux2~3 ; 1 ; 6 ;
-; a[3] ; ; ;
-; - Add0~12 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[5]~1 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|selnose[5]~0 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|selnose[0] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[3] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[4] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[3] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[4] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[3] ; 0 ; 6 ;
-; - Mux0~2 ; 0 ; 6 ;
-; b[3] ; ; ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_3_result_int[3]~6 ; 1 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_3_result_int[3]~7 ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[5]~1 ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|selnose[5]~0 ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[10]~3 ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[9]~4 ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[8]~5 ; 1 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[10]~0 ; 1 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[9]~1 ; 1 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[8]~2 ; 1 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|selnose[10] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[5] ; 1 ; 6 ;
-; - Add0~11 ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|selnose[0]~2 ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[0] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[0] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[1] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[4] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[2] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[3] ; 1 ; 6 ;
-; - Mux0~2 ; 1 ; 6 ;
-; b[2] ; ; ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_3_result_int[2]~4 ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_2_result_int[2]~4 ; 1 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_2_result_int[2]~4 ; 1 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_3_result_int[2]~5 ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[5]~1 ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|selnose[5]~0 ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[5] ; 1 ; 6 ;
-; - Add0~8 ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|selnose[0]~2 ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[0] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|cs2a[1]~0 ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[0] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[1] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[4] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[2] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[3] ; 1 ; 6 ;
-; - Mux1~2 ; 1 ; 6 ;
-; b[1] ; ; ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_3_result_int[1]~2 ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_2_result_int[1]~2 ; 1 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_2_result_int[1]~2 ; 1 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_3_result_int[1]~3 ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|op_3~0 ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[5]~0 ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|selnose[5]~0 ; 1 ; 6 ;
-; - Add0~5 ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[5] ; 1 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|selnose[0] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[0] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[1] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[2] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[0] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[3] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|cs2a[1]~0 ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[4] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[0] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[1] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[4] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[2] ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[3] ; 1 ; 6 ;
-; - Mux2~2 ; 1 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[5] ; 1 ; 6 ;
-; a[2] ; ; ;
-; - Add0~9 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[5]~0 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[4]~2 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|selnose[5]~1 ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[2] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[3] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[2] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[3] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[2] ; 0 ; 6 ;
-; - Mux1~2 ; 0 ; 6 ;
-; a[1] ; ; ;
-; - Add0~6 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_2_result_int[0]~0 ; 0 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|add_sub_2_result_int[0]~0 ; 0 ; 6 ;
-; - lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[8]~5 ; 0 ; 6 ;
-; - lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider|StageOut[8]~2 ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[1] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le3a[2] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[1] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le4a[2] ; 0 ; 6 ;
-; - lpm_mult:Mult0|mult_j8t:auto_generated|le5a[1] ; 0 ; 6 ;
-; - Mux2~2 ; 0 ; 6 ;
-; op[2] ; ; ;
-; - Mux3~3 ; 0 ; 6 ;
-; - Mux3~4 ; 0 ; 6 ;
-; - m~8 ; 0 ; 6 ;
-; - m~9 ; 0 ; 6 ;
-; - m~10 ; 0 ; 6 ;
-; - m~11 ; 0 ; 6 ;
-+----------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
-
-
-+-------------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+-------------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+-------------------------+
-; Block interconnects ; 117 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 0 / 10,120 ( 0 % ) ;
-; C4 interconnects ; 38 / 209,544 ( < 1 % ) ;
-; Direct links ; 32 / 342,891 ( < 1 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 41 / 119,088 ( < 1 % ) ;
-; R24 interconnects ; 0 / 9,963 ( 0 % ) ;
-; R4 interconnects ; 44 / 289,782 ( < 1 % ) ;
-+-----------------------+-------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+---------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 14.00) ; Number of LABs (Total = 7) ;
-+---------------------------------------------+-----------------------------+
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 1 ;
-; 16 ; 5 ;
-+---------------------------------------------+-----------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+----------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 13.29) ; Number of LABs (Total = 7) ;
-+----------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 1 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 1 ;
-; 16 ; 4 ;
-+----------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 7.43) ; Number of LABs (Total = 7) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 1 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 1 ;
-; 8 ; 1 ;
-; 9 ; 2 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 1 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+----------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 13.29) ; Number of LABs (Total = 7) ;
-+----------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 1 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-; 9 ; 0 ;
-; 10 ; 1 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 1 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-; 17 ; 0 ;
-; 18 ; 1 ;
-; 19 ; 0 ;
-; 20 ; 2 ;
-+----------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 9 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 21 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
-; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 11 ; 8 ; 0 ; 11 ; 0 ; 0 ; 8 ; 0 ; 19 ; 19 ; 19 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 19 ; 19 ; 19 ; 19 ; 19 ; 0 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 11 ; 19 ; 19 ; 19 ; 8 ; 11 ; 19 ; 8 ; 19 ; 19 ; 11 ; 19 ; 0 ; 0 ; 0 ; 19 ; 19 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; r[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; r[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; r[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; r[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; m[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; m[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; m[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; m[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; b[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; a[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; op[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; op[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; a[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; b[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; b[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; b[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; a[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; a[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; op[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "ALUDemo"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (169085): No exact pin location assignment(s) for 19 pins of 19 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ALUDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
- Info (176211): Number of I/O pins in group: 19 (unused VREF, 2.5V VCCIO, 11 input, 8 output, 0 bidirectional)
- Info (176212): I/O standards used: 2.5 V.
-Info (176215): I/O bank details before I/O pin placement
- Info (176214): Statistics of I/O banks
- Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 52 pins available
- Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 63 pins available
- Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 73 pins available
- Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 71 pins available
- Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 65 pins available
- Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 57 pins available
- Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 72 pins available
- Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 71 pins available
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X58_Y61 to location X68_Y73
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 527 warnings
- Info: Peak virtual memory: 1154 megabytes
- Info: Processing ended: Thu Mar 16 16:33:26 2023
- Info: Elapsed time: 00:00:08
- Info: Total CPU time (on all processors): 00:00:09
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.fit.smsg b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.fit.summary b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.fit.summary
deleted file mode 100644
index 578d2ab..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Thu Mar 16 16:33:25 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : ALUDemo
-Top-level Entity Name : ALU4
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 98 / 114,480 ( < 1 % )
- Total combinational functions : 98 / 114,480 ( < 1 % )
- Dedicated logic registers : 0 / 114,480 ( 0 % )
-Total registers : 0
-Total pins : 19 / 529 ( 4 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.flow.rpt b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.flow.rpt
deleted file mode 100644
index 7c927bb..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.flow.rpt
+++ /dev/null
@@ -1,135 +0,0 @@
-Flow report for ALUDemo
-Thu Mar 16 16:33:31 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Thu Mar 16 16:33:31 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; ALUDemo ;
-; Top-level Entity Name ; ALU4 ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 98 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 98 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 19 / 529 ( 4 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/16/2023 16:33:11 ;
-; Main task ; Compilation ;
-; Revision Name ; ALUDemo ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 2690080394329.167898439105098 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; ALU4 ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; ALU4 ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; ALU4 ; Top ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-; TOP_LEVEL_ENTITY ; ALU4 ; ALUDemo ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 439 MB ; 00:00:16 ;
-; Fitter ; 00:00:07 ; 1.0 ; 1154 MB ; 00:00:09 ;
-; Assembler ; 00:00:02 ; 1.0 ; 369 MB ; 00:00:02 ;
-; Timing Analyzer ; 00:00:01 ; 1.0 ; 536 MB ; 00:00:01 ;
-; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 612 MB ; 00:00:00 ;
-; Total ; 00:00:17 ; -- ; -- ; 00:00:28 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off ALUDemo -c ALUDemo
-quartus_fit --read_settings_files=off --write_settings_files=off ALUDemo -c ALUDemo
-quartus_asm --read_settings_files=off --write_settings_files=off ALUDemo -c ALUDemo
-quartus_sta ALUDemo -c ALUDemo
-quartus_eda --read_settings_files=off --write_settings_files=off ALUDemo -c ALUDemo
-
-
-
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.jdi b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.jdi
deleted file mode 100644
index a7566e9..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.map.rpt b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.map.rpt
deleted file mode 100644
index 1df4cba..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.map.rpt
+++ /dev/null
@@ -1,481 +0,0 @@
-Analysis & Synthesis report for ALUDemo
-Thu Mar 16 16:33:18 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Multiplexer Restructuring Statistics (Restructuring Performed)
- 10. Parameter Settings for Inferred Entity Instance: lpm_divide:Mod0
- 11. Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0
- 12. Parameter Settings for Inferred Entity Instance: lpm_divide:Div0
- 13. lpm_mult Parameter Settings by Entity Instance
- 14. Post-Synthesis Netlist Statistics for Top Partition
- 15. Elapsed Time Per Partition
- 16. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Thu Mar 16 16:33:18 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; ALUDemo ;
-; Top-level Entity Name ; ALU4 ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 98 ;
-; Total combinational functions ; 98 ;
-; Dedicated logic registers ; 0 ;
-; Total registers ; 0 ;
-; Total pins ; 19 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; ALU4 ; ALUDemo ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------+---------+
-; ALU4.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd ; ;
-; lpm_divide.tdf ; yes ; Megafunction ; /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_divide.tdf ; ;
-; abs_divider.inc ; yes ; Megafunction ; /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/abs_divider.inc ; ;
-; sign_div_unsign.inc ; yes ; Megafunction ; /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/sign_div_unsign.inc ; ;
-; aglobal201.inc ; yes ; Megafunction ; /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/aglobal201.inc ; ;
-; db/lpm_divide_i9m.tdf ; yes ; Auto-Generated Megafunction ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_i9m.tdf ; ;
-; db/sign_div_unsign_7kh.tdf ; yes ; Auto-Generated Megafunction ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/sign_div_unsign_7kh.tdf ; ;
-; db/alt_u_div_24f.tdf ; yes ; Auto-Generated Megafunction ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/alt_u_div_24f.tdf ; ;
-; db/add_sub_7pc.tdf ; yes ; Auto-Generated Megafunction ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_7pc.tdf ; ;
-; db/add_sub_8pc.tdf ; yes ; Auto-Generated Megafunction ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_8pc.tdf ; ;
-; lpm_mult.tdf ; yes ; Megafunction ; /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_mult.tdf ; ;
-; lpm_add_sub.inc ; yes ; Megafunction ; /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ;
-; multcore.inc ; yes ; Megafunction ; /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/multcore.inc ; ;
-; bypassff.inc ; yes ; Megafunction ; /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/bypassff.inc ; ;
-; altshift.inc ; yes ; Megafunction ; /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/altshift.inc ; ;
-; db/mult_j8t.tdf ; yes ; Auto-Generated Megafunction ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf ; ;
-; db/lpm_divide_fhm.tdf ; yes ; Auto-Generated Megafunction ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_fhm.tdf ; ;
-+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------+---------+
-
-
-+----------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+------------+
-; Resource ; Usage ;
-+---------------------------------------------+------------+
-; Estimated Total logic elements ; 98 ;
-; ; ;
-; Total combinational functions ; 98 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 42 ;
-; -- 3 input functions ; 37 ;
-; -- <=2 input functions ; 19 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 68 ;
-; -- arithmetic mode ; 30 ;
-; ; ;
-; Total registers ; 0 ;
-; -- Dedicated logic registers ; 0 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 19 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; b[1]~input ;
-; Maximum fan-out ; 24 ;
-; Total fan-out ; 335 ;
-; Average fan-out ; 2.46 ;
-+---------------------------------------------+------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------+---------------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------+---------------------+--------------+
-; |ALU4 ; 98 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; |ALU4 ; ALU4 ; work ;
-; |lpm_divide:Div0| ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ALU4|lpm_divide:Div0 ; lpm_divide ; work ;
-; |lpm_divide_fhm:auto_generated| ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ALU4|lpm_divide:Div0|lpm_divide_fhm:auto_generated ; lpm_divide_fhm ; work ;
-; |sign_div_unsign_7kh:divider| ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ALU4|lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider ; sign_div_unsign_7kh ; work ;
-; |alt_u_div_24f:divider| ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ALU4|lpm_divide:Div0|lpm_divide_fhm:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider ; alt_u_div_24f ; work ;
-; |lpm_divide:Mod0| ; 22 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ALU4|lpm_divide:Mod0 ; lpm_divide ; work ;
-; |lpm_divide_i9m:auto_generated| ; 22 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ALU4|lpm_divide:Mod0|lpm_divide_i9m:auto_generated ; lpm_divide_i9m ; work ;
-; |sign_div_unsign_7kh:divider| ; 22 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ALU4|lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider ; sign_div_unsign_7kh ; work ;
-; |alt_u_div_24f:divider| ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ALU4|lpm_divide:Mod0|lpm_divide_i9m:auto_generated|sign_div_unsign_7kh:divider|alt_u_div_24f:divider ; alt_u_div_24f ; work ;
-; |lpm_mult:Mult0| ; 31 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ALU4|lpm_mult:Mult0 ; lpm_mult ; work ;
-; |mult_j8t:auto_generated| ; 31 (31) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ALU4|lpm_mult:Mult0|mult_j8t:auto_generated ; mult_j8t ; work ;
-+----------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------+---------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 0 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; 8:1 ; 4 bits ; 20 LEs ; 16 LEs ; 4 LEs ; No ; |ALU4|Mux3 ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-
-
-+------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: lpm_divide:Mod0 ;
-+------------------------+----------------+------------------------+
-; Parameter Name ; Value ; Type ;
-+------------------------+----------------+------------------------+
-; LPM_WIDTHN ; 4 ; Untyped ;
-; LPM_WIDTHD ; 4 ; Untyped ;
-; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
-; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
-; LPM_PIPELINE ; 0 ; Untyped ;
-; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
-; MAXIMIZE_SPEED ; 5 ; Untyped ;
-; CBXI_PARAMETER ; lpm_divide_i9m ; Untyped ;
-; CARRY_CHAIN ; MANUAL ; Untyped ;
-; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
-; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
-; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
-; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
-; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
-+------------------------+----------------+------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-------------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0 ;
-+------------------------------------------------+--------------+---------------------+
-; Parameter Name ; Value ; Type ;
-+------------------------------------------------+--------------+---------------------+
-; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
-; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
-; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
-; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
-; LPM_WIDTHA ; 4 ; Untyped ;
-; LPM_WIDTHB ; 4 ; Untyped ;
-; LPM_WIDTHP ; 8 ; Untyped ;
-; LPM_WIDTHR ; 8 ; Untyped ;
-; LPM_WIDTHS ; 1 ; Untyped ;
-; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
-; LPM_PIPELINE ; 0 ; Untyped ;
-; LATENCY ; 0 ; Untyped ;
-; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
-; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
-; USE_EAB ; OFF ; Untyped ;
-; MAXIMIZE_SPEED ; 5 ; Untyped ;
-; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
-; CARRY_CHAIN ; MANUAL ; Untyped ;
-; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
-; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;
-; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
-; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
-; CBXI_PARAMETER ; mult_j8t ; Untyped ;
-; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
-; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
-; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
-+------------------------------------------------+--------------+---------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: lpm_divide:Div0 ;
-+------------------------+----------------+------------------------+
-; Parameter Name ; Value ; Type ;
-+------------------------+----------------+------------------------+
-; LPM_WIDTHN ; 4 ; Untyped ;
-; LPM_WIDTHD ; 4 ; Untyped ;
-; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
-; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
-; LPM_PIPELINE ; 0 ; Untyped ;
-; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
-; MAXIMIZE_SPEED ; 5 ; Untyped ;
-; CBXI_PARAMETER ; lpm_divide_fhm ; Untyped ;
-; CARRY_CHAIN ; MANUAL ; Untyped ;
-; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
-; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
-; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
-; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
-; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
-+------------------------+----------------+------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------+
-; lpm_mult Parameter Settings by Entity Instance ;
-+---------------------------------------+----------------+
-; Name ; Value ;
-+---------------------------------------+----------------+
-; Number of entity instances ; 1 ;
-; Entity Instance ; lpm_mult:Mult0 ;
-; -- LPM_WIDTHA ; 4 ;
-; -- LPM_WIDTHB ; 4 ;
-; -- LPM_WIDTHP ; 8 ;
-; -- LPM_REPRESENTATION ; UNSIGNED ;
-; -- INPUT_A_IS_CONSTANT ; NO ;
-; -- INPUT_B_IS_CONSTANT ; NO ;
-; -- USE_EAB ; OFF ;
-; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ;
-; -- INPUT_A_FIXED_VALUE ; Bx ;
-; -- INPUT_B_FIXED_VALUE ; Bx ;
-+---------------------------------------+----------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 19 ;
-; cycloneiii_lcell_comb ; 98 ;
-; arith ; 30 ;
-; 2 data inputs ; 3 ;
-; 3 data inputs ; 27 ;
-; normal ; 68 ;
-; 0 data inputs ; 4 ;
-; 1 data inputs ; 1 ;
-; 2 data inputs ; 11 ;
-; 3 data inputs ; 10 ;
-; 4 data inputs ; 42 ;
-; ; ;
-; Max LUT depth ; 9.50 ;
-; Average LUT depth ; 6.14 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Thu Mar 16 16:33:11 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ALUDemo -c ALUDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 2 design units, including 1 entities, in source file ALU4.vhd
- Info (12022): Found design unit 1: ALU4-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd Line: 14
- Info (12023): Found entity 1: ALU4 File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd Line: 5
-Info (12021): Found 1 design units, including 1 entities, in source file ALUDemo.bdf
- Info (12023): Found entity 1: ALUDemo
-Info (12127): Elaborating entity "ALU4" for the top level hierarchy
-Info (278001): Inferred 3 megafunctions from design logic
- Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Mod0" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd Line: 28
- Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "Mult0" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd Line: 21
- Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div0" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd Line: 27
-Info (12130): Elaborated megafunction instantiation "lpm_divide:Mod0" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd Line: 28
-Info (12133): Instantiated megafunction "lpm_divide:Mod0" with the following parameter: File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd Line: 28
- Info (12134): Parameter "LPM_WIDTHN" = "4"
- Info (12134): Parameter "LPM_WIDTHD" = "4"
- Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
- Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
-Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_i9m.tdf
- Info (12023): Found entity 1: lpm_divide_i9m File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_i9m.tdf Line: 25
-Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_7kh.tdf
- Info (12023): Found entity 1: sign_div_unsign_7kh File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/sign_div_unsign_7kh.tdf Line: 25
-Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_24f.tdf
- Info (12023): Found entity 1: alt_u_div_24f File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/alt_u_div_24f.tdf Line: 27
-Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_7pc.tdf
- Info (12023): Found entity 1: add_sub_7pc File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_7pc.tdf Line: 23
-Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_8pc.tdf
- Info (12023): Found entity 1: add_sub_8pc File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_8pc.tdf Line: 23
-Info (12130): Elaborated megafunction instantiation "lpm_mult:Mult0" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd Line: 21
-Info (12133): Instantiated megafunction "lpm_mult:Mult0" with the following parameter: File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd Line: 21
- Info (12134): Parameter "LPM_WIDTHA" = "4"
- Info (12134): Parameter "LPM_WIDTHB" = "4"
- Info (12134): Parameter "LPM_WIDTHP" = "8"
- Info (12134): Parameter "LPM_WIDTHR" = "8"
- Info (12134): Parameter "LPM_WIDTHS" = "1"
- Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
- Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
- Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
- Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
-Info (12021): Found 1 design units, including 1 entities, in source file db/mult_j8t.tdf
- Info (12023): Found entity 1: mult_j8t File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf Line: 29
-Info (12130): Elaborated megafunction instantiation "lpm_divide:Div0" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd Line: 27
-Info (12133): Instantiated megafunction "lpm_divide:Div0" with the following parameter: File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd Line: 27
- Info (12134): Parameter "LPM_WIDTHN" = "4"
- Info (12134): Parameter "LPM_WIDTHD" = "4"
- Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
- Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
-Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_fhm.tdf
- Info (12023): Found entity 1: lpm_divide_fhm File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_fhm.tdf Line: 25
-Warning (14284): Synthesized away the following node(s):
- Warning (14285): Synthesized away the following LCELL buffer node(s):
- Warning (14320): Synthesized away node "lpm_mult:Mult0|mult_j8t:auto_generated|le5a[4]" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf Line: 43
-Info (13014): Ignored 48 buffer(s)
- Info (13016): Ignored 4 CARRY_SUM buffer(s)
- Info (13019): Ignored 44 SOFT buffer(s)
-Info (286030): Timing-Driven Synthesis is running
-Info (17016): Found the following redundant logic cells in design
- Info (17048): Logic cell "lpm_mult:Mult0|mult_j8t:auto_generated|le3a[5]" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf Line: 41
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 117 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 11 input pins
- Info (21059): Implemented 8 output pins
- Info (21061): Implemented 98 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings
- Info: Peak virtual memory: 439 megabytes
- Info: Processing ended: Thu Mar 16 16:33:18 2023
- Info: Elapsed time: 00:00:07
- Info: Total CPU time (on all processors): 00:00:16
-
-
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.map.summary b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.map.summary
deleted file mode 100644
index 33cba93..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Thu Mar 16 16:33:18 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : ALUDemo
-Top-level Entity Name : ALU4
-Family : Cyclone IV E
-Total logic elements : 98
- Total combinational functions : 98
- Dedicated logic registers : 0
-Total registers : 0
-Total pins : 19
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.pin b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.pin
deleted file mode 100644
index a33dfc8..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "ALUDemo" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-r[3] : A17 : output : 2.5 V : : 7 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-m[3] : B17 : output : 2.5 V : : 7 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-a[2] : C16 : input : 2.5 V : : 7 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-r[1] : D16 : output : 2.5 V : : 7 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-m[1] : E17 : output : 2.5 V : : 7 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7 :
-VCCIO7 : E20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
-VCCIO7 : E23 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-m[2] : F17 : output : 2.5 V : : 7 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7 :
-GND : F20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-a[1] : G15 : input : 2.5 V : : 7 : N
-op[1] : G16 : input : 2.5 V : : 7 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-b[3] : G18 : input : 2.5 V : : 7 : N
-b[0] : G19 : input : 2.5 V : : 7 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-op[0] : G22 : input : 2.5 V : : 7 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-b[2] : H16 : input : 2.5 V : : 7 : N
-a[0] : H17 : input : 2.5 V : : 7 : N
-VCCIO7 : H18 : power : : 2.5V : 7 :
-op[2] : H19 : input : 2.5 V : : 7 : N
-GNDA2 : H20 : gnd : : : :
-r[2] : H21 : output : 2.5 V : : 7 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-r[0] : J15 : output : 2.5 V : : 7 : N
-a[3] : J16 : input : 2.5 V : : 7 : N
-b[1] : J17 : input : 2.5 V : : 7 : N
-GND : J18 : gnd : : : :
-m[0] : J19 : output : 2.5 V : : 7 : N
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6 :
-MSEL2 : M22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-GND+ : Y2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sld b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sta.rpt b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sta.rpt
deleted file mode 100644
index 7df6b00..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sta.rpt
+++ /dev/null
@@ -1,500 +0,0 @@
-Timing Analyzer report for ALUDemo
-Thu Mar 16 16:33:30 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Unconstrained Input Ports
- 37. Unconstrained Output Ports
- 38. Unconstrained Input Ports
- 39. Unconstrained Output Ports
- 40. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; ALUDemo ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.3% ;
-+----------------------------+-------------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; r[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; r[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; r[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; r[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; m[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; m[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; m[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; m[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; b[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; a[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; op[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; op[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; a[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; b[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; b[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; b[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; a[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; a[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; op[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; r[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; r[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; r[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; r[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; m[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; m[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; m[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; m[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; r[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; r[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; r[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; r[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; m[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; m[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; m[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; m[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; r[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; r[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; r[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; r[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; m[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; m[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; m[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; m[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 11 ; 11 ;
-; Unconstrained Input Port Paths ; 88 ; 88 ;
-; Unconstrained Output Ports ; 8 ; 8 ;
-; Unconstrained Output Port Paths ; 88 ; 88 ;
-+---------------------------------+-------+------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; a[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; a[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; a[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; a[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; b[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; b[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; b[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; b[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; m[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; m[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; m[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; m[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; r[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; r[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; r[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; r[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; a[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; a[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; a[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; a[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; b[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; b[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; b[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; b[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; m[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; m[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; m[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; m[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; r[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; r[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; r[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; r[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Thu Mar 16 16:33:29 2023
-Info: Command: quartus_sta ALUDemo -c ALUDemo
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ALUDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 536 megabytes
- Info: Processing ended: Thu Mar 16 16:33:30 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sta.summary b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sta.summary
deleted file mode 100644
index aa5b327..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/simulation/modelsim/ALUDemo.sft b/1ano/2semestre/lsd/pratica03/ALUDemo/simulation/modelsim/ALUDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/simulation/modelsim/ALUDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/simulation/modelsim/ALUDemo.vho b/1ano/2semestre/lsd/pratica03/ALUDemo/simulation/modelsim/ALUDemo.vho
deleted file mode 100644
index 3fb35d3..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/simulation/modelsim/ALUDemo.vho
+++ /dev/null
@@ -1,2214 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/16/2023 16:33:31"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY ALU4 IS
- PORT (
- a : IN std_logic_vector(3 DOWNTO 0);
- b : IN std_logic_vector(3 DOWNTO 0);
- op : IN std_logic_vector(2 DOWNTO 0);
- r : BUFFER std_logic_vector(3 DOWNTO 0);
- m : BUFFER std_logic_vector(3 DOWNTO 0)
- );
-END ALU4;
-
--- Design Ports Information
--- r[0] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default
--- r[1] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default
--- r[2] => Location: PIN_H21, I/O Standard: 2.5 V, Current Strength: Default
--- r[3] => Location: PIN_A17, I/O Standard: 2.5 V, Current Strength: Default
--- m[0] => Location: PIN_J19, I/O Standard: 2.5 V, Current Strength: Default
--- m[1] => Location: PIN_E17, I/O Standard: 2.5 V, Current Strength: Default
--- m[2] => Location: PIN_F17, I/O Standard: 2.5 V, Current Strength: Default
--- m[3] => Location: PIN_B17, I/O Standard: 2.5 V, Current Strength: Default
--- b[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- a[0] => Location: PIN_H17, I/O Standard: 2.5 V, Current Strength: Default
--- op[1] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default
--- op[0] => Location: PIN_G22, I/O Standard: 2.5 V, Current Strength: Default
--- a[3] => Location: PIN_J16, I/O Standard: 2.5 V, Current Strength: Default
--- b[3] => Location: PIN_G18, I/O Standard: 2.5 V, Current Strength: Default
--- b[2] => Location: PIN_H16, I/O Standard: 2.5 V, Current Strength: Default
--- b[1] => Location: PIN_J17, I/O Standard: 2.5 V, Current Strength: Default
--- a[2] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default
--- a[1] => Location: PIN_G15, I/O Standard: 2.5 V, Current Strength: Default
--- op[2] => Location: PIN_H19, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF ALU4 IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_a : std_logic_vector(3 DOWNTO 0);
-SIGNAL ww_b : std_logic_vector(3 DOWNTO 0);
-SIGNAL ww_op : std_logic_vector(2 DOWNTO 0);
-SIGNAL ww_r : std_logic_vector(3 DOWNTO 0);
-SIGNAL ww_m : std_logic_vector(3 DOWNTO 0);
-SIGNAL \r[0]~output_o\ : std_logic;
-SIGNAL \r[1]~output_o\ : std_logic;
-SIGNAL \r[2]~output_o\ : std_logic;
-SIGNAL \r[3]~output_o\ : std_logic;
-SIGNAL \m[0]~output_o\ : std_logic;
-SIGNAL \m[1]~output_o\ : std_logic;
-SIGNAL \m[2]~output_o\ : std_logic;
-SIGNAL \m[3]~output_o\ : std_logic;
-SIGNAL \a[0]~input_o\ : std_logic;
-SIGNAL \b[1]~input_o\ : std_logic;
-SIGNAL \b[0]~input_o\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~0_combout\ : std_logic;
-SIGNAL \op[0]~input_o\ : std_logic;
-SIGNAL \Add0~0_combout\ : std_logic;
-SIGNAL \Add0~2_cout\ : std_logic;
-SIGNAL \Add0~3_combout\ : std_logic;
-SIGNAL \op[2]~input_o\ : std_logic;
-SIGNAL \op[1]~input_o\ : std_logic;
-SIGNAL \Mux3~4_combout\ : std_logic;
-SIGNAL \Mux3~3_combout\ : std_logic;
-SIGNAL \Mux3~5_combout\ : std_logic;
-SIGNAL \b[2]~input_o\ : std_logic;
-SIGNAL \a[2]~input_o\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|StageOut[5]~0_combout\ : std_logic;
-SIGNAL \a[3]~input_o\ : std_logic;
-SIGNAL \b[3]~input_o\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|selnose[5]~0_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\ : std_logic;
-SIGNAL \a[1]~input_o\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~4_combout\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~5\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|StageOut[10]~0_combout\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~2_combout\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|StageOut[9]~1_combout\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~0_combout\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|StageOut[8]~2_combout\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|add_sub_3_result_int[0]~1_cout\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|add_sub_3_result_int[1]~3_cout\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|add_sub_3_result_int[2]~5_cout\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|add_sub_3_result_int[3]~7_cout\ : std_logic;
-SIGNAL \Div0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~0_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~4_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~5\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|StageOut[10]~3_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~2_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|StageOut[9]~4_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~0_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|StageOut[8]~5_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~1\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~3\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~5\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~7\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\ : std_logic;
-SIGNAL \Mux3~0_combout\ : std_logic;
-SIGNAL \Mux3~1_combout\ : std_logic;
-SIGNAL \Mux3~2_combout\ : std_logic;
-SIGNAL \Mux3~6_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~1\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~2_combout\ : std_logic;
-SIGNAL \Mux2~2_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~2_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|StageOut[13]~6_combout\ : std_logic;
-SIGNAL \Mux2~3_combout\ : std_logic;
-SIGNAL \Add0~5_combout\ : std_logic;
-SIGNAL \Add0~4\ : std_logic;
-SIGNAL \Add0~6_combout\ : std_logic;
-SIGNAL \Mux2~0_combout\ : std_logic;
-SIGNAL \Mux2~1_combout\ : std_logic;
-SIGNAL \Mux1~2_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~4_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|StageOut[14]~7_combout\ : std_logic;
-SIGNAL \Mux1~3_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|selnose[5]~1_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_1~0_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~3\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~4_combout\ : std_logic;
-SIGNAL \Add0~8_combout\ : std_logic;
-SIGNAL \Add0~7\ : std_logic;
-SIGNAL \Add0~9_combout\ : std_logic;
-SIGNAL \Mux1~0_combout\ : std_logic;
-SIGNAL \Mux1~1_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_1~1\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_1~2_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|cs2a[1]~0_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~5\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~6_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~6_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|StageOut[15]~8_combout\ : std_logic;
-SIGNAL \Mux0~2_combout\ : std_logic;
-SIGNAL \Mux0~3_combout\ : std_logic;
-SIGNAL \Add0~11_combout\ : std_logic;
-SIGNAL \Add0~10\ : std_logic;
-SIGNAL \Add0~12_combout\ : std_logic;
-SIGNAL \Mux0~0_combout\ : std_logic;
-SIGNAL \Mod0|auto_generated|divider|divider|selnose[0]~2_combout\ : std_logic;
-SIGNAL \Mux0~1_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_1~3\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_1~4_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~7\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~8_combout\ : std_logic;
-SIGNAL \m~8_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_1~5\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_1~6_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~9\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~10_combout\ : std_logic;
-SIGNAL \m~9_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_1~7\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_1~8_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~11\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~12_combout\ : std_logic;
-SIGNAL \m~10_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_1~9\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_1~10_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~13\ : std_logic;
-SIGNAL \Mult0|auto_generated|op_3~14_combout\ : std_logic;
-SIGNAL \m~11_combout\ : std_logic;
-SIGNAL \Mult0|auto_generated|le5a\ : std_logic_vector(4 DOWNTO 0);
-SIGNAL \Div0|auto_generated|divider|divider|selnose\ : std_logic_vector(19 DOWNTO 0);
-SIGNAL \Mult0|auto_generated|le4a\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \Mod0|auto_generated|divider|divider|selnose\ : std_logic_vector(19 DOWNTO 0);
-SIGNAL \Mult0|auto_generated|le3a\ : std_logic_vector(5 DOWNTO 0);
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-ww_a <= a;
-ww_b <= b;
-ww_op <= op;
-r <= ww_r;
-m <= ww_m;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X60_Y73_N23
-\r[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Mux3~6_combout\,
- devoe => ww_devoe,
- o => \r[0]~output_o\);
-
--- Location: IOOBUF_X62_Y73_N23
-\r[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Mux2~1_combout\,
- devoe => ww_devoe,
- o => \r[1]~output_o\);
-
--- Location: IOOBUF_X72_Y73_N16
-\r[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Mux1~1_combout\,
- devoe => ww_devoe,
- o => \r[2]~output_o\);
-
--- Location: IOOBUF_X60_Y73_N2
-\r[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Mux0~1_combout\,
- devoe => ww_devoe,
- o => \r[3]~output_o\);
-
--- Location: IOOBUF_X72_Y73_N9
-\m[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \m~8_combout\,
- devoe => ww_devoe,
- o => \m[0]~output_o\);
-
--- Location: IOOBUF_X67_Y73_N23
-\m[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \m~9_combout\,
- devoe => ww_devoe,
- o => \m[1]~output_o\);
-
--- Location: IOOBUF_X67_Y73_N16
-\m[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \m~10_combout\,
- devoe => ww_devoe,
- o => \m[2]~output_o\);
-
--- Location: IOOBUF_X60_Y73_N9
-\m[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \m~11_combout\,
- devoe => ww_devoe,
- o => \m[3]~output_o\);
-
--- Location: IOIBUF_X67_Y73_N8
-\a[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_a(0),
- o => \a[0]~input_o\);
-
--- Location: IOIBUF_X69_Y73_N1
-\b[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_b(1),
- o => \b[1]~input_o\);
-
--- Location: IOIBUF_X69_Y73_N15
-\b[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_b(0),
- o => \b[0]~input_o\);
-
--- Location: LCCOMB_X66_Y72_N4
-\Mult0|auto_generated|le3a[0]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le3a\(0) = LCELL(\b[1]~input_o\ $ (((\a[0]~input_o\ & \b[0]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110110001101100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \a[0]~input_o\,
- datab => \b[1]~input_o\,
- datac => \b[0]~input_o\,
- combout => \Mult0|auto_generated|le3a\(0));
-
--- Location: LCCOMB_X66_Y72_N12
-\Mult0|auto_generated|op_3~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_3~0_combout\ = (\Mult0|auto_generated|le3a\(0) & (\b[1]~input_o\ $ (VCC))) # (!\Mult0|auto_generated|le3a\(0) & (\b[1]~input_o\ & VCC))
--- \Mult0|auto_generated|op_3~1\ = CARRY((\Mult0|auto_generated|le3a\(0) & \b[1]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110011010001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|le3a\(0),
- datab => \b[1]~input_o\,
- datad => VCC,
- combout => \Mult0|auto_generated|op_3~0_combout\,
- cout => \Mult0|auto_generated|op_3~1\);
-
--- Location: IOIBUF_X72_Y73_N22
-\op[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_op(0),
- o => \op[0]~input_o\);
-
--- Location: LCCOMB_X68_Y71_N0
-\Add0~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Add0~0_combout\ = \b[0]~input_o\ $ (\op[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101010110101010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \b[0]~input_o\,
- datad => \op[0]~input_o\,
- combout => \Add0~0_combout\);
-
--- Location: LCCOMB_X67_Y71_N10
-\Add0~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Add0~2_cout\ = CARRY(\op[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000010101010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \op[0]~input_o\,
- datad => VCC,
- cout => \Add0~2_cout\);
-
--- Location: LCCOMB_X67_Y71_N12
-\Add0~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \Add0~3_combout\ = (\a[0]~input_o\ & ((\Add0~0_combout\ & (\Add0~2_cout\ & VCC)) # (!\Add0~0_combout\ & (!\Add0~2_cout\)))) # (!\a[0]~input_o\ & ((\Add0~0_combout\ & (!\Add0~2_cout\)) # (!\Add0~0_combout\ & ((\Add0~2_cout\) # (GND)))))
--- \Add0~4\ = CARRY((\a[0]~input_o\ & (!\Add0~0_combout\ & !\Add0~2_cout\)) # (!\a[0]~input_o\ & ((!\Add0~2_cout\) # (!\Add0~0_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \a[0]~input_o\,
- datab => \Add0~0_combout\,
- datad => VCC,
- cin => \Add0~2_cout\,
- combout => \Add0~3_combout\,
- cout => \Add0~4\);
-
--- Location: IOIBUF_X72_Y73_N1
-\op[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_op(2),
- o => \op[2]~input_o\);
-
--- Location: IOIBUF_X67_Y73_N1
-\op[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_op(1),
- o => \op[1]~input_o\);
-
--- Location: LCCOMB_X67_Y72_N18
-\Mux3~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux3~4_combout\ = (!\op[2]~input_o\ & \op[1]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101010100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \op[2]~input_o\,
- datad => \op[1]~input_o\,
- combout => \Mux3~4_combout\);
-
--- Location: LCCOMB_X67_Y72_N8
-\Mux3~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux3~3_combout\ = (\op[2]~input_o\) # ((\op[0]~input_o\ & \op[1]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111101010101010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \op[2]~input_o\,
- datac => \op[0]~input_o\,
- datad => \op[1]~input_o\,
- combout => \Mux3~3_combout\);
-
--- Location: LCCOMB_X67_Y71_N22
-\Mux3~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux3~5_combout\ = (\Mux3~4_combout\ & ((\Mult0|auto_generated|op_3~0_combout\) # ((\Mux3~3_combout\)))) # (!\Mux3~4_combout\ & (((\Add0~3_combout\ & !\Mux3~3_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000010101100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|op_3~0_combout\,
- datab => \Add0~3_combout\,
- datac => \Mux3~4_combout\,
- datad => \Mux3~3_combout\,
- combout => \Mux3~5_combout\);
-
--- Location: IOIBUF_X65_Y73_N22
-\b[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_b(2),
- o => \b[2]~input_o\);
-
--- Location: IOIBUF_X62_Y73_N15
-\a[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_a(2),
- o => \a[2]~input_o\);
-
--- Location: LCCOMB_X66_Y71_N0
-\Mod0|auto_generated|divider|divider|StageOut[5]~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|StageOut[5]~0_combout\ = (\b[1]~input_o\ & (!\a[2]~input_o\ & \b[0]~input_o\)) # (!\b[1]~input_o\ & ((!\b[0]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101000000001111",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \a[2]~input_o\,
- datac => \b[1]~input_o\,
- datad => \b[0]~input_o\,
- combout => \Mod0|auto_generated|divider|divider|StageOut[5]~0_combout\);
-
--- Location: IOIBUF_X65_Y73_N15
-\a[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_a(3),
- o => \a[3]~input_o\);
-
--- Location: IOIBUF_X69_Y73_N22
-\b[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_b(3),
- o => \b[3]~input_o\);
-
--- Location: LCCOMB_X65_Y71_N24
-\Mod0|auto_generated|divider|divider|StageOut[5]~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\ = (\a[3]~input_o\ & ((\b[2]~input_o\) # ((\Mod0|auto_generated|divider|divider|StageOut[5]~0_combout\) # (\b[3]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000011100000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \b[2]~input_o\,
- datab => \Mod0|auto_generated|divider|divider|StageOut[5]~0_combout\,
- datac => \a[3]~input_o\,
- datad => \b[3]~input_o\,
- combout => \Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\);
-
--- Location: LCCOMB_X66_Y72_N8
-\Mod0|auto_generated|divider|divider|selnose[5]~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|selnose[5]~0_combout\ = (\b[2]~input_o\) # ((\b[3]~input_o\) # ((\b[1]~input_o\ & !\a[3]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111110101110",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \b[2]~input_o\,
- datab => \b[1]~input_o\,
- datac => \a[3]~input_o\,
- datad => \b[3]~input_o\,
- combout => \Mod0|auto_generated|divider|divider|selnose[5]~0_combout\);
-
--- Location: LCCOMB_X66_Y71_N2
-\Mod0|auto_generated|divider|divider|StageOut[4]~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\ = (\a[2]~input_o\ & ((\Mod0|auto_generated|divider|divider|selnose[5]~0_combout\) # (!\b[0]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010000010101010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \a[2]~input_o\,
- datac => \Mod0|auto_generated|divider|divider|selnose[5]~0_combout\,
- datad => \b[0]~input_o\,
- combout => \Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\);
-
--- Location: IOIBUF_X65_Y73_N8
-\a[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_a(1),
- o => \a[1]~input_o\);
-
--- Location: LCCOMB_X65_Y71_N16
-\Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~0_combout\ = (\b[0]~input_o\ & (\a[1]~input_o\ $ (VCC))) # (!\b[0]~input_o\ & ((\a[1]~input_o\) # (GND)))
--- \Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\ = CARRY((\a[1]~input_o\) # (!\b[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110011011011101",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \b[0]~input_o\,
- datab => \a[1]~input_o\,
- datad => VCC,
- combout => \Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~0_combout\,
- cout => \Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\);
-
--- Location: LCCOMB_X65_Y71_N18
-\Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~2_combout\ = (\Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\ & ((\b[1]~input_o\ & (!\Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\)) # (!\b[1]~input_o\ &
--- (\Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\ & VCC)))) # (!\Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\ & ((\b[1]~input_o\ & ((\Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\) # (GND))) # (!\b[1]~input_o\
--- & (!\Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\))))
--- \Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\ = CARRY((\Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\ & (\b[1]~input_o\ & !\Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\)) #
--- (!\Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\ & ((\b[1]~input_o\) # (!\Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100101001101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\,
- datab => \b[1]~input_o\,
- datad => VCC,
- cin => \Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\,
- combout => \Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~2_combout\,
- cout => \Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\);
-
--- Location: LCCOMB_X65_Y71_N20
-\Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~4_combout\ = ((\b[2]~input_o\ $ (\Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\ $ (\Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\)))) # (GND)
--- \Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~5\ = CARRY((\b[2]~input_o\ & (\Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\ & !\Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\)) # (!\b[2]~input_o\ &
--- ((\Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\) # (!\Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011001001101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \b[2]~input_o\,
- datab => \Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\,
- datad => VCC,
- cin => \Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\,
- combout => \Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~4_combout\,
- cout => \Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~5\);
-
--- Location: LCCOMB_X65_Y71_N22
-\Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ = !\Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~5\
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000111100001111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- cin => \Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~5\,
- combout => \Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\);
-
--- Location: LCCOMB_X65_Y71_N0
-\Div0|auto_generated|divider|divider|StageOut[10]~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Div0|auto_generated|divider|divider|StageOut[10]~0_combout\ = (\Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ & (\Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\)) #
--- (!\Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ & ((\b[3]~input_o\ & (\Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\)) # (!\b[3]~input_o\ &
--- ((\Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~4_combout\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010101010101100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\,
- datab => \Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~4_combout\,
- datac => \Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\,
- datad => \b[3]~input_o\,
- combout => \Div0|auto_generated|divider|divider|StageOut[10]~0_combout\);
-
--- Location: LCCOMB_X65_Y71_N26
-\Div0|auto_generated|divider|divider|StageOut[9]~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \Div0|auto_generated|divider|divider|StageOut[9]~1_combout\ = (\Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ & (\Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\)) #
--- (!\Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ & ((\b[3]~input_o\ & (\Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\)) # (!\b[3]~input_o\ &
--- ((\Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~2_combout\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010101010101100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\,
- datab => \Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~2_combout\,
- datac => \Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\,
- datad => \b[3]~input_o\,
- combout => \Div0|auto_generated|divider|divider|StageOut[9]~1_combout\);
-
--- Location: LCCOMB_X65_Y71_N28
-\Div0|auto_generated|divider|divider|StageOut[8]~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Div0|auto_generated|divider|divider|StageOut[8]~2_combout\ = (\Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ & (((\a[1]~input_o\)))) # (!\Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ & ((\b[3]~input_o\ &
--- ((\a[1]~input_o\))) # (!\b[3]~input_o\ & (\Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~0_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000011100100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\,
- datab => \Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~0_combout\,
- datac => \a[1]~input_o\,
- datad => \b[3]~input_o\,
- combout => \Div0|auto_generated|divider|divider|StageOut[8]~2_combout\);
-
--- Location: LCCOMB_X66_Y71_N10
-\Div0|auto_generated|divider|divider|add_sub_3_result_int[0]~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \Div0|auto_generated|divider|divider|add_sub_3_result_int[0]~1_cout\ = CARRY((\a[0]~input_o\) # (!\b[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000010111011",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \a[0]~input_o\,
- datab => \b[0]~input_o\,
- datad => VCC,
- cout => \Div0|auto_generated|divider|divider|add_sub_3_result_int[0]~1_cout\);
-
--- Location: LCCOMB_X66_Y71_N12
-\Div0|auto_generated|divider|divider|add_sub_3_result_int[1]~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \Div0|auto_generated|divider|divider|add_sub_3_result_int[1]~3_cout\ = CARRY((\b[1]~input_o\ & ((!\Div0|auto_generated|divider|divider|add_sub_3_result_int[0]~1_cout\) # (!\Div0|auto_generated|divider|divider|StageOut[8]~2_combout\))) # (!\b[1]~input_o\ &
--- (!\Div0|auto_generated|divider|divider|StageOut[8]~2_combout\ & !\Div0|auto_generated|divider|divider|add_sub_3_result_int[0]~1_cout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000101011",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \b[1]~input_o\,
- datab => \Div0|auto_generated|divider|divider|StageOut[8]~2_combout\,
- datad => VCC,
- cin => \Div0|auto_generated|divider|divider|add_sub_3_result_int[0]~1_cout\,
- cout => \Div0|auto_generated|divider|divider|add_sub_3_result_int[1]~3_cout\);
-
--- Location: LCCOMB_X66_Y71_N14
-\Div0|auto_generated|divider|divider|add_sub_3_result_int[2]~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \Div0|auto_generated|divider|divider|add_sub_3_result_int[2]~5_cout\ = CARRY((\Div0|auto_generated|divider|divider|StageOut[9]~1_combout\ & ((!\Div0|auto_generated|divider|divider|add_sub_3_result_int[1]~3_cout\) # (!\b[2]~input_o\))) #
--- (!\Div0|auto_generated|divider|divider|StageOut[9]~1_combout\ & (!\b[2]~input_o\ & !\Div0|auto_generated|divider|divider|add_sub_3_result_int[1]~3_cout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000101011",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Div0|auto_generated|divider|divider|StageOut[9]~1_combout\,
- datab => \b[2]~input_o\,
- datad => VCC,
- cin => \Div0|auto_generated|divider|divider|add_sub_3_result_int[1]~3_cout\,
- cout => \Div0|auto_generated|divider|divider|add_sub_3_result_int[2]~5_cout\);
-
--- Location: LCCOMB_X66_Y71_N16
-\Div0|auto_generated|divider|divider|add_sub_3_result_int[3]~7\ : cycloneive_lcell_comb
--- Equation(s):
--- \Div0|auto_generated|divider|divider|add_sub_3_result_int[3]~7_cout\ = CARRY((\Div0|auto_generated|divider|divider|StageOut[10]~0_combout\ & (\b[3]~input_o\ & !\Div0|auto_generated|divider|divider|add_sub_3_result_int[2]~5_cout\)) #
--- (!\Div0|auto_generated|divider|divider|StageOut[10]~0_combout\ & ((\b[3]~input_o\) # (!\Div0|auto_generated|divider|divider|add_sub_3_result_int[2]~5_cout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000001001101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Div0|auto_generated|divider|divider|StageOut[10]~0_combout\,
- datab => \b[3]~input_o\,
- datad => VCC,
- cin => \Div0|auto_generated|divider|divider|add_sub_3_result_int[2]~5_cout\,
- cout => \Div0|auto_generated|divider|divider|add_sub_3_result_int[3]~7_cout\);
-
--- Location: LCCOMB_X66_Y71_N18
-\Div0|auto_generated|divider|divider|add_sub_3_result_int[4]~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \Div0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\ = \Div0|auto_generated|divider|divider|add_sub_3_result_int[3]~7_cout\
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000011110000",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- cin => \Div0|auto_generated|divider|divider|add_sub_3_result_int[3]~7_cout\,
- combout => \Div0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\);
-
--- Location: LCCOMB_X66_Y71_N20
-\Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~0_combout\ = (\a[0]~input_o\ & ((GND) # (!\b[0]~input_o\))) # (!\a[0]~input_o\ & (\b[0]~input_o\ $ (GND)))
--- \Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~1\ = CARRY((\a[0]~input_o\) # (!\b[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110011010111011",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \a[0]~input_o\,
- datab => \b[0]~input_o\,
- datad => VCC,
- combout => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~0_combout\,
- cout => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~1\);
-
--- Location: LCCOMB_X65_Y71_N6
-\Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~0_combout\ = (\b[0]~input_o\ & (\a[1]~input_o\ $ (VCC))) # (!\b[0]~input_o\ & ((\a[1]~input_o\) # (GND)))
--- \Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\ = CARRY((\a[1]~input_o\) # (!\b[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110011011011101",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \b[0]~input_o\,
- datab => \a[1]~input_o\,
- datad => VCC,
- combout => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~0_combout\,
- cout => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\);
-
--- Location: LCCOMB_X65_Y71_N8
-\Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~2_combout\ = (\Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\ & ((\b[1]~input_o\ & (!\Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\)) # (!\b[1]~input_o\ &
--- (\Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\ & VCC)))) # (!\Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\ & ((\b[1]~input_o\ & ((\Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\) # (GND))) # (!\b[1]~input_o\
--- & (!\Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\))))
--- \Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\ = CARRY((\Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\ & (\b[1]~input_o\ & !\Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\)) #
--- (!\Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\ & ((\b[1]~input_o\) # (!\Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100101001101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\,
- datab => \b[1]~input_o\,
- datad => VCC,
- cin => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~1\,
- combout => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~2_combout\,
- cout => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\);
-
--- Location: LCCOMB_X65_Y71_N10
-\Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~4_combout\ = ((\b[2]~input_o\ $ (\Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\ $ (\Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\)))) # (GND)
--- \Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~5\ = CARRY((\b[2]~input_o\ & (\Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\ & !\Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\)) # (!\b[2]~input_o\ &
--- ((\Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\) # (!\Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011001001101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \b[2]~input_o\,
- datab => \Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\,
- datad => VCC,
- cin => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~3\,
- combout => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~4_combout\,
- cout => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~5\);
-
--- Location: LCCOMB_X65_Y71_N12
-\Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ = !\Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~5\
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000111100001111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- cin => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~5\,
- combout => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\);
-
--- Location: LCCOMB_X65_Y71_N2
-\Mod0|auto_generated|divider|divider|StageOut[10]~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|StageOut[10]~3_combout\ = (\Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ & (((\Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\)))) #
--- (!\Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ & ((\b[3]~input_o\ & ((\Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\))) # (!\b[3]~input_o\ &
--- (\Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~4_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100110011001010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~4_combout\,
- datab => \Mod0|auto_generated|divider|divider|StageOut[5]~1_combout\,
- datac => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\,
- datad => \b[3]~input_o\,
- combout => \Mod0|auto_generated|divider|divider|StageOut[10]~3_combout\);
-
--- Location: LCCOMB_X65_Y71_N4
-\Mod0|auto_generated|divider|divider|StageOut[9]~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|StageOut[9]~4_combout\ = (\Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ & (((\Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\)))) #
--- (!\Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ & ((\b[3]~input_o\ & ((\Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\))) # (!\b[3]~input_o\ &
--- (\Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~2_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111000010000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\,
- datab => \b[3]~input_o\,
- datac => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~2_combout\,
- datad => \Mod0|auto_generated|divider|divider|StageOut[4]~2_combout\,
- combout => \Mod0|auto_generated|divider|divider|StageOut[9]~4_combout\);
-
--- Location: LCCOMB_X65_Y71_N14
-\Mod0|auto_generated|divider|divider|StageOut[8]~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|StageOut[8]~5_combout\ = (\b[3]~input_o\ & (((\a[1]~input_o\)))) # (!\b[3]~input_o\ & ((\Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ & ((\a[1]~input_o\))) #
--- (!\Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\ & (\Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~0_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000011100010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~0_combout\,
- datab => \b[3]~input_o\,
- datac => \a[1]~input_o\,
- datad => \Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\,
- combout => \Mod0|auto_generated|divider|divider|StageOut[8]~5_combout\);
-
--- Location: LCCOMB_X66_Y71_N22
-\Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~2_combout\ = (\Mod0|auto_generated|divider|divider|StageOut[8]~5_combout\ & ((\b[1]~input_o\ & (!\Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~1\)) # (!\b[1]~input_o\ &
--- (\Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~1\ & VCC)))) # (!\Mod0|auto_generated|divider|divider|StageOut[8]~5_combout\ & ((\b[1]~input_o\ & ((\Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~1\) # (GND))) # (!\b[1]~input_o\
--- & (!\Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~1\))))
--- \Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~3\ = CARRY((\Mod0|auto_generated|divider|divider|StageOut[8]~5_combout\ & (\b[1]~input_o\ & !\Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~1\)) #
--- (!\Mod0|auto_generated|divider|divider|StageOut[8]~5_combout\ & ((\b[1]~input_o\) # (!\Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~1\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100101001101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|StageOut[8]~5_combout\,
- datab => \b[1]~input_o\,
- datad => VCC,
- cin => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~1\,
- combout => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~2_combout\,
- cout => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~3\);
-
--- Location: LCCOMB_X66_Y71_N24
-\Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~4_combout\ = ((\Mod0|auto_generated|divider|divider|StageOut[9]~4_combout\ $ (\b[2]~input_o\ $ (\Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~3\)))) # (GND)
--- \Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~5\ = CARRY((\Mod0|auto_generated|divider|divider|StageOut[9]~4_combout\ & ((!\Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~3\) # (!\b[2]~input_o\))) #
--- (!\Mod0|auto_generated|divider|divider|StageOut[9]~4_combout\ & (!\b[2]~input_o\ & !\Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~3\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000101011",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|StageOut[9]~4_combout\,
- datab => \b[2]~input_o\,
- datad => VCC,
- cin => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~3\,
- combout => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~4_combout\,
- cout => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~5\);
-
--- Location: LCCOMB_X66_Y71_N26
-\Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~6_combout\ = (\Mod0|auto_generated|divider|divider|StageOut[10]~3_combout\ & ((\b[3]~input_o\ & (!\Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~5\)) # (!\b[3]~input_o\ &
--- (\Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~5\ & VCC)))) # (!\Mod0|auto_generated|divider|divider|StageOut[10]~3_combout\ & ((\b[3]~input_o\ & ((\Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~5\) # (GND))) #
--- (!\b[3]~input_o\ & (!\Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~5\))))
--- \Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~7\ = CARRY((\Mod0|auto_generated|divider|divider|StageOut[10]~3_combout\ & (\b[3]~input_o\ & !\Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~5\)) #
--- (!\Mod0|auto_generated|divider|divider|StageOut[10]~3_combout\ & ((\b[3]~input_o\) # (!\Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~5\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100101001101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|StageOut[10]~3_combout\,
- datab => \b[3]~input_o\,
- datad => VCC,
- cin => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~5\,
- combout => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~6_combout\,
- cout => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~7\);
-
--- Location: LCCOMB_X66_Y71_N28
-\Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\ = \Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~7\
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000011110000",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- cin => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~7\,
- combout => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\);
-
--- Location: LCCOMB_X67_Y71_N24
-\Mux3~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux3~0_combout\ = (\op[0]~input_o\ & (((\a[0]~input_o\)))) # (!\op[0]~input_o\ & ((\Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\ & ((\a[0]~input_o\))) # (!\Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\ &
--- (\Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~0_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111000000100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \op[0]~input_o\,
- datab => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~0_combout\,
- datac => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\,
- datad => \a[0]~input_o\,
- combout => \Mux3~0_combout\);
-
--- Location: LCCOMB_X67_Y71_N26
-\Mux3~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux3~1_combout\ = (\op[1]~input_o\ & (\op[0]~input_o\)) # (!\op[1]~input_o\ & (\Mux3~0_combout\ & ((\b[0]~input_o\) # (!\op[0]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010110010100100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \op[0]~input_o\,
- datab => \Mux3~0_combout\,
- datac => \op[1]~input_o\,
- datad => \b[0]~input_o\,
- combout => \Mux3~1_combout\);
-
--- Location: LCCOMB_X67_Y71_N4
-\Mux3~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux3~2_combout\ = (\op[1]~input_o\ & ((\a[0]~input_o\ & ((!\b[0]~input_o\) # (!\Mux3~1_combout\))) # (!\a[0]~input_o\ & ((\b[0]~input_o\))))) # (!\op[1]~input_o\ & (\Mux3~1_combout\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0111101011001010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mux3~1_combout\,
- datab => \a[0]~input_o\,
- datac => \op[1]~input_o\,
- datad => \b[0]~input_o\,
- combout => \Mux3~2_combout\);
-
--- Location: LCCOMB_X67_Y71_N8
-\Mux3~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux3~6_combout\ = (\Mux3~5_combout\ & (((!\Mux3~3_combout\)) # (!\Div0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\))) # (!\Mux3~5_combout\ & (((\Mux3~2_combout\ & \Mux3~3_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0111001010101010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mux3~5_combout\,
- datab => \Div0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\,
- datac => \Mux3~2_combout\,
- datad => \Mux3~3_combout\,
- combout => \Mux3~6_combout\);
-
--- Location: LCCOMB_X66_Y72_N30
-\Mult0|auto_generated|le3a[1]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le3a\(1) = LCELL((\b[0]~input_o\ & ((\b[1]~input_o\ $ (\a[1]~input_o\)))) # (!\b[0]~input_o\ & (!\a[0]~input_o\ & (\b[1]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011010011000100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \a[0]~input_o\,
- datab => \b[1]~input_o\,
- datac => \b[0]~input_o\,
- datad => \a[1]~input_o\,
- combout => \Mult0|auto_generated|le3a\(1));
-
--- Location: LCCOMB_X66_Y72_N14
-\Mult0|auto_generated|op_3~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_3~2_combout\ = (\Mult0|auto_generated|le3a\(1) & (!\Mult0|auto_generated|op_3~1\)) # (!\Mult0|auto_generated|le3a\(1) & ((\Mult0|auto_generated|op_3~1\) # (GND)))
--- \Mult0|auto_generated|op_3~3\ = CARRY((!\Mult0|auto_generated|op_3~1\) # (!\Mult0|auto_generated|le3a\(1)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|le3a\(1),
- datad => VCC,
- cin => \Mult0|auto_generated|op_3~1\,
- combout => \Mult0|auto_generated|op_3~2_combout\,
- cout => \Mult0|auto_generated|op_3~3\);
-
--- Location: LCCOMB_X67_Y72_N10
-\Mux2~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux2~2_combout\ = (\b[1]~input_o\ & ((\a[1]~input_o\ $ (\op[1]~input_o\)) # (!\op[0]~input_o\))) # (!\b[1]~input_o\ & ((\op[1]~input_o\ & (\a[1]~input_o\)) # (!\op[1]~input_o\ & ((!\op[0]~input_o\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110111010001111",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \b[1]~input_o\,
- datab => \a[1]~input_o\,
- datac => \op[0]~input_o\,
- datad => \op[1]~input_o\,
- combout => \Mux2~2_combout\);
-
--- Location: LCCOMB_X66_Y71_N4
-\Mod0|auto_generated|divider|divider|StageOut[13]~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|StageOut[13]~6_combout\ = (\Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\ & (\Mod0|auto_generated|divider|divider|StageOut[8]~5_combout\)) #
--- (!\Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\ & ((\Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~2_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010101011110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|StageOut[8]~5_combout\,
- datac => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~2_combout\,
- datad => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\,
- combout => \Mod0|auto_generated|divider|divider|StageOut[13]~6_combout\);
-
--- Location: LCCOMB_X67_Y72_N12
-\Mux2~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux2~3_combout\ = (\Mux2~2_combout\ & ((\Mod0|auto_generated|divider|divider|StageOut[13]~6_combout\) # ((\op[0]~input_o\) # (\op[1]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010101010101000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mux2~2_combout\,
- datab => \Mod0|auto_generated|divider|divider|StageOut[13]~6_combout\,
- datac => \op[0]~input_o\,
- datad => \op[1]~input_o\,
- combout => \Mux2~3_combout\);
-
--- Location: LCCOMB_X68_Y71_N2
-\Add0~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \Add0~5_combout\ = \op[0]~input_o\ $ (\b[1]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011001111001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \op[0]~input_o\,
- datad => \b[1]~input_o\,
- combout => \Add0~5_combout\);
-
--- Location: LCCOMB_X67_Y71_N14
-\Add0~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \Add0~6_combout\ = ((\Add0~5_combout\ $ (\a[1]~input_o\ $ (!\Add0~4\)))) # (GND)
--- \Add0~7\ = CARRY((\Add0~5_combout\ & ((\a[1]~input_o\) # (!\Add0~4\))) # (!\Add0~5_combout\ & (\a[1]~input_o\ & !\Add0~4\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Add0~5_combout\,
- datab => \a[1]~input_o\,
- datad => VCC,
- cin => \Add0~4\,
- combout => \Add0~6_combout\,
- cout => \Add0~7\);
-
--- Location: LCCOMB_X67_Y72_N20
-\Mux2~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux2~0_combout\ = (\Mux3~4_combout\ & (((\Mux3~3_combout\)))) # (!\Mux3~4_combout\ & ((\Mux3~3_combout\ & (\Mux2~3_combout\)) # (!\Mux3~3_combout\ & ((\Add0~6_combout\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1110111000110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mux2~3_combout\,
- datab => \Mux3~4_combout\,
- datac => \Add0~6_combout\,
- datad => \Mux3~3_combout\,
- combout => \Mux2~0_combout\);
-
--- Location: LCCOMB_X65_Y71_N30
-\Div0|auto_generated|divider|divider|selnose[10]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Div0|auto_generated|divider|divider|selnose\(10) = (\Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\) # (\b[3]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6_combout\,
- datad => \b[3]~input_o\,
- combout => \Div0|auto_generated|divider|divider|selnose\(10));
-
--- Location: LCCOMB_X67_Y72_N14
-\Mux2~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux2~1_combout\ = (\Mux2~0_combout\ & (((!\Mux3~4_combout\) # (!\Div0|auto_generated|divider|divider|selnose\(10))))) # (!\Mux2~0_combout\ & (\Mult0|auto_generated|op_3~2_combout\ & ((\Mux3~4_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0010111011001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|op_3~2_combout\,
- datab => \Mux2~0_combout\,
- datac => \Div0|auto_generated|divider|divider|selnose\(10),
- datad => \Mux3~4_combout\,
- combout => \Mux2~1_combout\);
-
--- Location: LCCOMB_X67_Y71_N20
-\Mux1~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux1~2_combout\ = (\b[2]~input_o\ & ((\op[1]~input_o\ $ (\a[2]~input_o\)) # (!\op[0]~input_o\))) # (!\b[2]~input_o\ & ((\op[1]~input_o\ & ((\a[2]~input_o\))) # (!\op[1]~input_o\ & (!\op[0]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0111110111000101",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \op[0]~input_o\,
- datab => \b[2]~input_o\,
- datac => \op[1]~input_o\,
- datad => \a[2]~input_o\,
- combout => \Mux1~2_combout\);
-
--- Location: LCCOMB_X66_Y71_N6
-\Mod0|auto_generated|divider|divider|StageOut[14]~7\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|StageOut[14]~7_combout\ = (\Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\ & ((\Mod0|auto_generated|divider|divider|StageOut[9]~4_combout\))) #
--- (!\Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\ & (\Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~4_combout\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000011001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~4_combout\,
- datac => \Mod0|auto_generated|divider|divider|StageOut[9]~4_combout\,
- datad => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\,
- combout => \Mod0|auto_generated|divider|divider|StageOut[14]~7_combout\);
-
--- Location: LCCOMB_X67_Y71_N6
-\Mux1~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux1~3_combout\ = (\Mux1~2_combout\ & ((\op[1]~input_o\) # ((\op[0]~input_o\) # (\Mod0|auto_generated|divider|divider|StageOut[14]~7_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100110011001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \op[1]~input_o\,
- datab => \Mux1~2_combout\,
- datac => \op[0]~input_o\,
- datad => \Mod0|auto_generated|divider|divider|StageOut[14]~7_combout\,
- combout => \Mux1~3_combout\);
-
--- Location: LCCOMB_X67_Y71_N0
-\Mod0|auto_generated|divider|divider|selnose[5]~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|selnose[5]~1_combout\ = (\Mod0|auto_generated|divider|divider|selnose[5]~0_combout\) # ((!\a[2]~input_o\ & \b[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010111110101010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|selnose[5]~0_combout\,
- datac => \a[2]~input_o\,
- datad => \b[0]~input_o\,
- combout => \Mod0|auto_generated|divider|divider|selnose[5]~1_combout\);
-
--- Location: LCCOMB_X66_Y72_N10
-\Mult0|auto_generated|le4a[0]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le4a\(0) = LCELL(\b[3]~input_o\ $ (((\b[2]~input_o\ & ((\b[1]~input_o\) # (\a[0]~input_o\))) # (!\b[2]~input_o\ & (\b[1]~input_o\ & \a[0]~input_o\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0001011111101000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \b[2]~input_o\,
- datab => \b[1]~input_o\,
- datac => \a[0]~input_o\,
- datad => \b[3]~input_o\,
- combout => \Mult0|auto_generated|le4a\(0));
-
--- Location: LCCOMB_X66_Y72_N0
-\Mult0|auto_generated|le3a[2]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le3a\(2) = LCELL((\b[0]~input_o\ & ((\a[2]~input_o\ $ (\b[1]~input_o\)))) # (!\b[0]~input_o\ & (!\a[1]~input_o\ & ((\b[1]~input_o\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011010111000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \a[1]~input_o\,
- datab => \a[2]~input_o\,
- datac => \b[0]~input_o\,
- datad => \b[1]~input_o\,
- combout => \Mult0|auto_generated|le3a\(2));
-
--- Location: LCCOMB_X65_Y72_N0
-\Mult0|auto_generated|le4a[5]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le4a\(5) = LCELL(\b[3]~input_o\ $ (((\b[2]~input_o\ & \b[1]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101111110100000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \b[2]~input_o\,
- datac => \b[1]~input_o\,
- datad => \b[3]~input_o\,
- combout => \Mult0|auto_generated|le4a\(5));
-
--- Location: LCCOMB_X65_Y72_N10
-\Mult0|auto_generated|op_1~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_1~0_combout\ = (\Mult0|auto_generated|le3a\(2) & (\Mult0|auto_generated|le4a\(5) $ (VCC))) # (!\Mult0|auto_generated|le3a\(2) & (\Mult0|auto_generated|le4a\(5) & VCC))
--- \Mult0|auto_generated|op_1~1\ = CARRY((\Mult0|auto_generated|le3a\(2) & \Mult0|auto_generated|le4a\(5)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110011010001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|le3a\(2),
- datab => \Mult0|auto_generated|le4a\(5),
- datad => VCC,
- combout => \Mult0|auto_generated|op_1~0_combout\,
- cout => \Mult0|auto_generated|op_1~1\);
-
--- Location: LCCOMB_X66_Y72_N16
-\Mult0|auto_generated|op_3~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_3~4_combout\ = ((\Mult0|auto_generated|le4a\(0) $ (\Mult0|auto_generated|op_1~0_combout\ $ (!\Mult0|auto_generated|op_3~3\)))) # (GND)
--- \Mult0|auto_generated|op_3~5\ = CARRY((\Mult0|auto_generated|le4a\(0) & ((\Mult0|auto_generated|op_1~0_combout\) # (!\Mult0|auto_generated|op_3~3\))) # (!\Mult0|auto_generated|le4a\(0) & (\Mult0|auto_generated|op_1~0_combout\ &
--- !\Mult0|auto_generated|op_3~3\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|le4a\(0),
- datab => \Mult0|auto_generated|op_1~0_combout\,
- datad => VCC,
- cin => \Mult0|auto_generated|op_3~3\,
- combout => \Mult0|auto_generated|op_3~4_combout\,
- cout => \Mult0|auto_generated|op_3~5\);
-
--- Location: LCCOMB_X67_Y71_N28
-\Add0~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \Add0~8_combout\ = \op[0]~input_o\ $ (\b[2]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \op[0]~input_o\,
- datac => \b[2]~input_o\,
- combout => \Add0~8_combout\);
-
--- Location: LCCOMB_X67_Y71_N16
-\Add0~9\ : cycloneive_lcell_comb
--- Equation(s):
--- \Add0~9_combout\ = (\a[2]~input_o\ & ((\Add0~8_combout\ & (\Add0~7\ & VCC)) # (!\Add0~8_combout\ & (!\Add0~7\)))) # (!\a[2]~input_o\ & ((\Add0~8_combout\ & (!\Add0~7\)) # (!\Add0~8_combout\ & ((\Add0~7\) # (GND)))))
--- \Add0~10\ = CARRY((\a[2]~input_o\ & (!\Add0~8_combout\ & !\Add0~7\)) # (!\a[2]~input_o\ & ((!\Add0~7\) # (!\Add0~8_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \a[2]~input_o\,
- datab => \Add0~8_combout\,
- datad => VCC,
- cin => \Add0~7\,
- combout => \Add0~9_combout\,
- cout => \Add0~10\);
-
--- Location: LCCOMB_X67_Y71_N30
-\Mux1~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux1~0_combout\ = (\Mux3~4_combout\ & ((\Mult0|auto_generated|op_3~4_combout\) # ((\Mux3~3_combout\)))) # (!\Mux3~4_combout\ & (((\Add0~9_combout\ & !\Mux3~3_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000010101100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|op_3~4_combout\,
- datab => \Add0~9_combout\,
- datac => \Mux3~4_combout\,
- datad => \Mux3~3_combout\,
- combout => \Mux1~0_combout\);
-
--- Location: LCCOMB_X67_Y71_N2
-\Mux1~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux1~1_combout\ = (\Mux1~0_combout\ & (((!\Mux3~3_combout\) # (!\Mod0|auto_generated|divider|divider|selnose[5]~1_combout\)))) # (!\Mux1~0_combout\ & (\Mux1~3_combout\ & ((\Mux3~3_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011101011110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mux1~3_combout\,
- datab => \Mod0|auto_generated|divider|divider|selnose[5]~1_combout\,
- datac => \Mux1~0_combout\,
- datad => \Mux3~3_combout\,
- combout => \Mux1~1_combout\);
-
--- Location: LCCOMB_X65_Y72_N26
-\Mult0|auto_generated|le3a[3]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le3a\(3) = LCELL((\b[0]~input_o\ & ((\a[3]~input_o\ $ (\b[1]~input_o\)))) # (!\b[0]~input_o\ & (!\a[2]~input_o\ & ((\b[1]~input_o\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110001010000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \a[2]~input_o\,
- datab => \a[3]~input_o\,
- datac => \b[1]~input_o\,
- datad => \b[0]~input_o\,
- combout => \Mult0|auto_generated|le3a\(3));
-
--- Location: LCCOMB_X65_Y72_N12
-\Mult0|auto_generated|op_1~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_1~2_combout\ = (\Mult0|auto_generated|le3a\(3) & (!\Mult0|auto_generated|op_1~1\)) # (!\Mult0|auto_generated|le3a\(3) & ((\Mult0|auto_generated|op_1~1\) # (GND)))
--- \Mult0|auto_generated|op_1~3\ = CARRY((!\Mult0|auto_generated|op_1~1\) # (!\Mult0|auto_generated|le3a\(3)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|le3a\(3),
- datad => VCC,
- cin => \Mult0|auto_generated|op_1~1\,
- combout => \Mult0|auto_generated|op_1~2_combout\,
- cout => \Mult0|auto_generated|op_1~3\);
-
--- Location: LCCOMB_X65_Y72_N4
-\Mult0|auto_generated|cs2a[1]~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|cs2a[1]~0_combout\ = \b[1]~input_o\ $ (\b[2]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \b[1]~input_o\,
- datad => \b[2]~input_o\,
- combout => \Mult0|auto_generated|cs2a[1]~0_combout\);
-
--- Location: LCCOMB_X66_Y72_N28
-\Mult0|auto_generated|le4a[1]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le4a\(1) = LCELL((\Mult0|auto_generated|cs2a[1]~0_combout\ & ((\a[1]~input_o\ $ (\Mult0|auto_generated|le4a\(5))))) # (!\Mult0|auto_generated|cs2a[1]~0_combout\ & (!\a[0]~input_o\ & ((\Mult0|auto_generated|le4a\(5))))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0001110111000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \a[0]~input_o\,
- datab => \Mult0|auto_generated|cs2a[1]~0_combout\,
- datac => \a[1]~input_o\,
- datad => \Mult0|auto_generated|le4a\(5),
- combout => \Mult0|auto_generated|le4a\(1));
-
--- Location: LCCOMB_X66_Y72_N18
-\Mult0|auto_generated|op_3~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_3~6_combout\ = (\Mult0|auto_generated|op_1~2_combout\ & ((\Mult0|auto_generated|le4a\(1) & (\Mult0|auto_generated|op_3~5\ & VCC)) # (!\Mult0|auto_generated|le4a\(1) & (!\Mult0|auto_generated|op_3~5\)))) #
--- (!\Mult0|auto_generated|op_1~2_combout\ & ((\Mult0|auto_generated|le4a\(1) & (!\Mult0|auto_generated|op_3~5\)) # (!\Mult0|auto_generated|le4a\(1) & ((\Mult0|auto_generated|op_3~5\) # (GND)))))
--- \Mult0|auto_generated|op_3~7\ = CARRY((\Mult0|auto_generated|op_1~2_combout\ & (!\Mult0|auto_generated|le4a\(1) & !\Mult0|auto_generated|op_3~5\)) # (!\Mult0|auto_generated|op_1~2_combout\ & ((!\Mult0|auto_generated|op_3~5\) #
--- (!\Mult0|auto_generated|le4a\(1)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|op_1~2_combout\,
- datab => \Mult0|auto_generated|le4a\(1),
- datad => VCC,
- cin => \Mult0|auto_generated|op_3~5\,
- combout => \Mult0|auto_generated|op_3~6_combout\,
- cout => \Mult0|auto_generated|op_3~7\);
-
--- Location: LCCOMB_X66_Y71_N8
-\Mod0|auto_generated|divider|divider|StageOut[15]~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|StageOut[15]~8_combout\ = (\Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\ & (\Mod0|auto_generated|divider|divider|StageOut[10]~3_combout\)) #
--- (!\Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\ & ((\Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~6_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010101011110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|StageOut[10]~3_combout\,
- datac => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~6_combout\,
- datad => \Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8_combout\,
- combout => \Mod0|auto_generated|divider|divider|StageOut[15]~8_combout\);
-
--- Location: LCCOMB_X67_Y72_N30
-\Mux0~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux0~2_combout\ = (\a[3]~input_o\ & ((\b[3]~input_o\ $ (\op[1]~input_o\)) # (!\op[0]~input_o\))) # (!\a[3]~input_o\ & ((\op[1]~input_o\ & ((\b[3]~input_o\))) # (!\op[1]~input_o\ & (!\op[0]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0111101010110011",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \a[3]~input_o\,
- datab => \op[0]~input_o\,
- datac => \b[3]~input_o\,
- datad => \op[1]~input_o\,
- combout => \Mux0~2_combout\);
-
--- Location: LCCOMB_X67_Y72_N24
-\Mux0~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux0~3_combout\ = (\Mux0~2_combout\ & ((\Mod0|auto_generated|divider|divider|StageOut[15]~8_combout\) # ((\op[0]~input_o\) # (\op[1]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000011100000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|StageOut[15]~8_combout\,
- datab => \op[0]~input_o\,
- datac => \Mux0~2_combout\,
- datad => \op[1]~input_o\,
- combout => \Mux0~3_combout\);
-
--- Location: LCCOMB_X68_Y71_N4
-\Add0~11\ : cycloneive_lcell_comb
--- Equation(s):
--- \Add0~11_combout\ = \op[0]~input_o\ $ (\b[3]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011001111001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \op[0]~input_o\,
- datad => \b[3]~input_o\,
- combout => \Add0~11_combout\);
-
--- Location: LCCOMB_X67_Y71_N18
-\Add0~12\ : cycloneive_lcell_comb
--- Equation(s):
--- \Add0~12_combout\ = \a[3]~input_o\ $ (\Add0~10\ $ (!\Add0~11_combout\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110011000011",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \a[3]~input_o\,
- datad => \Add0~11_combout\,
- cin => \Add0~10\,
- combout => \Add0~12_combout\);
-
--- Location: LCCOMB_X67_Y72_N16
-\Mux0~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux0~0_combout\ = (\Mux3~3_combout\ & ((\Mux0~3_combout\) # ((\Mux3~4_combout\)))) # (!\Mux3~3_combout\ & (((\Add0~12_combout\ & !\Mux3~4_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010101011011000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mux3~3_combout\,
- datab => \Mux0~3_combout\,
- datac => \Add0~12_combout\,
- datad => \Mux3~4_combout\,
- combout => \Mux0~0_combout\);
-
--- Location: LCCOMB_X66_Y72_N2
-\Mod0|auto_generated|divider|divider|selnose[0]~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|selnose[0]~2_combout\ = (!\b[2]~input_o\ & !\b[3]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000001010101",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \b[2]~input_o\,
- datad => \b[3]~input_o\,
- combout => \Mod0|auto_generated|divider|divider|selnose[0]~2_combout\);
-
--- Location: LCCOMB_X67_Y72_N26
-\Mod0|auto_generated|divider|divider|selnose[0]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mod0|auto_generated|divider|divider|selnose\(0) = ((\b[1]~input_o\) # ((!\a[3]~input_o\ & \b[0]~input_o\))) # (!\Mod0|auto_generated|divider|divider|selnose[0]~2_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111101110101",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mod0|auto_generated|divider|divider|selnose[0]~2_combout\,
- datab => \a[3]~input_o\,
- datac => \b[0]~input_o\,
- datad => \b[1]~input_o\,
- combout => \Mod0|auto_generated|divider|divider|selnose\(0));
-
--- Location: LCCOMB_X67_Y72_N4
-\Mux0~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mux0~1_combout\ = (\Mux0~0_combout\ & (((!\Mux3~4_combout\) # (!\Mod0|auto_generated|divider|divider|selnose\(0))))) # (!\Mux0~0_combout\ & (\Mult0|auto_generated|op_3~6_combout\ & ((\Mux3~4_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0010111011001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|op_3~6_combout\,
- datab => \Mux0~0_combout\,
- datac => \Mod0|auto_generated|divider|divider|selnose\(0),
- datad => \Mux3~4_combout\,
- combout => \Mux0~1_combout\);
-
--- Location: LCCOMB_X65_Y72_N30
-\Mult0|auto_generated|le3a[4]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le3a\(4) = LCELL((\b[1]~input_o\ & ((\b[0]~input_o\) # (!\a[3]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000000110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \a[3]~input_o\,
- datac => \b[1]~input_o\,
- datad => \b[0]~input_o\,
- combout => \Mult0|auto_generated|le3a\(4));
-
--- Location: LCCOMB_X65_Y72_N24
-\Mult0|auto_generated|le4a[2]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le4a\(2) = LCELL((\Mult0|auto_generated|cs2a[1]~0_combout\ & (\Mult0|auto_generated|le4a\(5) $ ((\a[2]~input_o\)))) # (!\Mult0|auto_generated|cs2a[1]~0_combout\ & (\Mult0|auto_generated|le4a\(5) & ((!\a[1]~input_o\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0010100001101100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|cs2a[1]~0_combout\,
- datab => \Mult0|auto_generated|le4a\(5),
- datac => \a[2]~input_o\,
- datad => \a[1]~input_o\,
- combout => \Mult0|auto_generated|le4a\(2));
-
--- Location: LCCOMB_X65_Y72_N14
-\Mult0|auto_generated|op_1~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_1~4_combout\ = ((\Mult0|auto_generated|le3a\(4) $ (\Mult0|auto_generated|le4a\(2) $ (!\Mult0|auto_generated|op_1~3\)))) # (GND)
--- \Mult0|auto_generated|op_1~5\ = CARRY((\Mult0|auto_generated|le3a\(4) & ((\Mult0|auto_generated|le4a\(2)) # (!\Mult0|auto_generated|op_1~3\))) # (!\Mult0|auto_generated|le3a\(4) & (\Mult0|auto_generated|le4a\(2) & !\Mult0|auto_generated|op_1~3\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|le3a\(4),
- datab => \Mult0|auto_generated|le4a\(2),
- datad => VCC,
- cin => \Mult0|auto_generated|op_1~3\,
- combout => \Mult0|auto_generated|op_1~4_combout\,
- cout => \Mult0|auto_generated|op_1~5\);
-
--- Location: LCCOMB_X65_Y72_N6
-\Mult0|auto_generated|le5a[0]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le5a\(0) = LCELL((\a[0]~input_o\ & ((\b[3]~input_o\) # ((\b[2]~input_o\ & \b[1]~input_o\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100110010000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \b[2]~input_o\,
- datab => \a[0]~input_o\,
- datac => \b[1]~input_o\,
- datad => \b[3]~input_o\,
- combout => \Mult0|auto_generated|le5a\(0));
-
--- Location: LCCOMB_X66_Y72_N20
-\Mult0|auto_generated|op_3~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_3~8_combout\ = ((\Mult0|auto_generated|op_1~4_combout\ $ (\Mult0|auto_generated|le5a\(0) $ (!\Mult0|auto_generated|op_3~7\)))) # (GND)
--- \Mult0|auto_generated|op_3~9\ = CARRY((\Mult0|auto_generated|op_1~4_combout\ & ((\Mult0|auto_generated|le5a\(0)) # (!\Mult0|auto_generated|op_3~7\))) # (!\Mult0|auto_generated|op_1~4_combout\ & (\Mult0|auto_generated|le5a\(0) &
--- !\Mult0|auto_generated|op_3~7\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|op_1~4_combout\,
- datab => \Mult0|auto_generated|le5a\(0),
- datad => VCC,
- cin => \Mult0|auto_generated|op_3~7\,
- combout => \Mult0|auto_generated|op_3~8_combout\,
- cout => \Mult0|auto_generated|op_3~9\);
-
--- Location: LCCOMB_X67_Y72_N6
-\m~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \m~8_combout\ = (!\op[2]~input_o\ & (\Mult0|auto_generated|op_3~8_combout\ & (!\op[0]~input_o\ & \op[1]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000010000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \op[2]~input_o\,
- datab => \Mult0|auto_generated|op_3~8_combout\,
- datac => \op[0]~input_o\,
- datad => \op[1]~input_o\,
- combout => \m~8_combout\);
-
--- Location: LCCOMB_X66_Y72_N6
-\Mult0|auto_generated|le5a[1]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le5a\(1) = LCELL((\a[1]~input_o\ & ((\b[3]~input_o\) # ((\b[2]~input_o\ & \b[1]~input_o\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000010000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \b[2]~input_o\,
- datab => \b[1]~input_o\,
- datac => \a[1]~input_o\,
- datad => \b[3]~input_o\,
- combout => \Mult0|auto_generated|le5a\(1));
-
--- Location: LCCOMB_X65_Y72_N8
-\Mult0|auto_generated|le4a[3]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le4a\(3) = LCELL((\Mult0|auto_generated|cs2a[1]~0_combout\ & (\Mult0|auto_generated|le4a\(5) $ (((\a[3]~input_o\))))) # (!\Mult0|auto_generated|cs2a[1]~0_combout\ & (\Mult0|auto_generated|le4a\(5) & (!\a[2]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0010011010001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|cs2a[1]~0_combout\,
- datab => \Mult0|auto_generated|le4a\(5),
- datac => \a[2]~input_o\,
- datad => \a[3]~input_o\,
- combout => \Mult0|auto_generated|le4a\(3));
-
--- Location: LCCOMB_X65_Y72_N16
-\Mult0|auto_generated|op_1~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_1~6_combout\ = (\Mult0|auto_generated|le5a\(1) & ((\Mult0|auto_generated|le4a\(3) & (\Mult0|auto_generated|op_1~5\ & VCC)) # (!\Mult0|auto_generated|le4a\(3) & (!\Mult0|auto_generated|op_1~5\)))) # (!\Mult0|auto_generated|le5a\(1)
--- & ((\Mult0|auto_generated|le4a\(3) & (!\Mult0|auto_generated|op_1~5\)) # (!\Mult0|auto_generated|le4a\(3) & ((\Mult0|auto_generated|op_1~5\) # (GND)))))
--- \Mult0|auto_generated|op_1~7\ = CARRY((\Mult0|auto_generated|le5a\(1) & (!\Mult0|auto_generated|le4a\(3) & !\Mult0|auto_generated|op_1~5\)) # (!\Mult0|auto_generated|le5a\(1) & ((!\Mult0|auto_generated|op_1~5\) # (!\Mult0|auto_generated|le4a\(3)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|le5a\(1),
- datab => \Mult0|auto_generated|le4a\(3),
- datad => VCC,
- cin => \Mult0|auto_generated|op_1~5\,
- combout => \Mult0|auto_generated|op_1~6_combout\,
- cout => \Mult0|auto_generated|op_1~7\);
-
--- Location: LCCOMB_X67_Y72_N22
-\Mult0|auto_generated|le3a[5]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le3a\(5) = LCELL(\b[1]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datad => \b[1]~input_o\,
- combout => \Mult0|auto_generated|le3a\(5));
-
--- Location: LCCOMB_X66_Y72_N22
-\Mult0|auto_generated|op_3~10\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_3~10_combout\ = (\Mult0|auto_generated|op_1~6_combout\ & ((\Mult0|auto_generated|le3a\(5) & (\Mult0|auto_generated|op_3~9\ & VCC)) # (!\Mult0|auto_generated|le3a\(5) & (!\Mult0|auto_generated|op_3~9\)))) #
--- (!\Mult0|auto_generated|op_1~6_combout\ & ((\Mult0|auto_generated|le3a\(5) & (!\Mult0|auto_generated|op_3~9\)) # (!\Mult0|auto_generated|le3a\(5) & ((\Mult0|auto_generated|op_3~9\) # (GND)))))
--- \Mult0|auto_generated|op_3~11\ = CARRY((\Mult0|auto_generated|op_1~6_combout\ & (!\Mult0|auto_generated|le3a\(5) & !\Mult0|auto_generated|op_3~9\)) # (!\Mult0|auto_generated|op_1~6_combout\ & ((!\Mult0|auto_generated|op_3~9\) #
--- (!\Mult0|auto_generated|le3a\(5)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|op_1~6_combout\,
- datab => \Mult0|auto_generated|le3a\(5),
- datad => VCC,
- cin => \Mult0|auto_generated|op_3~9\,
- combout => \Mult0|auto_generated|op_3~10_combout\,
- cout => \Mult0|auto_generated|op_3~11\);
-
--- Location: LCCOMB_X67_Y72_N0
-\m~9\ : cycloneive_lcell_comb
--- Equation(s):
--- \m~9_combout\ = (!\op[2]~input_o\ & (\Mult0|auto_generated|op_3~10_combout\ & (!\op[0]~input_o\ & \op[1]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000010000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \op[2]~input_o\,
- datab => \Mult0|auto_generated|op_3~10_combout\,
- datac => \op[0]~input_o\,
- datad => \op[1]~input_o\,
- combout => \m~9_combout\);
-
--- Location: LCCOMB_X65_Y72_N2
-\Mult0|auto_generated|le4a[4]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le4a\(4) = LCELL((\a[3]~input_o\ & (\b[3]~input_o\ & (\b[2]~input_o\ $ (\b[1]~input_o\)))) # (!\a[3]~input_o\ & (\b[3]~input_o\ $ (((\b[2]~input_o\ & \b[1]~input_o\))))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101100100000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \b[2]~input_o\,
- datab => \a[3]~input_o\,
- datac => \b[1]~input_o\,
- datad => \b[3]~input_o\,
- combout => \Mult0|auto_generated|le4a\(4));
-
--- Location: LCCOMB_X65_Y72_N28
-\Mult0|auto_generated|le5a[2]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le5a\(2) = LCELL((\a[2]~input_o\ & ((\b[3]~input_o\) # ((\b[1]~input_o\ & \b[2]~input_o\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010100010100000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \a[2]~input_o\,
- datab => \b[1]~input_o\,
- datac => \b[3]~input_o\,
- datad => \b[2]~input_o\,
- combout => \Mult0|auto_generated|le5a\(2));
-
--- Location: LCCOMB_X65_Y72_N18
-\Mult0|auto_generated|op_1~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_1~8_combout\ = ((\Mult0|auto_generated|le4a\(4) $ (\Mult0|auto_generated|le5a\(2) $ (!\Mult0|auto_generated|op_1~7\)))) # (GND)
--- \Mult0|auto_generated|op_1~9\ = CARRY((\Mult0|auto_generated|le4a\(4) & ((\Mult0|auto_generated|le5a\(2)) # (!\Mult0|auto_generated|op_1~7\))) # (!\Mult0|auto_generated|le4a\(4) & (\Mult0|auto_generated|le5a\(2) & !\Mult0|auto_generated|op_1~7\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|le4a\(4),
- datab => \Mult0|auto_generated|le5a\(2),
- datad => VCC,
- cin => \Mult0|auto_generated|op_1~7\,
- combout => \Mult0|auto_generated|op_1~8_combout\,
- cout => \Mult0|auto_generated|op_1~9\);
-
--- Location: LCCOMB_X66_Y72_N24
-\Mult0|auto_generated|op_3~12\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_3~12_combout\ = ((\Mult0|auto_generated|op_1~8_combout\ $ (\Mult0|auto_generated|le3a\(5) $ (!\Mult0|auto_generated|op_3~11\)))) # (GND)
--- \Mult0|auto_generated|op_3~13\ = CARRY((\Mult0|auto_generated|op_1~8_combout\ & ((\Mult0|auto_generated|le3a\(5)) # (!\Mult0|auto_generated|op_3~11\))) # (!\Mult0|auto_generated|op_1~8_combout\ & (\Mult0|auto_generated|le3a\(5) &
--- !\Mult0|auto_generated|op_3~11\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|op_1~8_combout\,
- datab => \Mult0|auto_generated|le3a\(5),
- datad => VCC,
- cin => \Mult0|auto_generated|op_3~11\,
- combout => \Mult0|auto_generated|op_3~12_combout\,
- cout => \Mult0|auto_generated|op_3~13\);
-
--- Location: LCCOMB_X67_Y72_N2
-\m~10\ : cycloneive_lcell_comb
--- Equation(s):
--- \m~10_combout\ = (!\op[2]~input_o\ & (\Mult0|auto_generated|op_3~12_combout\ & (!\op[0]~input_o\ & \op[1]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000010000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \op[2]~input_o\,
- datab => \Mult0|auto_generated|op_3~12_combout\,
- datac => \op[0]~input_o\,
- datad => \op[1]~input_o\,
- combout => \m~10_combout\);
-
--- Location: LCCOMB_X65_Y72_N22
-\Mult0|auto_generated|le5a[3]\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|le5a\(3) = LCELL((\a[3]~input_o\ & ((\b[3]~input_o\) # ((\b[2]~input_o\ & \b[1]~input_o\)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100110010000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \b[2]~input_o\,
- datab => \a[3]~input_o\,
- datac => \b[1]~input_o\,
- datad => \b[3]~input_o\,
- combout => \Mult0|auto_generated|le5a\(3));
-
--- Location: LCCOMB_X65_Y72_N20
-\Mult0|auto_generated|op_1~10\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_1~10_combout\ = \Mult0|auto_generated|le5a\(3) $ (\Mult0|auto_generated|op_1~9\ $ (!\Mult0|auto_generated|le4a\(5)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101010100101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|le5a\(3),
- datad => \Mult0|auto_generated|le4a\(5),
- cin => \Mult0|auto_generated|op_1~9\,
- combout => \Mult0|auto_generated|op_1~10_combout\);
-
--- Location: LCCOMB_X66_Y72_N26
-\Mult0|auto_generated|op_3~14\ : cycloneive_lcell_comb
--- Equation(s):
--- \Mult0|auto_generated|op_3~14_combout\ = \Mult0|auto_generated|op_1~10_combout\ $ (\Mult0|auto_generated|op_3~13\ $ (!\Mult0|auto_generated|le3a\(5)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110011000011",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \Mult0|auto_generated|op_1~10_combout\,
- datad => \Mult0|auto_generated|le3a\(5),
- cin => \Mult0|auto_generated|op_3~13\,
- combout => \Mult0|auto_generated|op_3~14_combout\);
-
--- Location: LCCOMB_X67_Y72_N28
-\m~11\ : cycloneive_lcell_comb
--- Equation(s):
--- \m~11_combout\ = (\Mult0|auto_generated|op_3~14_combout\ & (\op[1]~input_o\ & (!\op[0]~input_o\ & !\op[2]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Mult0|auto_generated|op_3~14_combout\,
- datab => \op[1]~input_o\,
- datac => \op[0]~input_o\,
- datad => \op[2]~input_o\,
- combout => \m~11_combout\);
-
-ww_r(0) <= \r[0]~output_o\;
-
-ww_r(1) <= \r[1]~output_o\;
-
-ww_r(2) <= \r[2]~output_o\;
-
-ww_r(3) <= \r[3]~output_o\;
-
-ww_m(0) <= \m[0]~output_o\;
-
-ww_m(1) <= \m[1]~output_o\;
-
-ww_m(2) <= \m[2]~output_o\;
-
-ww_m(3) <= \m[3]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/simulation/modelsim/ALUDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica03/ALUDemo/simulation/modelsim/ALUDemo_modelsim.xrf
deleted file mode 100644
index c916002..0000000
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/simulation/modelsim/ALUDemo_modelsim.xrf
+++ /dev/null
@@ -1,143 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALUDemo.bdf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_divide.tdf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/abs_divider.inc
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/sign_div_unsign.inc
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/aglobal201.inc
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/cbx.lst
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_i9m.tdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/sign_div_unsign_7kh.tdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/alt_u_div_24f.tdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_7pc.tdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_8pc.tdf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_mult.tdf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_add_sub.inc
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/multcore.inc
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/bypassff.inc
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/altshift.inc
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_fhm.tdf
-design_name = hard_block
-design_name = ALU4
-instance = comp, \r[0]~output\, r[0]~output, ALU4, 1
-instance = comp, \r[1]~output\, r[1]~output, ALU4, 1
-instance = comp, \r[2]~output\, r[2]~output, ALU4, 1
-instance = comp, \r[3]~output\, r[3]~output, ALU4, 1
-instance = comp, \m[0]~output\, m[0]~output, ALU4, 1
-instance = comp, \m[1]~output\, m[1]~output, ALU4, 1
-instance = comp, \m[2]~output\, m[2]~output, ALU4, 1
-instance = comp, \m[3]~output\, m[3]~output, ALU4, 1
-instance = comp, \a[0]~input\, a[0]~input, ALU4, 1
-instance = comp, \b[1]~input\, b[1]~input, ALU4, 1
-instance = comp, \b[0]~input\, b[0]~input, ALU4, 1
-instance = comp, \Mult0|auto_generated|le3a[0]\, Mult0|auto_generated|le3a[0], ALU4, 1
-instance = comp, \Mult0|auto_generated|op_3~0\, Mult0|auto_generated|op_3~0, ALU4, 1
-instance = comp, \op[0]~input\, op[0]~input, ALU4, 1
-instance = comp, \Add0~0\, Add0~0, ALU4, 1
-instance = comp, \Add0~2\, Add0~2, ALU4, 1
-instance = comp, \Add0~3\, Add0~3, ALU4, 1
-instance = comp, \op[2]~input\, op[2]~input, ALU4, 1
-instance = comp, \op[1]~input\, op[1]~input, ALU4, 1
-instance = comp, \Mux3~4\, Mux3~4, ALU4, 1
-instance = comp, \Mux3~3\, Mux3~3, ALU4, 1
-instance = comp, \Mux3~5\, Mux3~5, ALU4, 1
-instance = comp, \b[2]~input\, b[2]~input, ALU4, 1
-instance = comp, \a[2]~input\, a[2]~input, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|StageOut[5]~0\, Mod0|auto_generated|divider|divider|StageOut[5]~0, ALU4, 1
-instance = comp, \a[3]~input\, a[3]~input, ALU4, 1
-instance = comp, \b[3]~input\, b[3]~input, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|StageOut[5]~1\, Mod0|auto_generated|divider|divider|StageOut[5]~1, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|selnose[5]~0\, Mod0|auto_generated|divider|divider|selnose[5]~0, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|StageOut[4]~2\, Mod0|auto_generated|divider|divider|StageOut[4]~2, ALU4, 1
-instance = comp, \a[1]~input\, a[1]~input, ALU4, 1
-instance = comp, \Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~0\, Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~0, ALU4, 1
-instance = comp, \Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~2\, Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~2, ALU4, 1
-instance = comp, \Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~4\, Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~4, ALU4, 1
-instance = comp, \Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6\, Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6, ALU4, 1
-instance = comp, \Div0|auto_generated|divider|divider|StageOut[10]~0\, Div0|auto_generated|divider|divider|StageOut[10]~0, ALU4, 1
-instance = comp, \Div0|auto_generated|divider|divider|StageOut[9]~1\, Div0|auto_generated|divider|divider|StageOut[9]~1, ALU4, 1
-instance = comp, \Div0|auto_generated|divider|divider|StageOut[8]~2\, Div0|auto_generated|divider|divider|StageOut[8]~2, ALU4, 1
-instance = comp, \Div0|auto_generated|divider|divider|add_sub_3_result_int[0]~1\, Div0|auto_generated|divider|divider|add_sub_3_result_int[0]~1, ALU4, 1
-instance = comp, \Div0|auto_generated|divider|divider|add_sub_3_result_int[1]~3\, Div0|auto_generated|divider|divider|add_sub_3_result_int[1]~3, ALU4, 1
-instance = comp, \Div0|auto_generated|divider|divider|add_sub_3_result_int[2]~5\, Div0|auto_generated|divider|divider|add_sub_3_result_int[2]~5, ALU4, 1
-instance = comp, \Div0|auto_generated|divider|divider|add_sub_3_result_int[3]~7\, Div0|auto_generated|divider|divider|add_sub_3_result_int[3]~7, ALU4, 1
-instance = comp, \Div0|auto_generated|divider|divider|add_sub_3_result_int[4]~8\, Div0|auto_generated|divider|divider|add_sub_3_result_int[4]~8, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~0\, Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~0, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~0\, Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~0, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~2\, Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~2, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~4\, Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~4, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6\, Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|StageOut[10]~3\, Mod0|auto_generated|divider|divider|StageOut[10]~3, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|StageOut[9]~4\, Mod0|auto_generated|divider|divider|StageOut[9]~4, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|StageOut[8]~5\, Mod0|auto_generated|divider|divider|StageOut[8]~5, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~2\, Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~2, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~4\, Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~4, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~6\, Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~6, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8\, Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8, ALU4, 1
-instance = comp, \Mux3~0\, Mux3~0, ALU4, 1
-instance = comp, \Mux3~1\, Mux3~1, ALU4, 1
-instance = comp, \Mux3~2\, Mux3~2, ALU4, 1
-instance = comp, \Mux3~6\, Mux3~6, ALU4, 1
-instance = comp, \Mult0|auto_generated|le3a[1]\, Mult0|auto_generated|le3a[1], ALU4, 1
-instance = comp, \Mult0|auto_generated|op_3~2\, Mult0|auto_generated|op_3~2, ALU4, 1
-instance = comp, \Mux2~2\, Mux2~2, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|StageOut[13]~6\, Mod0|auto_generated|divider|divider|StageOut[13]~6, ALU4, 1
-instance = comp, \Mux2~3\, Mux2~3, ALU4, 1
-instance = comp, \Add0~5\, Add0~5, ALU4, 1
-instance = comp, \Add0~6\, Add0~6, ALU4, 1
-instance = comp, \Mux2~0\, Mux2~0, ALU4, 1
-instance = comp, \Div0|auto_generated|divider|divider|selnose[10]\, Div0|auto_generated|divider|divider|selnose[10], ALU4, 1
-instance = comp, \Mux2~1\, Mux2~1, ALU4, 1
-instance = comp, \Mux1~2\, Mux1~2, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|StageOut[14]~7\, Mod0|auto_generated|divider|divider|StageOut[14]~7, ALU4, 1
-instance = comp, \Mux1~3\, Mux1~3, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|selnose[5]~1\, Mod0|auto_generated|divider|divider|selnose[5]~1, ALU4, 1
-instance = comp, \Mult0|auto_generated|le4a[0]\, Mult0|auto_generated|le4a[0], ALU4, 1
-instance = comp, \Mult0|auto_generated|le3a[2]\, Mult0|auto_generated|le3a[2], ALU4, 1
-instance = comp, \Mult0|auto_generated|le4a[5]\, Mult0|auto_generated|le4a[5], ALU4, 1
-instance = comp, \Mult0|auto_generated|op_1~0\, Mult0|auto_generated|op_1~0, ALU4, 1
-instance = comp, \Mult0|auto_generated|op_3~4\, Mult0|auto_generated|op_3~4, ALU4, 1
-instance = comp, \Add0~8\, Add0~8, ALU4, 1
-instance = comp, \Add0~9\, Add0~9, ALU4, 1
-instance = comp, \Mux1~0\, Mux1~0, ALU4, 1
-instance = comp, \Mux1~1\, Mux1~1, ALU4, 1
-instance = comp, \Mult0|auto_generated|le3a[3]\, Mult0|auto_generated|le3a[3], ALU4, 1
-instance = comp, \Mult0|auto_generated|op_1~2\, Mult0|auto_generated|op_1~2, ALU4, 1
-instance = comp, \Mult0|auto_generated|cs2a[1]~0\, Mult0|auto_generated|cs2a[1]~0, ALU4, 1
-instance = comp, \Mult0|auto_generated|le4a[1]\, Mult0|auto_generated|le4a[1], ALU4, 1
-instance = comp, \Mult0|auto_generated|op_3~6\, Mult0|auto_generated|op_3~6, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|StageOut[15]~8\, Mod0|auto_generated|divider|divider|StageOut[15]~8, ALU4, 1
-instance = comp, \Mux0~2\, Mux0~2, ALU4, 1
-instance = comp, \Mux0~3\, Mux0~3, ALU4, 1
-instance = comp, \Add0~11\, Add0~11, ALU4, 1
-instance = comp, \Add0~12\, Add0~12, ALU4, 1
-instance = comp, \Mux0~0\, Mux0~0, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|selnose[0]~2\, Mod0|auto_generated|divider|divider|selnose[0]~2, ALU4, 1
-instance = comp, \Mod0|auto_generated|divider|divider|selnose[0]\, Mod0|auto_generated|divider|divider|selnose[0], ALU4, 1
-instance = comp, \Mux0~1\, Mux0~1, ALU4, 1
-instance = comp, \Mult0|auto_generated|le3a[4]\, Mult0|auto_generated|le3a[4], ALU4, 1
-instance = comp, \Mult0|auto_generated|le4a[2]\, Mult0|auto_generated|le4a[2], ALU4, 1
-instance = comp, \Mult0|auto_generated|op_1~4\, Mult0|auto_generated|op_1~4, ALU4, 1
-instance = comp, \Mult0|auto_generated|le5a[0]\, Mult0|auto_generated|le5a[0], ALU4, 1
-instance = comp, \Mult0|auto_generated|op_3~8\, Mult0|auto_generated|op_3~8, ALU4, 1
-instance = comp, \m~8\, m~8, ALU4, 1
-instance = comp, \Mult0|auto_generated|le5a[1]\, Mult0|auto_generated|le5a[1], ALU4, 1
-instance = comp, \Mult0|auto_generated|le4a[3]\, Mult0|auto_generated|le4a[3], ALU4, 1
-instance = comp, \Mult0|auto_generated|op_1~6\, Mult0|auto_generated|op_1~6, ALU4, 1
-instance = comp, \Mult0|auto_generated|le3a[5]\, Mult0|auto_generated|le3a[5], ALU4, 1
-instance = comp, \Mult0|auto_generated|op_3~10\, Mult0|auto_generated|op_3~10, ALU4, 1
-instance = comp, \m~9\, m~9, ALU4, 1
-instance = comp, \Mult0|auto_generated|le4a[4]\, Mult0|auto_generated|le4a[4], ALU4, 1
-instance = comp, \Mult0|auto_generated|le5a[2]\, Mult0|auto_generated|le5a[2], ALU4, 1
-instance = comp, \Mult0|auto_generated|op_1~8\, Mult0|auto_generated|op_1~8, ALU4, 1
-instance = comp, \Mult0|auto_generated|op_3~12\, Mult0|auto_generated|op_3~12, ALU4, 1
-instance = comp, \m~10\, m~10, ALU4, 1
-instance = comp, \Mult0|auto_generated|le5a[3]\, Mult0|auto_generated|le5a[3], ALU4, 1
-instance = comp, \Mult0|auto_generated|op_1~10\, Mult0|auto_generated|op_1~10, ALU4, 1
-instance = comp, \Mult0|auto_generated|op_3~14\, Mult0|auto_generated|op_3~14, ALU4, 1
-instance = comp, \m~11\, m~11, ALU4, 1
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd.bak b/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd.bak
deleted file mode 100644
index c86e612..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd.bak
+++ /dev/null
@@ -1,29 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-
-entity AddSub4 is
- port
- (
- sub : in std_logic;
- a, b : in std_logic_vector(3 downto 0);
- cout : out std_logic;
- s : out std_logic_vector(3 downto 0)
- );
-end AddSub4;
-
-architecture Structural of AddSub4 is
- signal s_b: std_logic_vector(3 downto 0);
-begin
- -- Mux
- sub_mux : s_b <= b when sub = '0' else
- not b;
-
- -- out_mux : cout <= s_cout when sub='0' else
- -- not s_cout;
-
- Adder : entity work.Adder4(Structural) port map
- (
- cin => sub, a => a, b => s_b, cout => cout, s => s
- );
-end Structural;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd.bak b/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd.bak
deleted file mode 100644
index b4d9b7e..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd.bak
+++ /dev/null
@@ -1,39 +0,0 @@
-
-
-
-architecture Structural of Adder4 is
- signal intCarry : std_logic_vector(2 downto 0);
-begin
- bit0 : entity work.FullAdder(Behavioral) port map
- (
- a => a(0),
- b => b(0),
- cin => cin,
- s => s(0),
- cout => intCarry(0)
- );
- bit1 : entity work.FullAdder(Behavioral) port map
- (
- a => a(1),
- b => b(1),
- cin => intCarry(0),
- s => s(1),
- cout => intCarry(1)
- );
- bit2 : entity work.FullAdder(Behavioral) port map
- (
- a => a(2),
- b => b(2),
- cin => intCarry(1),
- s => s(2),
- cout => intCarry(2)
- );
- bit3 : entity work.FullAdder(Behavioral) port map
- (
- a => a(3),
- b => b(3),
- cin => intCarry(2),
- s => s(3),
- cout => cout
- );
-end Structural;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.qpf b/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.qpf
deleted file mode 100644
index 50ba715..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 10:31:52 March 08, 2023
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "20.1"
-DATE = "10:31:52 March 08, 2023"
-
-# Revisions
-
-PROJECT_REVISION = "AdderDemo"
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.qsf b/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.qsf
deleted file mode 100644
index dd31f0c..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.qsf
+++ /dev/null
@@ -1,585 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 10:31:52 March 08, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# AdderDemo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY AdderDemo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:31:52 MARCH 08, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VHDL_FILE FullAdder.vhd
-set_global_assignment -name VHDL_FILE Adder4.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE Adder4.vwf
-set_global_assignment -name BDF_FILE AdderDemo.bdf
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_global_assignment -name VHDL_FILE AddSub4.vhd
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.qsf.bak b/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.qsf.bak
deleted file mode 100644
index dd31f0c..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.qsf.bak
+++ /dev/null
@@ -1,585 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 10:31:52 March 08, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# AdderDemo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY AdderDemo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:31:52 MARCH 08, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VHDL_FILE FullAdder.vhd
-set_global_assignment -name VHDL_FILE Adder4.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE Adder4.vwf
-set_global_assignment -name BDF_FILE AdderDemo.bdf
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_global_assignment -name VHDL_FILE AddSub4.vhd
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.qws b/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.qws
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd.bak b/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd.bak
deleted file mode 100644
index e69de29..0000000
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(0).cnf.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(0).cnf.cdb
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index 6c5f4b5..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(0).cnf.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(0).cnf.hdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(1).cnf.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(1).cnf.cdb
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index f8f624e..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(1).cnf.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(1).cnf.hdb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(2).cnf.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(2).cnf.cdb
deleted file mode 100644
index 91dbed4..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(2).cnf.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(2).cnf.hdb
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index 3b6bcb8..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(3).cnf.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(3).cnf.cdb
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index 83c7f4b..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(3).cnf.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(3).cnf.hdb
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index 6eedcbe..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(4).cnf.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(4).cnf.cdb
deleted file mode 100644
index cf65b91..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(4).cnf.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.(4).cnf.hdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.asm.qmsg b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.asm.qmsg
deleted file mode 100644
index 95d47f1..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.asm.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678380693793 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678380693794 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 16:51:33 2023 " "Processing started: Thu Mar 9 16:51:33 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678380693794 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678380693794 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678380693794 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678380693930 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678380695489 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678380695577 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "362 " "Peak virtual memory: 362 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678380695783 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 16:51:35 2023 " "Processing ended: Thu Mar 9 16:51:35 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678380695783 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678380695783 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678380695783 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678380695783 ""}
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.asm.rdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.asm.rdb
deleted file mode 100644
index 7e4a7d8..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.asm_labs.ddb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.asm_labs.ddb
deleted file mode 100644
index 6c4e0bb..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.asm_labs.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cbx.xml b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cbx.xml
deleted file mode 100644
index e49b372..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.bpm b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.bpm
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.cdb
deleted file mode 100644
index e3870f7..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.hdb
deleted file mode 100644
index 8a37533..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.idb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.idb
deleted file mode 100644
index 43dae6b..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.logdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.logdb
deleted file mode 100644
index 97d083c..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.logdb
+++ /dev/null
@@ -1,76 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;34;34;0;0;34;34;0;0;0;0;0;0;15;0;0;0;19;15;0;19;0;0;15;0;34;34;34;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,34;0;0;34;34;0;0;34;34;34;34;34;34;19;34;34;34;15;19;34;15;34;34;19;34;0;0;0;34;34,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,LEDR[14],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[13],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[12],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[11],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[10],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[13],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[17],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[12],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[16],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[11],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[15],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[10],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[14],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.rdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.rdb
deleted file mode 100644
index a3cbfaf..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp_merge.kpt b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp_merge.kpt
deleted file mode 100644
index 2fb013b..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cmp_merge.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index 12d57d7..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
deleted file mode 100644
index 218eca7..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
deleted file mode 100644
index bea9e20..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.db_info b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.db_info
deleted file mode 100644
index 3104721..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Mon Mar 13 19:07:09 2023
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.eda.qmsg b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.eda.qmsg
deleted file mode 100644
index fcab146..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678380698268 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678380698268 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 16:51:38 2023 " "Processing started: Thu Mar 9 16:51:38 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678380698268 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678380698268 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678380698269 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678380698444 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "AdderDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/ simulation " "Generated file AdderDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678380698471 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678380698483 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 16:51:38 2023 " "Processing ended: Thu Mar 9 16:51:38 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678380698483 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678380698483 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678380698483 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678380698483 ""}
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.fit.qmsg b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.fit.qmsg
deleted file mode 100644
index 418e05d..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.fit.qmsg
+++ /dev/null
@@ -1,48 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678380686859 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678380686859 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "AdderDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"AdderDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678380686861 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678380686908 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678380686908 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678380687163 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678380687166 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380687197 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380687197 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380687197 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380687197 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380687197 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380687197 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380687197 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380687197 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380687197 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678380687197 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/" { { 0 { 0 ""} 0 637 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678380687200 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/" { { 0 { 0 ""} 0 639 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678380687200 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/" { { 0 { 0 ""} 0 641 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678380687200 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/" { { 0 { 0 ""} 0 643 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678380687200 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/" { { 0 { 0 ""} 0 645 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678380687200 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678380687200 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678380687201 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AdderDemo.sdc " "Synopsys Design Constraints File file not found: 'AdderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678380687703 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678380687703 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678380687703 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678380687704 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678380687704 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678380687704 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678380687705 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678380687707 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678380687707 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678380687707 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678380687708 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678380687708 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678380687708 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678380687708 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678380687708 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678380687708 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678380687708 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678380687708 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380687734 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678380687734 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678380687742 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678380687745 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678380689405 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678380689477 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678380689504 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678380689794 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678380689795 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678380689941 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y12 X115_Y23 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23"} { { 12 { 0 ""} 104 12 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678380692107 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678380692107 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678380692225 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678380692225 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678380692225 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678380692227 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678380692306 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678380692314 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678380692492 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678380692492 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678380692671 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678380692921 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678380693102 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678380693142 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 492 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 492 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1151 " "Peak virtual memory: 1151 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678380693272 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 16:51:33 2023 " "Processing ended: Thu Mar 9 16:51:33 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678380693272 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678380693272 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678380693272 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678380693272 ""}
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.hier_info b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.hier_info
deleted file mode 100644
index 4d775ca..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.hier_info
+++ /dev/null
@@ -1,139 +0,0 @@
-|AdderDemo
-LEDR[0] <= Adder4:Adder4Demo.s[0]
-LEDR[1] <= Adder4:Adder4Demo.s[1]
-LEDR[2] <= Adder4:Adder4Demo.s[2]
-LEDR[3] <= Adder4:Adder4Demo.s[3]
-LEDR[4] <= Adder4:Adder4Demo.cout
-LEDR[5] <=
-LEDR[6] <=
-LEDR[7] <=
-LEDR[8] <=
-LEDR[9] <=
-LEDR[10] <= AddSub4:AddSub4Demo.s[0]
-LEDR[11] <= AddSub4:AddSub4Demo.s[1]
-LEDR[12] <= AddSub4:AddSub4Demo.s[2]
-LEDR[13] <= AddSub4:AddSub4Demo.s[3]
-LEDR[14] <= AddSub4:AddSub4Demo.cout
-SW[0] => Adder4:Adder4Demo.b[0]
-SW[1] => Adder4:Adder4Demo.b[1]
-SW[2] => Adder4:Adder4Demo.b[2]
-SW[3] => Adder4:Adder4Demo.b[3]
-SW[4] => Adder4:Adder4Demo.a[0]
-SW[5] => Adder4:Adder4Demo.a[1]
-SW[6] => Adder4:Adder4Demo.a[2]
-SW[7] => Adder4:Adder4Demo.a[3]
-SW[8] => ~NO_FANOUT~
-SW[9] => ~NO_FANOUT~
-SW[10] => AddSub4:AddSub4Demo.b[0]
-SW[11] => AddSub4:AddSub4Demo.b[1]
-SW[12] => AddSub4:AddSub4Demo.b[2]
-SW[13] => AddSub4:AddSub4Demo.b[3]
-SW[14] => AddSub4:AddSub4Demo.a[0]
-SW[15] => AddSub4:AddSub4Demo.a[1]
-SW[16] => AddSub4:AddSub4Demo.a[2]
-SW[17] => AddSub4:AddSub4Demo.a[3]
-KEY[0] => AddSub4:AddSub4Demo.sub
-
-
-|AdderDemo|Adder4:Adder4Demo
-a[0] => fulladder:bit0.a
-a[1] => fulladder:bit1.a
-a[2] => fulladder:bit2.a
-a[3] => fulladder:bit3.a
-b[0] => fulladder:bit0.b
-b[1] => fulladder:bit1.b
-b[2] => fulladder:bit2.b
-b[3] => fulladder:bit3.b
-cin => fulladder:bit0.cin
-s[0] <= fulladder:bit0.s
-s[1] <= fulladder:bit1.s
-s[2] <= fulladder:bit2.s
-s[3] <= fulladder:bit3.s
-cout <= fulladder:bit3.cout
-
-
-|AdderDemo|Adder4:Adder4Demo|FullAdder:bit0
-a => s.IN0
-a => cout.IN0
-a => cout.IN0
-b => s.IN1
-b => cout.IN1
-b => cout.IN0
-cin => s.IN1
-cin => cout.IN1
-cin => cout.IN1
-s <= s.DB_MAX_OUTPUT_PORT_TYPE
-cout <= cout.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|AdderDemo|Adder4:Adder4Demo|FullAdder:bit1
-a => s.IN0
-a => cout.IN0
-a => cout.IN0
-b => s.IN1
-b => cout.IN1
-b => cout.IN0
-cin => s.IN1
-cin => cout.IN1
-cin => cout.IN1
-s <= s.DB_MAX_OUTPUT_PORT_TYPE
-cout <= cout.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|AdderDemo|Adder4:Adder4Demo|FullAdder:bit2
-a => s.IN0
-a => cout.IN0
-a => cout.IN0
-b => s.IN1
-b => cout.IN1
-b => cout.IN0
-cin => s.IN1
-cin => cout.IN1
-cin => cout.IN1
-s <= s.DB_MAX_OUTPUT_PORT_TYPE
-cout <= cout.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|AdderDemo|Adder4:Adder4Demo|FullAdder:bit3
-a => s.IN0
-a => cout.IN0
-a => cout.IN0
-b => s.IN1
-b => cout.IN1
-b => cout.IN0
-cin => s.IN1
-cin => cout.IN1
-cin => cout.IN1
-s <= s.DB_MAX_OUTPUT_PORT_TYPE
-cout <= cout.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|AdderDemo|AddSub4:AddSub4Demo
-a[0] => Add0.IN10
-a[0] => Add1.IN6
-a[1] => Add0.IN9
-a[1] => Add1.IN5
-a[2] => Add0.IN8
-a[2] => Add1.IN4
-a[3] => Add0.IN7
-a[3] => Add1.IN3
-b[0] => Add1.IN10
-b[0] => Add0.IN6
-b[1] => Add1.IN9
-b[1] => Add0.IN5
-b[2] => Add1.IN8
-b[2] => Add0.IN4
-b[3] => Add1.IN7
-b[3] => Add0.IN3
-sub => s_s.OUTPUTSELECT
-sub => s_s.OUTPUTSELECT
-sub => s_s.OUTPUTSELECT
-sub => s_s.OUTPUTSELECT
-sub => s_s.OUTPUTSELECT
-s[0] <= s_s.DB_MAX_OUTPUT_PORT_TYPE
-s[1] <= s_s.DB_MAX_OUTPUT_PORT_TYPE
-s[2] <= s_s.DB_MAX_OUTPUT_PORT_TYPE
-s[3] <= s_s.DB_MAX_OUTPUT_PORT_TYPE
-cout <= s_s.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.hif b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.hif
deleted file mode 100644
index e43b0b3..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.hif and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.lpc.html b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.lpc.html
deleted file mode 100644
index d407443..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.lpc.html
+++ /dev/null
@@ -1,114 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| AddSub4Demo |
-9 |
-0 |
-0 |
-0 |
-5 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
-| Adder4Demo|bit3 |
-3 |
-0 |
-0 |
-0 |
-2 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
-| Adder4Demo|bit2 |
-3 |
-0 |
-0 |
-0 |
-2 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
-| Adder4Demo|bit1 |
-3 |
-0 |
-0 |
-0 |
-2 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
-| Adder4Demo|bit0 |
-3 |
-0 |
-0 |
-0 |
-2 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
-| Adder4Demo |
-9 |
-1 |
-0 |
-1 |
-5 |
-1 |
-1 |
-1 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.lpc.rdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.lpc.rdb
deleted file mode 100644
index 46f994e..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.lpc.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.lpc.txt b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.lpc.txt
deleted file mode 100644
index bf5d387..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.lpc.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; AddSub4Demo ; 9 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Adder4Demo|bit3 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Adder4Demo|bit2 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Adder4Demo|bit1 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Adder4Demo|bit0 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Adder4Demo ; 9 ; 1 ; 0 ; 1 ; 5 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.ammdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.ammdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.bpm b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.bpm
deleted file mode 100644
index 781c128..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.cdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.hdb
deleted file mode 100644
index a89d6fd..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.kpt b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.kpt
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index b767219..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.logdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.qmsg b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.qmsg
deleted file mode 100644
index ee53c5e..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.qmsg
+++ /dev/null
@@ -1,20 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678380679758 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678380679758 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 16:51:19 2023 " "Processing started: Thu Mar 9 16:51:19 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678380679758 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380679758 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380679758 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678380679908 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678380679908 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FullAdder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FullAdder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FullAdder-Behavioral " "Found design unit 1: FullAdder-Behavioral" { } { { "FullAdder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685473 ""} { "Info" "ISGN_ENTITY_NAME" "1 FullAdder " "Found entity 1: FullAdder" { } { { "FullAdder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685473 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380685473 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Adder4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Adder4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Adder4-Structural " "Found design unit 1: Adder4-Structural" { } { { "Adder4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685473 ""} { "Info" "ISGN_ENTITY_NAME" "1 Adder4 " "Found entity 1: Adder4" { } { { "Adder4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685473 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380685473 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AdderDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file AdderDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 AdderDemo " "Found entity 1: AdderDemo" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685473 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380685473 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AddSub4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AddSub4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AddSub4-Behavioral " "Found design unit 1: AddSub4-Behavioral" { } { { "AddSub4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd" 29 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685474 ""} { "Info" "ISGN_ENTITY_NAME" "1 AddSub4 " "Found entity 1: AddSub4" { } { { "AddSub4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685474 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380685474 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "AdderDemo " "Elaborating entity \"AdderDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678380685504 ""}
-{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND Ground2 " "Primitive \"GND\" of instance \"Ground2\" not used" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 304 464 496 336 "Ground2" "" } } } } } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Analysis & Synthesis" 0 -1 1678380685505 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Adder4 Adder4:Adder4Demo " "Elaborating entity \"Adder4\" for hierarchy \"Adder4:Adder4Demo\"" { } { { "AdderDemo.bdf" "Adder4Demo" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 160 488 640 272 "Adder4Demo" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678380685506 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "FullAdder Adder4:Adder4Demo\|FullAdder:bit0 A:behavioral " "Elaborating entity \"FullAdder\" using architecture \"A:behavioral\" for hierarchy \"Adder4:Adder4Demo\|FullAdder:bit0\"" { } { { "Adder4.vhd" "bit0" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd" 17 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678380685507 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AddSub4 AddSub4:AddSub4Demo " "Elaborating entity \"AddSub4\" for hierarchy \"AddSub4:AddSub4Demo\"" { } { { "AdderDemo.bdf" "AddSub4Demo" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 344 488 640 456 "AddSub4Demo" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678380685509 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[9\] GND " "Pin \"LEDR\[9\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380685841 "|AdderDemo|LEDR[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[8\] GND " "Pin \"LEDR\[8\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380685841 "|AdderDemo|LEDR[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[7\] GND " "Pin \"LEDR\[7\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380685841 "|AdderDemo|LEDR[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[6\] GND " "Pin \"LEDR\[6\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380685841 "|AdderDemo|LEDR[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[5\] GND " "Pin \"LEDR\[5\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380685841 "|AdderDemo|LEDR[5]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1678380685841 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678380685896 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678380686259 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678380686259 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 200 312 480 216 "SW" "" } } } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1678380686280 "|AdderDemo|SW[9]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 200 312 480 216 "SW" "" } } } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1678380686280 "|AdderDemo|SW[8]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1678380686280 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "51 " "Implemented 51 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "19 " "Implemented 19 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678380686280 ""} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Implemented 15 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678380686280 ""} { "Info" "ICUT_CUT_TM_LCELLS" "17 " "Implemented 17 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678380686280 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678380686280 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "431 " "Peak virtual memory: 431 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678380686284 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 16:51:26 2023 " "Processing ended: Thu Mar 9 16:51:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678380686284 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678380686284 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678380686284 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380686284 ""}
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.rdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.rdb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map_bb.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map_bb.cdb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map_bb.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map_bb.hdb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map_bb.logdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.pre_map.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.root_partition.map.reg_db.cdb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.routing.rdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.rtlv.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.rtlv_sg.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.rtlv_sg.cdb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.rtlv_sg_swap.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.rtlv_sg_swap.cdb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.sld_design_entry.sci b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.smart_action.txt b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.smart_action.txt
deleted file mode 100644
index c8e8a13..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.sta.qmsg b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.sta.qmsg
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--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678380696292 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678380696292 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 16:51:36 2023 " "Processing started: Thu Mar 9 16:51:36 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678380696292 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678380696292 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta AdderDemo -c AdderDemo " "Command: quartus_sta AdderDemo -c AdderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678380696292 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678380696317 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678380696381 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678380696381 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678380696433 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678380696433 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AdderDemo.sdc " "Synopsys Design Constraints File file not found: 'AdderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678380696745 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678380696745 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678380696746 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678380696746 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678380696746 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678380696746 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678380696746 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678380696750 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678380696750 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380696751 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380696753 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380696754 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380696754 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380696755 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380696755 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678380696757 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678380696770 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678380696944 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678380696958 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678380696958 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678380696958 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678380696958 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380696959 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380696960 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380696960 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380696960 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380696961 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380696961 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678380696963 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678380697003 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678380697003 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678380697003 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678380697003 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380697004 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380697005 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380697005 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380697006 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380697006 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678380697236 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678380697236 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "535 " "Peak virtual memory: 535 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678380697247 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 16:51:37 2023 " "Processing ended: Thu Mar 9 16:51:37 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678380697247 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678380697247 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678380697247 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678380697247 ""}
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.sta.rdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.sta.rdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.sta_cmp.7_slow_1200mv_85c.tdb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.tis_db_list.ddb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.tiscmp.fast_1200mv_0c.ddb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index b639f55..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index 0e37ac4..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.tmw_info b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.tmw_info
deleted file mode 100644
index 1bd50f7..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.tmw_info
+++ /dev/null
@@ -1,4 +0,0 @@
-start_full_compilation:s
-start_assembler:s-start_full_compilation
-start_timing_analyzer:s-start_full_compilation
-start_eda_netlist_writer:s-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.vpr.ammdb b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.vpr.ammdb
deleted file mode 100644
index 2af95d4..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo_partition_pins.json b/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo_partition_pins.json
deleted file mode 100644
index c5f10a2..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo_partition_pins.json
+++ /dev/null
@@ -1,117 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "LEDR[14]",
- "strict" : false
- },
- {
- "name" : "LEDR[13]",
- "strict" : false
- },
- {
- "name" : "LEDR[12]",
- "strict" : false
- },
- {
- "name" : "LEDR[11]",
- "strict" : false
- },
- {
- "name" : "LEDR[10]",
- "strict" : false
- },
- {
- "name" : "LEDR[4]",
- "strict" : false
- },
- {
- "name" : "LEDR[3]",
- "strict" : false
- },
- {
- "name" : "LEDR[2]",
- "strict" : false
- },
- {
- "name" : "LEDR[1]",
- "strict" : false
- },
- {
- "name" : "LEDR[0]",
- "strict" : false
- },
- {
- "name" : "KEY[0]",
- "strict" : false
- },
- {
- "name" : "SW[13]",
- "strict" : false
- },
- {
- "name" : "SW[17]",
- "strict" : false
- },
- {
- "name" : "SW[12]",
- "strict" : false
- },
- {
- "name" : "SW[16]",
- "strict" : false
- },
- {
- "name" : "SW[11]",
- "strict" : false
- },
- {
- "name" : "SW[15]",
- "strict" : false
- },
- {
- "name" : "SW[10]",
- "strict" : false
- },
- {
- "name" : "SW[14]",
- "strict" : false
- },
- {
- "name" : "SW[7]",
- "strict" : false
- },
- {
- "name" : "SW[3]",
- "strict" : false
- },
- {
- "name" : "SW[6]",
- "strict" : false
- },
- {
- "name" : "SW[2]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- },
- {
- "name" : "SW[4]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- },
- {
- "name" : "SW[5]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/db/prev_cmp_AdderDemo.qmsg b/1ano/2semestre/lsd/pratica03/AdderDemo/db/prev_cmp_AdderDemo.qmsg
deleted file mode 100644
index ba4cacb..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/db/prev_cmp_AdderDemo.qmsg
+++ /dev/null
@@ -1,139 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678380065907 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678380065907 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 16:41:05 2023 " "Processing started: Thu Mar 9 16:41:05 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678380065907 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380065907 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380065907 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678380066070 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678380066070 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FullAdder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FullAdder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FullAdder-Behavioral " "Found design unit 1: FullAdder-Behavioral" { } { { "FullAdder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380071868 ""} { "Info" "ISGN_ENTITY_NAME" "1 FullAdder " "Found entity 1: FullAdder" { } { { "FullAdder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380071868 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380071868 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Adder4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Adder4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Adder4-Structural " "Found design unit 1: Adder4-Structural" { } { { "Adder4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380071874 ""} { "Info" "ISGN_ENTITY_NAME" "1 Adder4 " "Found entity 1: Adder4" { } { { "Adder4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380071874 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380071874 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AdderDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file AdderDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 AdderDemo " "Found entity 1: AdderDemo" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380071874 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380071874 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AddSub4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AddSub4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AddSub4-Structural " "Found design unit 1: AddSub4-Structural" { } { { "AddSub4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380071874 ""} { "Info" "ISGN_ENTITY_NAME" "1 AddSub4 " "Found entity 1: AddSub4" { } { { "AddSub4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380071874 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380071874 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "AdderDemo " "Elaborating entity \"AdderDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678380071903 ""}
-{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND Ground2 " "Primitive \"GND\" of instance \"Ground2\" not used" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 304 464 496 336 "Ground2" "" } } } } } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Analysis & Synthesis" 0 -1 1678380071904 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Adder4 Adder4:Adder4Demo " "Elaborating entity \"Adder4\" for hierarchy \"Adder4:Adder4Demo\"" { } { { "AdderDemo.bdf" "Adder4Demo" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 160 488 640 272 "Adder4Demo" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678380071905 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "FullAdder Adder4:Adder4Demo\|FullAdder:bit0 A:behavioral " "Elaborating entity \"FullAdder\" using architecture \"A:behavioral\" for hierarchy \"Adder4:Adder4Demo\|FullAdder:bit0\"" { } { { "Adder4.vhd" "bit0" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd" 17 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678380071905 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AddSub4 AddSub4:AddSub4Demo " "Elaborating entity \"AddSub4\" for hierarchy \"AddSub4:AddSub4Demo\"" { } { { "AdderDemo.bdf" "AddSub4Demo" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 344 488 640 456 "AddSub4Demo" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678380071907 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "Adder4 AddSub4:AddSub4Demo\|Adder4:Adder A:structural " "Elaborating entity \"Adder4\" using architecture \"A:structural\" for hierarchy \"AddSub4:AddSub4Demo\|Adder4:Adder\"" { } { { "AddSub4.vhd" "Adder" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd" 23 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678380071908 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[9\] GND " "Pin \"LEDR\[9\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380072238 "|AdderDemo|LEDR[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[8\] GND " "Pin \"LEDR\[8\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380072238 "|AdderDemo|LEDR[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[7\] GND " "Pin \"LEDR\[7\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380072238 "|AdderDemo|LEDR[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[6\] GND " "Pin \"LEDR\[6\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380072238 "|AdderDemo|LEDR[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[5\] GND " "Pin \"LEDR\[5\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380072238 "|AdderDemo|LEDR[5]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1678380072238 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678380072292 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678380072635 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678380072635 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 200 312 480 216 "SW" "" } } } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1678380072656 "|AdderDemo|SW[9]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 200 312 480 216 "SW" "" } } } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1678380072656 "|AdderDemo|SW[8]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1678380072656 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "49 " "Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "19 " "Implemented 19 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678380072656 ""} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Implemented 15 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678380072656 ""} { "Info" "ICUT_CUT_TM_LCELLS" "15 " "Implemented 15 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678380072656 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678380072656 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "431 " "Peak virtual memory: 431 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678380072660 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 16:41:12 2023 " "Processing ended: Thu Mar 9 16:41:12 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678380072660 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678380072660 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678380072660 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380072660 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1678380073214 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678380073214 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 16:41:13 2023 " "Processing started: Thu Mar 9 16:41:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678380073214 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1678380073214 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo " "Command: quartus_fit --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1678380073214 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1678380073233 ""}
-{ "Info" "0" "" "Project = AdderDemo" { } { } 0 0 "Project = AdderDemo" 0 0 "Fitter" 0 0 1678380073234 ""}
-{ "Info" "0" "" "Revision = AdderDemo" { } { } 0 0 "Revision = AdderDemo" 0 0 "Fitter" 0 0 1678380073234 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678380073270 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678380073270 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "AdderDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"AdderDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678380073272 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678380073317 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678380073317 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678380073585 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678380073589 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380073631 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380073631 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380073631 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380073631 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380073631 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380073631 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380073631 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380073631 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678380073631 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678380073631 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/" { { 0 { 0 ""} 0 640 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678380073634 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/" { { 0 { 0 ""} 0 642 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678380073634 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/" { { 0 { 0 ""} 0 644 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678380073634 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/" { { 0 { 0 ""} 0 646 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678380073634 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/" { { 0 { 0 ""} 0 648 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678380073634 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678380073634 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678380073635 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AdderDemo.sdc " "Synopsys Design Constraints File file not found: 'AdderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678380074251 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678380074251 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678380074251 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678380074252 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678380074252 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678380074252 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678380074252 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678380074254 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678380074254 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678380074255 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678380074256 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678380074256 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678380074256 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678380074256 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678380074256 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678380074256 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678380074256 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678380074256 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678380074278 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678380074278 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678380074287 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678380074289 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678380075861 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678380075936 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678380075963 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678380076213 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678380076213 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678380076360 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y12 X115_Y23 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23"} { { 12 { 0 ""} 104 12 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678380078436 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678380078436 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678380078558 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678380078558 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678380078558 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678380078560 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678380078642 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678380078647 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678380078815 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678380078815 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678380078978 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678380079228 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678380079405 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678380079442 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 492 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 492 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1154 " "Peak virtual memory: 1154 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678380079572 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 16:41:19 2023 " "Processing ended: Thu Mar 9 16:41:19 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678380079572 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678380079572 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678380079572 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678380079572 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1678380080073 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678380080073 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 16:41:20 2023 " "Processing started: Thu Mar 9 16:41:20 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678380080073 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678380080073 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678380080073 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678380080213 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678380081766 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678380081847 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "364 " "Peak virtual memory: 364 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678380082051 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 16:41:22 2023 " "Processing ended: Thu Mar 9 16:41:22 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678380082051 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678380082051 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678380082051 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678380082051 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1678380082634 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1678380083040 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678380083040 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 16:41:22 2023 " "Processing started: Thu Mar 9 16:41:22 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678380083040 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678380083040 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta AdderDemo -c AdderDemo " "Command: quartus_sta AdderDemo -c AdderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678380083040 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678380083062 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678380083128 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678380083128 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678380083177 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678380083177 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AdderDemo.sdc " "Synopsys Design Constraints File file not found: 'AdderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678380083491 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678380083491 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678380083491 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678380083491 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678380083491 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678380083492 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678380083492 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678380083495 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678380083495 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083496 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083499 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083500 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083500 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083500 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083501 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678380083502 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678380083520 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678380083697 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678380083714 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678380083714 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678380083714 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678380083714 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083715 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083716 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083717 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083717 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083718 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083718 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678380083720 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678380083763 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678380083763 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678380083763 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678380083763 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083764 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083765 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083765 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083766 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678380083766 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678380083992 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678380083992 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "538 " "Peak virtual memory: 538 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678380084003 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 16:41:24 2023 " "Processing ended: Thu Mar 9 16:41:24 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678380084003 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678380084003 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678380084003 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678380084003 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1678380084488 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678380084488 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 16:41:24 2023 " "Processing started: Thu Mar 9 16:41:24 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678380084488 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678380084488 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678380084488 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678380084660 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "AdderDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/ simulation " "Generated file AdderDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678380084693 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678380084706 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 16:41:24 2023 " "Processing ended: Thu Mar 9 16:41:24 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678380084706 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678380084706 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678380084706 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678380084706 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 510 s " "Quartus Prime Full Compilation was successful. 0 errors, 510 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678380085323 ""}
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/README b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.db_info b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.db_info
deleted file mode 100644
index 488a312..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Wed Mar 8 10:57:54 2023
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.ammdb
deleted file mode 100644
index ec979f8..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.cdb
deleted file mode 100644
index beed2c6..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.dfp and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.hdb
deleted file mode 100644
index 5923f97..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.rcfdb
deleted file mode 100644
index 150eb5c..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.cmp.rcfdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.cdb
deleted file mode 100644
index 08a5d8a..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.dpi
deleted file mode 100644
index 17a1b30..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.dpi and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hbdb.cdb
deleted file mode 100644
index f5de16f..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hbdb.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hbdb.hdb
deleted file mode 100644
index dcd012e..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hdb
deleted file mode 100644
index eebe31a..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.kpt
deleted file mode 100644
index 9a050cd..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.rrp.hdb b/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.rrp.hdb
deleted file mode 100644
index 899fe82..0000000
Binary files a/1ano/2semestre/lsd/pratica03/AdderDemo/incremental_db/compiled_partitions/AdderDemo.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.asm.rpt b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.asm.rpt
deleted file mode 100644
index 03546e5..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for AdderDemo
-Thu Mar 9 16:51:35 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: AdderDemo.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Thu Mar 9 16:51:35 2023 ;
-; Revision Name ; AdderDemo ;
-; Top-level Entity Name ; AdderDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+----------------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+----------------------------------------------------------------------------------------------------+
-; File Name ;
-+----------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.sof ;
-+----------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------+
-; Assembler Device Options: AdderDemo.sof ;
-+----------------+------------------------+
-; Option ; Setting ;
-+----------------+------------------------+
-; JTAG usercode ; 0x00567C84 ;
-; Checksum ; 0x00567C84 ;
-+----------------+------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Thu Mar 9 16:51:33 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 362 megabytes
- Info: Processing ended: Thu Mar 9 16:51:35 2023
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.cdf b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.cdf
deleted file mode 100644
index 6850020..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.cdf
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition */
-JedecChain;
- FileRevision(JESD32A);
- DefaultMfr(6E);
-
- P ActionCode(Cfg)
- Device PartName(EP4CE115F29) Path("/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/") File("AdderDemo.sof") MfrSpec(OpMask(1));
-
-ChainEnd;
-
-AlteraBegin;
- ChainType(JTAG);
-AlteraEnd;
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.done b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.done
deleted file mode 100644
index 38289f1..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.done
+++ /dev/null
@@ -1 +0,0 @@
-Thu Mar 9 16:51:38 2023
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.eda.rpt b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.eda.rpt
deleted file mode 100644
index 6e82aaa..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.eda.rpt
+++ /dev/null
@@ -1,94 +0,0 @@
-EDA Netlist Writer report for AdderDemo
-Thu Mar 9 16:51:38 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Thu Mar 9 16:51:38 2023 ;
-; Revision Name ; AdderDemo ;
-; Top-level Entity Name ; AdderDemo ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+-----------------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+-----------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/AdderDemo.vho ;
-+-----------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Thu Mar 9 16:51:38 2023
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file AdderDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 612 megabytes
- Info: Processing ended: Thu Mar 9 16:51:38 2023
- Info: Elapsed time: 00:00:00
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.rpt b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.rpt
deleted file mode 100644
index 9d8e6b4..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.rpt
+++ /dev/null
@@ -1,2635 +0,0 @@
-Fitter report for AdderDemo
-Thu Mar 9 16:51:33 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Thu Mar 9 16:51:33 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; AdderDemo ;
-; Top-level Entity Name ; AdderDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 17 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 17 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 34 / 529 ( 6 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.1% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; CLOCK_50 ; PIN_Y2 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
-; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
-; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
-; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
-; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
-; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
-; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[1] ; PIN_M21 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[0] ; PIN_E21 ; QSF Assignment ;
-; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
-; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
-; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 96 ) ; 0.00 % ( 0 / 96 ) ; 0.00 % ( 0 / 96 ) ;
-; -- Achieved ; 0.00 % ( 0 / 96 ) ; 0.00 % ( 0 / 96 ) ; 0.00 % ( 0 / 96 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 86 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.pin.
-
-
-+----------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+------------------------+
-; Total logic elements ; 17 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 17 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 2 ;
-; -- 3 input functions ; 8 ;
-; -- <=2 input functions ; 7 ;
-; -- Register only ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 12 ;
-; -- arithmetic mode ; 5 ;
-; ; ;
-; Total registers* ; 0 / 117,053 ( 0 % ) ;
-; -- Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 2 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 34 / 529 ( 6 % ) ;
-; -- Clock pins ; 0 / 7 ( 0 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.1% / 0.0% / 0.1% ;
-; Peak interconnect usage (total/H/V) ; 0.7% / 0.5% / 1.0% ;
-; Maximum fan-out ; 6 ;
-; Highest non-global fan-out ; 6 ;
-; Total fan-out ; 94 ;
-; Average fan-out ; 0.99 ;
-+---------------------------------------------+------------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 17 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 17 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 2 ; 0 ;
-; -- 3 input functions ; 8 ; 0 ;
-; -- <=2 input functions ; 7 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 12 ; 0 ;
-; -- arithmetic mode ; 5 ; 0 ;
-; ; ; ;
-; Total registers ; 0 ; 0 ;
-; -- Dedicated logic registers ; 0 / 114480 ( 0 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 2 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 34 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 89 ; 5 ;
-; -- Registered Connections ; 0 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 19 ; 0 ;
-; -- Output Ports ; 15 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+-----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; KEY[0] ; M23 ; 6 ; 115 ; 40 ; 7 ; 6 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[10] ; AC24 ; 5 ; 115 ; 4 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[11] ; AB24 ; 5 ; 115 ; 5 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[12] ; AB23 ; 5 ; 115 ; 7 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[13] ; AA24 ; 5 ; 115 ; 9 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[14] ; AA23 ; 5 ; 115 ; 10 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[15] ; AA22 ; 5 ; 115 ; 6 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[16] ; Y24 ; 5 ; 115 ; 13 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[17] ; Y23 ; 5 ; 115 ; 14 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[3] ; AD27 ; 5 ; 115 ; 13 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[4] ; AB27 ; 5 ; 115 ; 18 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[5] ; AC26 ; 5 ; 115 ; 11 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[6] ; AD26 ; 5 ; 115 ; 10 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[7] ; AB26 ; 5 ; 115 ; 15 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[8] ; AC25 ; 5 ; 115 ; 4 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[9] ; AB25 ; 5 ; 115 ; 16 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[10] ; J15 ; 7 ; 60 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[11] ; H16 ; 7 ; 65 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[12] ; J16 ; 7 ; 65 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[13] ; H17 ; 7 ; 67 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[14] ; F15 ; 7 ; 58 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[2] ; E19 ; 7 ; 94 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[3] ; F21 ; 7 ; 107 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[4] ; F18 ; 7 ; 87 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[5] ; E18 ; 7 ; 87 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[6] ; J19 ; 7 ; 72 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[7] ; H19 ; 7 ; 72 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[8] ; J17 ; 7 ; 69 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[9] ; G17 ; 7 ; 83 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 0 / 63 ( 0 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 18 / 65 ( 28 % ) ; 2.5V ; -- ;
-; 6 ; 2 / 58 ( 3 % ) ; 2.5V ; -- ;
-; 7 ; 15 / 72 ( 21 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; SW[15] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA23 ; 280 ; 5 ; SW[14] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA24 ; 279 ; 5 ; SW[13] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; SW[12] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB24 ; 274 ; 5 ; SW[11] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB25 ; 292 ; 5 ; SW[9] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB26 ; 291 ; 5 ; SW[7] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB27 ; 296 ; 5 ; SW[4] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; SW[10] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC25 ; 272 ; 5 ; SW[8] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC26 ; 282 ; 5 ; SW[5] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; SW[6] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD27 ; 286 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 427 ; 7 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E19 ; 421 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; LEDR[14] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; LEDR[9] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G18 ; 452 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; LEDR[11] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; H17 ; 454 ; 7 ; LEDR[13] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; LEDR[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; LEDR[10] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; J16 ; 458 ; 7 ; LEDR[12] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; J17 ; 450 ; 7 ; LEDR[8] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; SW[17] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y24 ; 287 ; 5 ; SW[16] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; LEDR[14] ; Incomplete set of assignments ;
-; LEDR[13] ; Incomplete set of assignments ;
-; LEDR[12] ; Incomplete set of assignments ;
-; LEDR[11] ; Incomplete set of assignments ;
-; LEDR[10] ; Incomplete set of assignments ;
-; LEDR[9] ; Incomplete set of assignments ;
-; LEDR[8] ; Incomplete set of assignments ;
-; LEDR[7] ; Incomplete set of assignments ;
-; LEDR[6] ; Incomplete set of assignments ;
-; LEDR[5] ; Incomplete set of assignments ;
-; LEDR[4] ; Incomplete set of assignments ;
-; LEDR[3] ; Incomplete set of assignments ;
-; LEDR[2] ; Incomplete set of assignments ;
-; LEDR[1] ; Incomplete set of assignments ;
-; LEDR[0] ; Incomplete set of assignments ;
-; SW[9] ; Incomplete set of assignments ;
-; SW[8] ; Incomplete set of assignments ;
-; KEY[0] ; Incomplete set of assignments ;
-; SW[13] ; Incomplete set of assignments ;
-; SW[17] ; Incomplete set of assignments ;
-; SW[12] ; Incomplete set of assignments ;
-; SW[16] ; Incomplete set of assignments ;
-; SW[11] ; Incomplete set of assignments ;
-; SW[15] ; Incomplete set of assignments ;
-; SW[10] ; Incomplete set of assignments ;
-; SW[14] ; Incomplete set of assignments ;
-; SW[7] ; Incomplete set of assignments ;
-; SW[3] ; Incomplete set of assignments ;
-; SW[6] ; Incomplete set of assignments ;
-; SW[2] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-; SW[4] ; Incomplete set of assignments ;
-; SW[1] ; Incomplete set of assignments ;
-; SW[5] ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------+-------------+--------------+
-; |AdderDemo ; 17 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 34 ; 0 ; 17 (0) ; 0 (0) ; 0 (0) ; |AdderDemo ; AdderDemo ; work ;
-; |AddSub4:AddSub4Demo| ; 10 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 0 (0) ; |AdderDemo|AddSub4:AddSub4Demo ; AddSub4 ; work ;
-; |Adder4:Adder4Demo| ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; |AdderDemo|Adder4:Adder4Demo ; Adder4 ; work ;
-; |FullAdder:bit0| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |AdderDemo|Adder4:Adder4Demo|FullAdder:bit0 ; FullAdder ; work ;
-; |FullAdder:bit1| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |AdderDemo|Adder4:Adder4Demo|FullAdder:bit1 ; FullAdder ; work ;
-; |FullAdder:bit2| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |AdderDemo|Adder4:Adder4Demo|FullAdder:bit2 ; FullAdder ; work ;
-; |FullAdder:bit3| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |AdderDemo|Adder4:Adder4Demo|FullAdder:bit3 ; FullAdder ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+----------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+----------+----------+---------------+---------------+-----------------------+-----+------+
-; LEDR[14] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[13] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[12] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[11] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[10] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[9] ; Input ; -- ; -- ; -- ; -- ; -- ;
-; SW[8] ; Input ; -- ; -- ; -- ; -- ; -- ;
-; KEY[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[13] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[17] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[12] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[16] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[11] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[15] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[10] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[14] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[3] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[4] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-+----------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+------------------------------------------------+-------------------+---------+
-; SW[9] ; ; ;
-; SW[8] ; ; ;
-; KEY[0] ; ; ;
-; - AddSub4:AddSub4Demo|Add0~14 ; 1 ; 6 ;
-; - AddSub4:AddSub4Demo|Add0~5 ; 1 ; 6 ;
-; - AddSub4:AddSub4Demo|Add0~0 ; 1 ; 6 ;
-; - AddSub4:AddSub4Demo|Add0~1 ; 1 ; 6 ;
-; - AddSub4:AddSub4Demo|Add0~2 ; 1 ; 6 ;
-; - AddSub4:AddSub4Demo|Add0~3 ; 1 ; 6 ;
-; SW[13] ; ; ;
-; - AddSub4:AddSub4Demo|Add0~0 ; 1 ; 6 ;
-; SW[17] ; ; ;
-; - AddSub4:AddSub4Demo|Add0~12 ; 1 ; 6 ;
-; SW[12] ; ; ;
-; - AddSub4:AddSub4Demo|Add0~1 ; 1 ; 6 ;
-; SW[16] ; ; ;
-; - AddSub4:AddSub4Demo|Add0~10 ; 0 ; 6 ;
-; SW[11] ; ; ;
-; - AddSub4:AddSub4Demo|Add0~2 ; 0 ; 6 ;
-; SW[15] ; ; ;
-; - AddSub4:AddSub4Demo|Add0~8 ; 0 ; 6 ;
-; SW[10] ; ; ;
-; - AddSub4:AddSub4Demo|Add0~3 ; 0 ; 6 ;
-; SW[14] ; ; ;
-; - AddSub4:AddSub4Demo|Add0~6 ; 1 ; 6 ;
-; SW[7] ; ; ;
-; - Adder4:Adder4Demo|FullAdder:bit3|cout~0 ; 0 ; 6 ;
-; - Adder4:Adder4Demo|FullAdder:bit3|s ; 0 ; 6 ;
-; SW[3] ; ; ;
-; - Adder4:Adder4Demo|FullAdder:bit3|cout~0 ; 0 ; 6 ;
-; - Adder4:Adder4Demo|FullAdder:bit3|s ; 0 ; 6 ;
-; SW[6] ; ; ;
-; - Adder4:Adder4Demo|FullAdder:bit2|cout~0 ; 0 ; 6 ;
-; - Adder4:Adder4Demo|FullAdder:bit2|s~0 ; 0 ; 6 ;
-; SW[2] ; ; ;
-; - Adder4:Adder4Demo|FullAdder:bit2|cout~0 ; 0 ; 6 ;
-; - Adder4:Adder4Demo|FullAdder:bit2|s~0 ; 0 ; 6 ;
-; SW[0] ; ; ;
-; - Adder4:Adder4Demo|FullAdder:bit1|cout~0 ; 0 ; 6 ;
-; - Adder4:Adder4Demo|FullAdder:bit1|s~0 ; 0 ; 6 ;
-; - Adder4:Adder4Demo|FullAdder:bit0|s~0 ; 0 ; 6 ;
-; SW[4] ; ; ;
-; - Adder4:Adder4Demo|FullAdder:bit1|cout~0 ; 0 ; 6 ;
-; - Adder4:Adder4Demo|FullAdder:bit1|s~0 ; 0 ; 6 ;
-; - Adder4:Adder4Demo|FullAdder:bit0|s~0 ; 0 ; 6 ;
-; SW[1] ; ; ;
-; - Adder4:Adder4Demo|FullAdder:bit1|cout~0 ; 0 ; 6 ;
-; - Adder4:Adder4Demo|FullAdder:bit1|s~0 ; 0 ; 6 ;
-; SW[5] ; ; ;
-; - Adder4:Adder4Demo|FullAdder:bit1|cout~0 ; 0 ; 6 ;
-; - Adder4:Adder4Demo|FullAdder:bit1|s~0 ; 0 ; 6 ;
-+------------------------------------------------+-------------------+---------+
-
-
-+------------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+------------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+------------------------+
-; Block interconnects ; 27 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 26 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 94 / 209,544 ( < 1 % ) ;
-; Direct links ; 0 / 342,891 ( 0 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 6 / 119,088 ( < 1 % ) ;
-; R24 interconnects ; 16 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 46 / 289,782 ( < 1 % ) ;
-+-----------------------+------------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 8.50) ; Number of LABs (Total = 2) ;
-+--------------------------------------------+-----------------------------+
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 1 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 1 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-+--------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 8.00) ; Number of LABs (Total = 2) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 1 ;
-; 8 ; 0 ;
-; 9 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 2) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 2 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 8.50) ; Number of LABs (Total = 2) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-; 9 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 34 ; 34 ; 0 ; 0 ; 34 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 ; 0 ; 0 ; 0 ; 19 ; 15 ; 0 ; 19 ; 0 ; 0 ; 15 ; 0 ; 34 ; 34 ; 34 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 34 ; 0 ; 0 ; 34 ; 34 ; 0 ; 0 ; 34 ; 34 ; 34 ; 34 ; 34 ; 34 ; 19 ; 34 ; 34 ; 34 ; 15 ; 19 ; 34 ; 15 ; 34 ; 34 ; 19 ; 34 ; 0 ; 0 ; 0 ; 34 ; 34 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; LEDR[14] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[13] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[12] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[11] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[10] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[9] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[9] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[13] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[17] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[12] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[16] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[11] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[15] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[10] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[14] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "AdderDemo"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'AdderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 492 warnings
- Info: Peak virtual memory: 1151 megabytes
- Info: Processing ended: Thu Mar 9 16:51:33 2023
- Info: Elapsed time: 00:00:07
- Info: Total CPU time (on all processors): 00:00:11
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.smsg b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.summary b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.summary
deleted file mode 100644
index a7fdae2..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Thu Mar 9 16:51:33 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : AdderDemo
-Top-level Entity Name : AdderDemo
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 17 / 114,480 ( < 1 % )
- Total combinational functions : 17 / 114,480 ( < 1 % )
- Dedicated logic registers : 0 / 114,480 ( 0 % )
-Total registers : 0
-Total pins : 34 / 529 ( 6 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.flow.rpt b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.flow.rpt
deleted file mode 100644
index 207ee32..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.flow.rpt
+++ /dev/null
@@ -1,134 +0,0 @@
-Flow report for AdderDemo
-Thu Mar 9 16:51:38 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Thu Mar 9 16:51:38 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; AdderDemo ;
-; Top-level Entity Name ; AdderDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 17 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 17 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 34 / 529 ( 6 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/09/2023 16:51:19 ;
-; Main task ; Compilation ;
-; Revision Name ; AdderDemo ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 198516037997543.167838067907393 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 431 MB ; 00:00:16 ;
-; Fitter ; 00:00:07 ; 1.0 ; 1151 MB ; 00:00:11 ;
-; Assembler ; 00:00:02 ; 1.0 ; 362 MB ; 00:00:02 ;
-; Timing Analyzer ; 00:00:01 ; 1.0 ; 535 MB ; 00:00:01 ;
-; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 612 MB ; 00:00:00 ;
-; Total ; 00:00:17 ; -- ; -- ; 00:00:30 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo
-quartus_fit --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo
-quartus_asm --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo
-quartus_sta AdderDemo -c AdderDemo
-quartus_eda --read_settings_files=off --write_settings_files=off AdderDemo -c AdderDemo
-
-
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.jdi b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.jdi
deleted file mode 100644
index 9b23781..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.map.rpt b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.map.rpt
deleted file mode 100644
index 4719ca9..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.map.rpt
+++ /dev/null
@@ -1,319 +0,0 @@
-Analysis & Synthesis report for AdderDemo
-Thu Mar 9 16:51:26 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Post-Synthesis Netlist Statistics for Top Partition
- 10. Elapsed Time Per Partition
- 11. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Thu Mar 9 16:51:26 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; AdderDemo ;
-; Top-level Entity Name ; AdderDemo ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 17 ;
-; Total combinational functions ; 17 ;
-; Dedicated logic registers ; 0 ;
-; Total registers ; 0 ;
-; Total pins ; 34 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; AdderDemo ; AdderDemo ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------+---------+
-; FullAdder.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd ; ;
-; Adder4.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd ; ;
-; AdderDemo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf ; ;
-; AddSub4.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd ; ;
-+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------+---------+
-
-
-+------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+--------------+
-; Resource ; Usage ;
-+---------------------------------------------+--------------+
-; Estimated Total logic elements ; 17 ;
-; ; ;
-; Total combinational functions ; 17 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 2 ;
-; -- 3 input functions ; 8 ;
-; -- <=2 input functions ; 7 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 12 ;
-; -- arithmetic mode ; 5 ;
-; ; ;
-; Total registers ; 0 ;
-; -- Dedicated logic registers ; 0 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 34 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; KEY[0]~input ;
-; Maximum fan-out ; 6 ;
-; Total fan-out ; 89 ;
-; Average fan-out ; 1.05 ;
-+---------------------------------------------+--------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------+-------------+--------------+
-; |AdderDemo ; 17 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 34 ; 0 ; |AdderDemo ; AdderDemo ; work ;
-; |AddSub4:AddSub4Demo| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AdderDemo|AddSub4:AddSub4Demo ; AddSub4 ; work ;
-; |Adder4:Adder4Demo| ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AdderDemo|Adder4:Adder4Demo ; Adder4 ; work ;
-; |FullAdder:bit0| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AdderDemo|Adder4:Adder4Demo|FullAdder:bit0 ; FullAdder ; work ;
-; |FullAdder:bit1| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AdderDemo|Adder4:Adder4Demo|FullAdder:bit1 ; FullAdder ; work ;
-; |FullAdder:bit2| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AdderDemo|Adder4:Adder4Demo|FullAdder:bit2 ; FullAdder ; work ;
-; |FullAdder:bit3| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AdderDemo|Adder4:Adder4Demo|FullAdder:bit3 ; FullAdder ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 0 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 34 ;
-; cycloneiii_lcell_comb ; 18 ;
-; arith ; 5 ;
-; 2 data inputs ; 1 ;
-; 3 data inputs ; 4 ;
-; normal ; 13 ;
-; 0 data inputs ; 1 ;
-; 1 data inputs ; 1 ;
-; 2 data inputs ; 5 ;
-; 3 data inputs ; 4 ;
-; 4 data inputs ; 2 ;
-; ; ;
-; Max LUT depth ; 3.00 ;
-; Average LUT depth ; 2.09 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Thu Mar 9 16:51:19 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 2 design units, including 1 entities, in source file FullAdder.vhd
- Info (12022): Found design unit 1: FullAdder-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd Line: 12
- Info (12023): Found entity 1: FullAdder File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd Line: 4
-Info (12021): Found 2 design units, including 1 entities, in source file Adder4.vhd
- Info (12022): Found design unit 1: Adder4-Structural File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd Line: 14
- Info (12023): Found entity 1: Adder4 File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd Line: 4
-Info (12021): Found 1 design units, including 1 entities, in source file AdderDemo.bdf
- Info (12023): Found entity 1: AdderDemo
-Info (12021): Found 2 design units, including 1 entities, in source file AddSub4.vhd
- Info (12022): Found design unit 1: AddSub4-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd Line: 29
- Info (12023): Found entity 1: AddSub4 File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd Line: 5
-Info (12127): Elaborating entity "AdderDemo" for the top level hierarchy
-Warning (275008): Primitive "GND" of instance "Ground2" not used
-Info (12128): Elaborating entity "Adder4" for hierarchy "Adder4:Adder4Demo"
-Info (12129): Elaborating entity "FullAdder" using architecture "A:behavioral" for hierarchy "Adder4:Adder4Demo|FullAdder:bit0" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd Line: 17
-Info (12128): Elaborating entity "AddSub4" for hierarchy "AddSub4:AddSub4Demo"
-Warning (13024): Output pins are stuck at VCC or GND
- Warning (13410): Pin "LEDR[9]" is stuck at GND
- Warning (13410): Pin "LEDR[8]" is stuck at GND
- Warning (13410): Pin "LEDR[7]" is stuck at GND
- Warning (13410): Pin "LEDR[6]" is stuck at GND
- Warning (13410): Pin "LEDR[5]" is stuck at GND
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 2 input pin(s) that do not drive logic
- Warning (15610): No output dependent on input pin "SW[9]"
- Warning (15610): No output dependent on input pin "SW[8]"
-Info (21057): Implemented 51 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 19 input pins
- Info (21059): Implemented 15 output pins
- Info (21061): Implemented 17 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 11 warnings
- Info: Peak virtual memory: 431 megabytes
- Info: Processing ended: Thu Mar 9 16:51:26 2023
- Info: Elapsed time: 00:00:07
- Info: Total CPU time (on all processors): 00:00:16
-
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.map.summary b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.map.summary
deleted file mode 100644
index db4174d..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Thu Mar 9 16:51:26 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : AdderDemo
-Top-level Entity Name : AdderDemo
-Family : Cyclone IV E
-Total logic elements : 17
- Total combinational functions : 17
- Dedicated logic registers : 0
-Total registers : 0
-Total pins : 34
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.pin b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.pin
deleted file mode 100644
index 5c9cdae..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "AdderDemo" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-SW[15] : AA22 : input : 2.5 V : : 5 : Y
-SW[14] : AA23 : input : 2.5 V : : 5 : Y
-SW[13] : AA24 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-SW[12] : AB23 : input : 2.5 V : : 5 : Y
-SW[11] : AB24 : input : 2.5 V : : 5 : Y
-SW[9] : AB25 : input : 2.5 V : : 5 : Y
-SW[7] : AB26 : input : 2.5 V : : 5 : Y
-SW[4] : AB27 : input : 2.5 V : : 5 : Y
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-SW[10] : AC24 : input : 2.5 V : : 5 : Y
-SW[8] : AC25 : input : 2.5 V : : 5 : Y
-SW[5] : AC26 : input : 2.5 V : : 5 : Y
-SW[2] : AC27 : input : 2.5 V : : 5 : Y
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-SW[6] : AD26 : input : 2.5 V : : 5 : Y
-SW[3] : AD27 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
-LEDR[5] : E18 : output : 2.5 V : : 7 : Y
-LEDR[2] : E19 : output : 2.5 V : : 7 : Y
-VCCIO7 : E20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
-VCCIO7 : E23 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-LEDR[14] : F15 : output : 2.5 V : : 7 : Y
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-LEDR[4] : F18 : output : 2.5 V : : 7 : Y
-LEDR[1] : F19 : output : 2.5 V : : 7 : Y
-GND : F20 : gnd : : : :
-LEDR[3] : F21 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-LEDR[9] : G17 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
-LEDR[0] : G19 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-LEDR[11] : H16 : output : 2.5 V : : 7 : Y
-LEDR[13] : H17 : output : 2.5 V : : 7 : Y
-VCCIO7 : H18 : power : : 2.5V : 7 :
-LEDR[7] : H19 : output : 2.5 V : : 7 : Y
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-LEDR[10] : J15 : output : 2.5 V : : 7 : Y
-LEDR[12] : J16 : output : 2.5 V : : 7 : Y
-LEDR[8] : J17 : output : 2.5 V : : 7 : Y
-GND : J18 : gnd : : : :
-LEDR[6] : J19 : output : 2.5 V : : 7 : Y
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6 :
-MSEL2 : M22 : : : : 6 :
-KEY[0] : M23 : input : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-GND+ : Y2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-SW[17] : Y23 : input : 2.5 V : : 5 : Y
-SW[16] : Y24 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.sld b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.sta.rpt b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.sta.rpt
deleted file mode 100644
index 146c95e..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.sta.rpt
+++ /dev/null
@@ -1,552 +0,0 @@
-Timing Analyzer report for AdderDemo
-Thu Mar 9 16:51:37 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Unconstrained Input Ports
- 37. Unconstrained Output Ports
- 38. Unconstrained Input Ports
- 39. Unconstrained Output Ports
- 40. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; AdderDemo ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.3% ;
-+----------------------------+-------------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDR[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[13] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[17] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[12] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[16] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[11] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[15] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[10] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[14] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ;
-; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ;
-; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ;
-; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 17 ; 17 ;
-; Unconstrained Input Port Paths ; 61 ; 61 ;
-; Unconstrained Output Ports ; 10 ; 10 ;
-; Unconstrained Output Port Paths ; 61 ; 61 ;
-+---------------------------------+-------+------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[16] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[17] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[13] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[14] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[16] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[17] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[13] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[14] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Thu Mar 9 16:51:36 2023
-Info: Command: quartus_sta AdderDemo -c AdderDemo
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'AdderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 535 megabytes
- Info: Processing ended: Thu Mar 9 16:51:37 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.sta.summary b/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.sta.summary
deleted file mode 100644
index aa5b327..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/AdderDemo.sft b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/AdderDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/AdderDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/AdderDemo.vho b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/AdderDemo.vho
deleted file mode 100644
index c10d4a8..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/AdderDemo.vho
+++ /dev/null
@@ -1,914 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/09/2023 16:51:38"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY AdderDemo IS
- PORT (
- LEDR : OUT std_logic_vector(14 DOWNTO 0);
- SW : IN std_logic_vector(17 DOWNTO 0);
- KEY : IN std_logic_vector(0 DOWNTO 0)
- );
-END AdderDemo;
-
--- Design Ports Information
--- LEDR[14] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[13] => Location: PIN_H17, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[12] => Location: PIN_J16, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[11] => Location: PIN_H16, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[10] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[9] => Location: PIN_G17, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[8] => Location: PIN_J17, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[7] => Location: PIN_H19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[6] => Location: PIN_J19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[5] => Location: PIN_E18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[4] => Location: PIN_F18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- SW[9] => Location: PIN_AB25, I/O Standard: 2.5 V, Current Strength: Default
--- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[13] => Location: PIN_AA24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[17] => Location: PIN_Y23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[12] => Location: PIN_AB23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[16] => Location: PIN_Y24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[11] => Location: PIN_AB24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[15] => Location: PIN_AA22, I/O Standard: 2.5 V, Current Strength: Default
--- SW[10] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[14] => Location: PIN_AA23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF AdderDemo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDR : std_logic_vector(14 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(17 DOWNTO 0);
-SIGNAL ww_KEY : std_logic_vector(0 DOWNTO 0);
-SIGNAL \SW[9]~input_o\ : std_logic;
-SIGNAL \SW[8]~input_o\ : std_logic;
-SIGNAL \LEDR[14]~output_o\ : std_logic;
-SIGNAL \LEDR[13]~output_o\ : std_logic;
-SIGNAL \LEDR[12]~output_o\ : std_logic;
-SIGNAL \LEDR[11]~output_o\ : std_logic;
-SIGNAL \LEDR[10]~output_o\ : std_logic;
-SIGNAL \LEDR[9]~output_o\ : std_logic;
-SIGNAL \LEDR[8]~output_o\ : std_logic;
-SIGNAL \LEDR[7]~output_o\ : std_logic;
-SIGNAL \LEDR[6]~output_o\ : std_logic;
-SIGNAL \LEDR[5]~output_o\ : std_logic;
-SIGNAL \LEDR[4]~output_o\ : std_logic;
-SIGNAL \LEDR[3]~output_o\ : std_logic;
-SIGNAL \LEDR[2]~output_o\ : std_logic;
-SIGNAL \LEDR[1]~output_o\ : std_logic;
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \KEY[0]~input_o\ : std_logic;
-SIGNAL \SW[17]~input_o\ : std_logic;
-SIGNAL \SW[13]~input_o\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~0_combout\ : std_logic;
-SIGNAL \SW[12]~input_o\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~1_combout\ : std_logic;
-SIGNAL \SW[16]~input_o\ : std_logic;
-SIGNAL \SW[11]~input_o\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~2_combout\ : std_logic;
-SIGNAL \SW[15]~input_o\ : std_logic;
-SIGNAL \SW[10]~input_o\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~3_combout\ : std_logic;
-SIGNAL \SW[14]~input_o\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~5_cout\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~7\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~9\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~11\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~13\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~14_combout\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~12_combout\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~10_combout\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~8_combout\ : std_logic;
-SIGNAL \AddSub4Demo|Add0~6_combout\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \SW[5]~input_o\ : std_logic;
-SIGNAL \SW[4]~input_o\ : std_logic;
-SIGNAL \Adder4Demo|bit1|cout~0_combout\ : std_logic;
-SIGNAL \SW[6]~input_o\ : std_logic;
-SIGNAL \SW[2]~input_o\ : std_logic;
-SIGNAL \Adder4Demo|bit2|cout~0_combout\ : std_logic;
-SIGNAL \SW[3]~input_o\ : std_logic;
-SIGNAL \SW[7]~input_o\ : std_logic;
-SIGNAL \Adder4Demo|bit3|cout~0_combout\ : std_logic;
-SIGNAL \Adder4Demo|bit3|s~combout\ : std_logic;
-SIGNAL \Adder4Demo|bit2|s~0_combout\ : std_logic;
-SIGNAL \Adder4Demo|bit1|s~0_combout\ : std_logic;
-SIGNAL \Adder4Demo|bit0|s~0_combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-LEDR <= ww_LEDR;
-ww_SW <= SW;
-ww_KEY <= KEY;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X58_Y73_N2
-\LEDR[14]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \AddSub4Demo|Add0~14_combout\,
- devoe => ww_devoe,
- o => \LEDR[14]~output_o\);
-
--- Location: IOOBUF_X67_Y73_N9
-\LEDR[13]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \AddSub4Demo|Add0~12_combout\,
- devoe => ww_devoe,
- o => \LEDR[13]~output_o\);
-
--- Location: IOOBUF_X65_Y73_N16
-\LEDR[12]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \AddSub4Demo|Add0~10_combout\,
- devoe => ww_devoe,
- o => \LEDR[12]~output_o\);
-
--- Location: IOOBUF_X65_Y73_N23
-\LEDR[11]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \AddSub4Demo|Add0~8_combout\,
- devoe => ww_devoe,
- o => \LEDR[11]~output_o\);
-
--- Location: IOOBUF_X60_Y73_N23
-\LEDR[10]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \AddSub4Demo|Add0~6_combout\,
- devoe => ww_devoe,
- o => \LEDR[10]~output_o\);
-
--- Location: IOOBUF_X83_Y73_N23
-\LEDR[9]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => GND,
- devoe => ww_devoe,
- o => \LEDR[9]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N2
-\LEDR[8]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => GND,
- devoe => ww_devoe,
- o => \LEDR[8]~output_o\);
-
--- Location: IOOBUF_X72_Y73_N2
-\LEDR[7]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => GND,
- devoe => ww_devoe,
- o => \LEDR[7]~output_o\);
-
--- Location: IOOBUF_X72_Y73_N9
-\LEDR[6]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => GND,
- devoe => ww_devoe,
- o => \LEDR[6]~output_o\);
-
--- Location: IOOBUF_X87_Y73_N9
-\LEDR[5]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => GND,
- devoe => ww_devoe,
- o => \LEDR[5]~output_o\);
-
--- Location: IOOBUF_X87_Y73_N16
-\LEDR[4]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Adder4Demo|bit3|cout~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[4]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N16
-\LEDR[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Adder4Demo|bit3|s~combout\,
- devoe => ww_devoe,
- o => \LEDR[3]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N9
-\LEDR[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Adder4Demo|bit2|s~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[2]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N2
-\LEDR[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Adder4Demo|bit1|s~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[1]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N16
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Adder4Demo|bit0|s~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
--- Location: IOIBUF_X115_Y40_N8
-\KEY[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY(0),
- o => \KEY[0]~input_o\);
-
--- Location: IOIBUF_X115_Y14_N8
-\SW[17]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(17),
- o => \SW[17]~input_o\);
-
--- Location: IOIBUF_X115_Y9_N22
-\SW[13]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(13),
- o => \SW[13]~input_o\);
-
--- Location: LCCOMB_X114_Y13_N8
-\AddSub4Demo|Add0~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \AddSub4Demo|Add0~0_combout\ = \SW[13]~input_o\ $ (\KEY[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \SW[13]~input_o\,
- datad => \KEY[0]~input_o\,
- combout => \AddSub4Demo|Add0~0_combout\);
-
--- Location: IOIBUF_X115_Y7_N15
-\SW[12]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(12),
- o => \SW[12]~input_o\);
-
--- Location: LCCOMB_X114_Y13_N10
-\AddSub4Demo|Add0~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \AddSub4Demo|Add0~1_combout\ = \SW[12]~input_o\ $ (\KEY[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011001111001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[12]~input_o\,
- datad => \KEY[0]~input_o\,
- combout => \AddSub4Demo|Add0~1_combout\);
-
--- Location: IOIBUF_X115_Y13_N1
-\SW[16]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(16),
- o => \SW[16]~input_o\);
-
--- Location: IOIBUF_X115_Y5_N15
-\SW[11]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(11),
- o => \SW[11]~input_o\);
-
--- Location: LCCOMB_X114_Y13_N12
-\AddSub4Demo|Add0~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \AddSub4Demo|Add0~2_combout\ = \SW[11]~input_o\ $ (\KEY[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011001111001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \SW[11]~input_o\,
- datad => \KEY[0]~input_o\,
- combout => \AddSub4Demo|Add0~2_combout\);
-
--- Location: IOIBUF_X115_Y6_N15
-\SW[15]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(15),
- o => \SW[15]~input_o\);
-
--- Location: IOIBUF_X115_Y4_N15
-\SW[10]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(10),
- o => \SW[10]~input_o\);
-
--- Location: LCCOMB_X114_Y13_N30
-\AddSub4Demo|Add0~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \AddSub4Demo|Add0~3_combout\ = \SW[10]~input_o\ $ (\KEY[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \SW[10]~input_o\,
- datad => \KEY[0]~input_o\,
- combout => \AddSub4Demo|Add0~3_combout\);
-
--- Location: IOIBUF_X115_Y10_N8
-\SW[14]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(14),
- o => \SW[14]~input_o\);
-
--- Location: LCCOMB_X114_Y13_N18
-\AddSub4Demo|Add0~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \AddSub4Demo|Add0~5_cout\ = CARRY(\KEY[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000010101010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \KEY[0]~input_o\,
- datad => VCC,
- cout => \AddSub4Demo|Add0~5_cout\);
-
--- Location: LCCOMB_X114_Y13_N20
-\AddSub4Demo|Add0~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \AddSub4Demo|Add0~6_combout\ = (\AddSub4Demo|Add0~3_combout\ & ((\SW[14]~input_o\ & (\AddSub4Demo|Add0~5_cout\ & VCC)) # (!\SW[14]~input_o\ & (!\AddSub4Demo|Add0~5_cout\)))) # (!\AddSub4Demo|Add0~3_combout\ & ((\SW[14]~input_o\ &
--- (!\AddSub4Demo|Add0~5_cout\)) # (!\SW[14]~input_o\ & ((\AddSub4Demo|Add0~5_cout\) # (GND)))))
--- \AddSub4Demo|Add0~7\ = CARRY((\AddSub4Demo|Add0~3_combout\ & (!\SW[14]~input_o\ & !\AddSub4Demo|Add0~5_cout\)) # (!\AddSub4Demo|Add0~3_combout\ & ((!\AddSub4Demo|Add0~5_cout\) # (!\SW[14]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \AddSub4Demo|Add0~3_combout\,
- datab => \SW[14]~input_o\,
- datad => VCC,
- cin => \AddSub4Demo|Add0~5_cout\,
- combout => \AddSub4Demo|Add0~6_combout\,
- cout => \AddSub4Demo|Add0~7\);
-
--- Location: LCCOMB_X114_Y13_N22
-\AddSub4Demo|Add0~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \AddSub4Demo|Add0~8_combout\ = ((\AddSub4Demo|Add0~2_combout\ $ (\SW[15]~input_o\ $ (!\AddSub4Demo|Add0~7\)))) # (GND)
--- \AddSub4Demo|Add0~9\ = CARRY((\AddSub4Demo|Add0~2_combout\ & ((\SW[15]~input_o\) # (!\AddSub4Demo|Add0~7\))) # (!\AddSub4Demo|Add0~2_combout\ & (\SW[15]~input_o\ & !\AddSub4Demo|Add0~7\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \AddSub4Demo|Add0~2_combout\,
- datab => \SW[15]~input_o\,
- datad => VCC,
- cin => \AddSub4Demo|Add0~7\,
- combout => \AddSub4Demo|Add0~8_combout\,
- cout => \AddSub4Demo|Add0~9\);
-
--- Location: LCCOMB_X114_Y13_N24
-\AddSub4Demo|Add0~10\ : cycloneive_lcell_comb
--- Equation(s):
--- \AddSub4Demo|Add0~10_combout\ = (\AddSub4Demo|Add0~1_combout\ & ((\SW[16]~input_o\ & (\AddSub4Demo|Add0~9\ & VCC)) # (!\SW[16]~input_o\ & (!\AddSub4Demo|Add0~9\)))) # (!\AddSub4Demo|Add0~1_combout\ & ((\SW[16]~input_o\ & (!\AddSub4Demo|Add0~9\)) #
--- (!\SW[16]~input_o\ & ((\AddSub4Demo|Add0~9\) # (GND)))))
--- \AddSub4Demo|Add0~11\ = CARRY((\AddSub4Demo|Add0~1_combout\ & (!\SW[16]~input_o\ & !\AddSub4Demo|Add0~9\)) # (!\AddSub4Demo|Add0~1_combout\ & ((!\AddSub4Demo|Add0~9\) # (!\SW[16]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \AddSub4Demo|Add0~1_combout\,
- datab => \SW[16]~input_o\,
- datad => VCC,
- cin => \AddSub4Demo|Add0~9\,
- combout => \AddSub4Demo|Add0~10_combout\,
- cout => \AddSub4Demo|Add0~11\);
-
--- Location: LCCOMB_X114_Y13_N26
-\AddSub4Demo|Add0~12\ : cycloneive_lcell_comb
--- Equation(s):
--- \AddSub4Demo|Add0~12_combout\ = ((\SW[17]~input_o\ $ (\AddSub4Demo|Add0~0_combout\ $ (!\AddSub4Demo|Add0~11\)))) # (GND)
--- \AddSub4Demo|Add0~13\ = CARRY((\SW[17]~input_o\ & ((\AddSub4Demo|Add0~0_combout\) # (!\AddSub4Demo|Add0~11\))) # (!\SW[17]~input_o\ & (\AddSub4Demo|Add0~0_combout\ & !\AddSub4Demo|Add0~11\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[17]~input_o\,
- datab => \AddSub4Demo|Add0~0_combout\,
- datad => VCC,
- cin => \AddSub4Demo|Add0~11\,
- combout => \AddSub4Demo|Add0~12_combout\,
- cout => \AddSub4Demo|Add0~13\);
-
--- Location: LCCOMB_X114_Y13_N28
-\AddSub4Demo|Add0~14\ : cycloneive_lcell_comb
--- Equation(s):
--- \AddSub4Demo|Add0~14_combout\ = \AddSub4Demo|Add0~13\ $ (\KEY[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000111111110000",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datad => \KEY[0]~input_o\,
- cin => \AddSub4Demo|Add0~13\,
- combout => \AddSub4Demo|Add0~14_combout\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: IOIBUF_X115_Y11_N8
-\SW[5]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(5),
- o => \SW[5]~input_o\);
-
--- Location: IOIBUF_X115_Y18_N8
-\SW[4]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(4),
- o => \SW[4]~input_o\);
-
--- Location: LCCOMB_X114_Y15_N16
-\Adder4Demo|bit1|cout~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit1|cout~0_combout\ = (\SW[1]~input_o\ & ((\SW[5]~input_o\) # ((\SW[0]~input_o\ & \SW[4]~input_o\)))) # (!\SW[1]~input_o\ & (\SW[0]~input_o\ & (\SW[5]~input_o\ & \SW[4]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1110100010100000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[1]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[5]~input_o\,
- datad => \SW[4]~input_o\,
- combout => \Adder4Demo|bit1|cout~0_combout\);
-
--- Location: IOIBUF_X115_Y10_N1
-\SW[6]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(6),
- o => \SW[6]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N8
-\SW[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(2),
- o => \SW[2]~input_o\);
-
--- Location: LCCOMB_X114_Y15_N26
-\Adder4Demo|bit2|cout~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit2|cout~0_combout\ = (\Adder4Demo|bit1|cout~0_combout\ & ((\SW[6]~input_o\) # (\SW[2]~input_o\))) # (!\Adder4Demo|bit1|cout~0_combout\ & (\SW[6]~input_o\ & \SW[2]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111110011000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \Adder4Demo|bit1|cout~0_combout\,
- datac => \SW[6]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \Adder4Demo|bit2|cout~0_combout\);
-
--- Location: IOIBUF_X115_Y13_N8
-\SW[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(3),
- o => \SW[3]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N1
-\SW[7]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(7),
- o => \SW[7]~input_o\);
-
--- Location: LCCOMB_X114_Y15_N28
-\Adder4Demo|bit3|cout~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit3|cout~0_combout\ = (\Adder4Demo|bit2|cout~0_combout\ & ((\SW[3]~input_o\) # (\SW[7]~input_o\))) # (!\Adder4Demo|bit2|cout~0_combout\ & (\SW[3]~input_o\ & \SW[7]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111101010100000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Adder4Demo|bit2|cout~0_combout\,
- datac => \SW[3]~input_o\,
- datad => \SW[7]~input_o\,
- combout => \Adder4Demo|bit3|cout~0_combout\);
-
--- Location: LCCOMB_X114_Y15_N22
-\Adder4Demo|bit3|s\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit3|s~combout\ = \Adder4Demo|bit2|cout~0_combout\ $ (\SW[3]~input_o\ $ (\SW[7]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010010101011010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Adder4Demo|bit2|cout~0_combout\,
- datac => \SW[3]~input_o\,
- datad => \SW[7]~input_o\,
- combout => \Adder4Demo|bit3|s~combout\);
-
--- Location: LCCOMB_X114_Y15_N24
-\Adder4Demo|bit2|s~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit2|s~0_combout\ = \Adder4Demo|bit1|cout~0_combout\ $ (\SW[6]~input_o\ $ (\SW[2]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100111100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \Adder4Demo|bit1|cout~0_combout\,
- datac => \SW[6]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \Adder4Demo|bit2|s~0_combout\);
-
--- Location: LCCOMB_X114_Y15_N10
-\Adder4Demo|bit1|s~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit1|s~0_combout\ = \SW[1]~input_o\ $ (\SW[5]~input_o\ $ (((\SW[0]~input_o\ & \SW[4]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011001011010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[1]~input_o\,
- datab => \SW[0]~input_o\,
- datac => \SW[5]~input_o\,
- datad => \SW[4]~input_o\,
- combout => \Adder4Demo|bit1|s~0_combout\);
-
--- Location: LCCOMB_X114_Y15_N4
-\Adder4Demo|bit0|s~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit0|s~0_combout\ = \SW[0]~input_o\ $ (\SW[4]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \SW[0]~input_o\,
- datad => \SW[4]~input_o\,
- combout => \Adder4Demo|bit0|s~0_combout\);
-
--- Location: IOIBUF_X115_Y16_N8
-\SW[9]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(9),
- o => \SW[9]~input_o\);
-
--- Location: IOIBUF_X115_Y4_N22
-\SW[8]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(8),
- o => \SW[8]~input_o\);
-
-ww_LEDR(14) <= \LEDR[14]~output_o\;
-
-ww_LEDR(13) <= \LEDR[13]~output_o\;
-
-ww_LEDR(12) <= \LEDR[12]~output_o\;
-
-ww_LEDR(11) <= \LEDR[11]~output_o\;
-
-ww_LEDR(10) <= \LEDR[10]~output_o\;
-
-ww_LEDR(9) <= \LEDR[9]~output_o\;
-
-ww_LEDR(8) <= \LEDR[8]~output_o\;
-
-ww_LEDR(7) <= \LEDR[7]~output_o\;
-
-ww_LEDR(6) <= \LEDR[6]~output_o\;
-
-ww_LEDR(5) <= \LEDR[5]~output_o\;
-
-ww_LEDR(4) <= \LEDR[4]~output_o\;
-
-ww_LEDR(3) <= \LEDR[3]~output_o\;
-
-ww_LEDR(2) <= \LEDR[2]~output_o\;
-
-ww_LEDR(1) <= \LEDR[1]~output_o\;
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/AdderDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/AdderDemo_modelsim.xrf
deleted file mode 100644
index 555e7bc..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/modelsim/AdderDemo_modelsim.xrf
+++ /dev/null
@@ -1,64 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vwf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cbx.xml
-design_name = hard_block
-design_name = AdderDemo
-instance = comp, \LEDR[14]~output\, LEDR[14]~output, AdderDemo, 1
-instance = comp, \LEDR[13]~output\, LEDR[13]~output, AdderDemo, 1
-instance = comp, \LEDR[12]~output\, LEDR[12]~output, AdderDemo, 1
-instance = comp, \LEDR[11]~output\, LEDR[11]~output, AdderDemo, 1
-instance = comp, \LEDR[10]~output\, LEDR[10]~output, AdderDemo, 1
-instance = comp, \LEDR[9]~output\, LEDR[9]~output, AdderDemo, 1
-instance = comp, \LEDR[8]~output\, LEDR[8]~output, AdderDemo, 1
-instance = comp, \LEDR[7]~output\, LEDR[7]~output, AdderDemo, 1
-instance = comp, \LEDR[6]~output\, LEDR[6]~output, AdderDemo, 1
-instance = comp, \LEDR[5]~output\, LEDR[5]~output, AdderDemo, 1
-instance = comp, \LEDR[4]~output\, LEDR[4]~output, AdderDemo, 1
-instance = comp, \LEDR[3]~output\, LEDR[3]~output, AdderDemo, 1
-instance = comp, \LEDR[2]~output\, LEDR[2]~output, AdderDemo, 1
-instance = comp, \LEDR[1]~output\, LEDR[1]~output, AdderDemo, 1
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, AdderDemo, 1
-instance = comp, \KEY[0]~input\, KEY[0]~input, AdderDemo, 1
-instance = comp, \SW[17]~input\, SW[17]~input, AdderDemo, 1
-instance = comp, \SW[13]~input\, SW[13]~input, AdderDemo, 1
-instance = comp, \AddSub4Demo|Add0~0\, AddSub4Demo|Add0~0, AdderDemo, 1
-instance = comp, \SW[12]~input\, SW[12]~input, AdderDemo, 1
-instance = comp, \AddSub4Demo|Add0~1\, AddSub4Demo|Add0~1, AdderDemo, 1
-instance = comp, \SW[16]~input\, SW[16]~input, AdderDemo, 1
-instance = comp, \SW[11]~input\, SW[11]~input, AdderDemo, 1
-instance = comp, \AddSub4Demo|Add0~2\, AddSub4Demo|Add0~2, AdderDemo, 1
-instance = comp, \SW[15]~input\, SW[15]~input, AdderDemo, 1
-instance = comp, \SW[10]~input\, SW[10]~input, AdderDemo, 1
-instance = comp, \AddSub4Demo|Add0~3\, AddSub4Demo|Add0~3, AdderDemo, 1
-instance = comp, \SW[14]~input\, SW[14]~input, AdderDemo, 1
-instance = comp, \AddSub4Demo|Add0~5\, AddSub4Demo|Add0~5, AdderDemo, 1
-instance = comp, \AddSub4Demo|Add0~6\, AddSub4Demo|Add0~6, AdderDemo, 1
-instance = comp, \AddSub4Demo|Add0~8\, AddSub4Demo|Add0~8, AdderDemo, 1
-instance = comp, \AddSub4Demo|Add0~10\, AddSub4Demo|Add0~10, AdderDemo, 1
-instance = comp, \AddSub4Demo|Add0~12\, AddSub4Demo|Add0~12, AdderDemo, 1
-instance = comp, \AddSub4Demo|Add0~14\, AddSub4Demo|Add0~14, AdderDemo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, AdderDemo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, AdderDemo, 1
-instance = comp, \SW[5]~input\, SW[5]~input, AdderDemo, 1
-instance = comp, \SW[4]~input\, SW[4]~input, AdderDemo, 1
-instance = comp, \Adder4Demo|bit1|cout~0\, Adder4Demo|bit1|cout~0, AdderDemo, 1
-instance = comp, \SW[6]~input\, SW[6]~input, AdderDemo, 1
-instance = comp, \SW[2]~input\, SW[2]~input, AdderDemo, 1
-instance = comp, \Adder4Demo|bit2|cout~0\, Adder4Demo|bit2|cout~0, AdderDemo, 1
-instance = comp, \SW[3]~input\, SW[3]~input, AdderDemo, 1
-instance = comp, \SW[7]~input\, SW[7]~input, AdderDemo, 1
-instance = comp, \Adder4Demo|bit3|cout~0\, Adder4Demo|bit3|cout~0, AdderDemo, 1
-instance = comp, \Adder4Demo|bit3|s\, Adder4Demo|bit3|s, AdderDemo, 1
-instance = comp, \Adder4Demo|bit2|s~0\, Adder4Demo|bit2|s~0, AdderDemo, 1
-instance = comp, \Adder4Demo|bit1|s~0\, Adder4Demo|bit1|s~0, AdderDemo, 1
-instance = comp, \Adder4Demo|bit0|s~0\, Adder4Demo|bit0|s~0, AdderDemo, 1
-instance = comp, \SW[9]~input\, SW[9]~input, AdderDemo, 1
-instance = comp, \SW[8]~input\, SW[8]~input, AdderDemo, 1
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/Adder4.vwf.vht b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/Adder4.vwf.vht
deleted file mode 100644
index 1cdfa57..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/Adder4.vwf.vht
+++ /dev/null
@@ -1,52 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- *****************************************************************************
--- This file contains a Vhdl test bench with test vectors .The test vectors
--- are exported from a vector file in the Quartus Waveform Editor and apply to
--- the top level entity of the current Quartus project .The user can use this
--- testbench to simulate his design using a third-party simulation tool .
--- *****************************************************************************
--- Generated on "03/08/2023 11:38:17"
-
--- Vhdl Test Bench(with test vectors) for design : AdderDemo
---
--- Simulation tool : 3rd Party
---
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY AdderDemo_vhd_vec_tst IS
-END AdderDemo_vhd_vec_tst;
-ARCHITECTURE AdderDemo_arch OF AdderDemo_vhd_vec_tst IS
--- constants
--- signals
-SIGNAL LEDR : STD_LOGIC_VECTOR(4 DOWNTO 0);
-SIGNAL SW : STD_LOGIC_VECTOR(7 DOWNTO 0);
-COMPONENT AdderDemo
- PORT (
- LEDR : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
- SW : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
- );
-END COMPONENT;
-BEGIN
- i1 : AdderDemo
- PORT MAP (
--- list connections between master ports and signals
- LEDR => LEDR,
- SW => SW
- );
-END AdderDemo_arch;
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.do b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.do
deleted file mode 100644
index 0a9f158..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.do
+++ /dev/null
@@ -1,18 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vcom -work work AdderDemo.vho
-vcom -work work Adder4.vwf.vht
-vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Adder4_vhd_vec_tst
-vcd file -direction AdderDemo.msim.vcd
-vcd add -internal Adder4_vhd_vec_tst/*
-vcd add -internal Adder4_vhd_vec_tst/i1/*
-proc simTimestamp {} {
- echo "Simulation time: $::now ps"
- if { [string equal running [runStatus]] } {
- after 2500 simTimestamp
- }
-}
-after 2500 simTimestamp
-run -all
-quit -f
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.msim.vcd b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.msim.vcd
deleted file mode 100644
index 00ff615..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.msim.vcd
+++ /dev/null
@@ -1,230 +0,0 @@
-$comment
- File created using the following command:
- vcd file AdderDemo.msim.vcd -direction
-$end
-$date
- Wed Mar 8 11:38:18 2023
-$end
-$version
- ModelSim Version 2020.1
-$end
-$timescale
- 1ps
-$end
-
-$scope module adder4_vhd_vec_tst $end
-$var wire 1 ! a [3] $end
-$var wire 1 " a [2] $end
-$var wire 1 # a [1] $end
-$var wire 1 $ a [0] $end
-$var wire 1 % b [3] $end
-$var wire 1 & b [2] $end
-$var wire 1 ' b [1] $end
-$var wire 1 ( b [0] $end
-$var wire 1 ) cin $end
-$var wire 1 * cout $end
-$var wire 1 + s [3] $end
-$var wire 1 , s [2] $end
-$var wire 1 - s [1] $end
-$var wire 1 . s [0] $end
-
-$scope module i1 $end
-$var wire 1 / gnd $end
-$var wire 1 0 vcc $end
-$var wire 1 1 unknown $end
-$var wire 1 2 devoe $end
-$var wire 1 3 devclrn $end
-$var wire 1 4 devpor $end
-$var wire 1 5 ww_devoe $end
-$var wire 1 6 ww_devclrn $end
-$var wire 1 7 ww_devpor $end
-$var wire 1 8 ww_a [3] $end
-$var wire 1 9 ww_a [2] $end
-$var wire 1 : ww_a [1] $end
-$var wire 1 ; ww_a [0] $end
-$var wire 1 < ww_b [3] $end
-$var wire 1 = ww_b [2] $end
-$var wire 1 > ww_b [1] $end
-$var wire 1 ? ww_b [0] $end
-$var wire 1 @ ww_cin $end
-$var wire 1 A ww_s [3] $end
-$var wire 1 B ww_s [2] $end
-$var wire 1 C ww_s [1] $end
-$var wire 1 D ww_s [0] $end
-$var wire 1 E ww_cout $end
-$var wire 1 F \s[0]~output_o\ $end
-$var wire 1 G \s[1]~output_o\ $end
-$var wire 1 H \s[2]~output_o\ $end
-$var wire 1 I \s[3]~output_o\ $end
-$var wire 1 J \cout~output_o\ $end
-$var wire 1 K \a[0]~input_o\ $end
-$var wire 1 L \b[0]~input_o\ $end
-$var wire 1 M \cin~input_o\ $end
-$var wire 1 N \bit0|s~0_combout\ $end
-$var wire 1 O \b[1]~input_o\ $end
-$var wire 1 P \a[1]~input_o\ $end
-$var wire 1 Q \bit0|cout~0_combout\ $end
-$var wire 1 R \bit1|s~combout\ $end
-$var wire 1 S \bit1|cout~0_combout\ $end
-$var wire 1 T \a[2]~input_o\ $end
-$var wire 1 U \b[2]~input_o\ $end
-$var wire 1 V \bit2|s~combout\ $end
-$var wire 1 W \bit2|cout~0_combout\ $end
-$var wire 1 X \a[3]~input_o\ $end
-$var wire 1 Y \b[3]~input_o\ $end
-$var wire 1 Z \bit3|s~combout\ $end
-$var wire 1 [ \bit3|cout~0_combout\ $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0)
-1*
-0/
-10
-x1
-12
-13
-14
-15
-16
-17
-0@
-1E
-0F
-1G
-1H
-1I
-1J
-1K
-1L
-0M
-0N
-1O
-1P
-1Q
-1R
-1S
-1T
-1U
-1V
-1W
-1X
-1Y
-1Z
-1[
-1!
-1"
-1#
-1$
-1%
-1&
-1'
-1(
-18
-19
-1:
-1;
-1<
-1=
-1>
-1?
-1A
-1B
-1C
-0D
-1+
-1,
-1-
-0.
-$end
-#80000
-0%
-0&
-0'
-0(
-1)
-0?
-0>
-0=
-0<
-1@
-1M
-0Y
-0U
-0O
-0L
-0R
-0V
-0Z
-0I
-0H
-0G
-0A
-0B
-0C
-0-
-0,
-0+
-#160000
-1%
-1&
-0)
-0"
-0$
-1=
-1<
-0@
-0;
-09
-0T
-0K
-0M
-1Y
-1U
-1Z
-0Q
-1R
-0S
-1V
-0W
-1I
-0Z
-1A
-1G
-1+
-1C
-1H
-1-
-1B
-0I
-1,
-0A
-0+
-#240000
-0%
-0&
-0!
-0#
-0=
-0<
-0:
-08
-0X
-0P
-0Y
-0U
-0V
-0R
-0[
-0J
-0G
-0H
-0E
-0C
-0B
-0*
-0-
-0,
-#1000000
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.sft b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.vho b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.vho
deleted file mode 100644
index ebec02b..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.vho
+++ /dev/null
@@ -1,426 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/08/2023 11:38:17"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY AdderDemo IS
- PORT (
- LEDR : OUT std_logic_vector(4 DOWNTO 0);
- SW : IN std_logic_vector(7 DOWNTO 0)
- );
-END AdderDemo;
-
--- Design Ports Information
--- LEDR[4] => Location: PIN_F18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF AdderDemo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDR : std_logic_vector(4 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(7 DOWNTO 0);
-SIGNAL \LEDR[4]~output_o\ : std_logic;
-SIGNAL \LEDR[3]~output_o\ : std_logic;
-SIGNAL \LEDR[2]~output_o\ : std_logic;
-SIGNAL \LEDR[1]~output_o\ : std_logic;
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[5]~input_o\ : std_logic;
-SIGNAL \SW[4]~input_o\ : std_logic;
-SIGNAL \Adder4Demo|bit1|cout~0_combout\ : std_logic;
-SIGNAL \SW[6]~input_o\ : std_logic;
-SIGNAL \SW[2]~input_o\ : std_logic;
-SIGNAL \Adder4Demo|bit2|cout~0_combout\ : std_logic;
-SIGNAL \SW[3]~input_o\ : std_logic;
-SIGNAL \SW[7]~input_o\ : std_logic;
-SIGNAL \Adder4Demo|bit3|cout~0_combout\ : std_logic;
-SIGNAL \Adder4Demo|bit3|s~combout\ : std_logic;
-SIGNAL \Adder4Demo|bit2|s~0_combout\ : std_logic;
-SIGNAL \Adder4Demo|bit1|s~0_combout\ : std_logic;
-SIGNAL \Adder4Demo|bit0|s~0_combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-LEDR <= ww_LEDR;
-ww_SW <= SW;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X87_Y73_N16
-\LEDR[4]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Adder4Demo|bit3|cout~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[4]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N16
-\LEDR[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Adder4Demo|bit3|s~combout\,
- devoe => ww_devoe,
- o => \LEDR[3]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N9
-\LEDR[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Adder4Demo|bit2|s~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[2]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N2
-\LEDR[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Adder4Demo|bit1|s~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[1]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N16
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Adder4Demo|bit0|s~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y11_N8
-\SW[5]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(5),
- o => \SW[5]~input_o\);
-
--- Location: IOIBUF_X115_Y18_N8
-\SW[4]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(4),
- o => \SW[4]~input_o\);
-
--- Location: LCCOMB_X114_Y18_N24
-\Adder4Demo|bit1|cout~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit1|cout~0_combout\ = (\SW[1]~input_o\ & ((\SW[5]~input_o\) # ((\SW[0]~input_o\ & \SW[4]~input_o\)))) # (!\SW[1]~input_o\ & (\SW[0]~input_o\ & (\SW[5]~input_o\ & \SW[4]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1110100011000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[0]~input_o\,
- datab => \SW[1]~input_o\,
- datac => \SW[5]~input_o\,
- datad => \SW[4]~input_o\,
- combout => \Adder4Demo|bit1|cout~0_combout\);
-
--- Location: IOIBUF_X115_Y10_N1
-\SW[6]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(6),
- o => \SW[6]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N8
-\SW[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(2),
- o => \SW[2]~input_o\);
-
--- Location: LCCOMB_X114_Y18_N10
-\Adder4Demo|bit2|cout~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit2|cout~0_combout\ = (\Adder4Demo|bit1|cout~0_combout\ & ((\SW[6]~input_o\) # (\SW[2]~input_o\))) # (!\Adder4Demo|bit1|cout~0_combout\ & (\SW[6]~input_o\ & \SW[2]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111110011000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \Adder4Demo|bit1|cout~0_combout\,
- datac => \SW[6]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \Adder4Demo|bit2|cout~0_combout\);
-
--- Location: IOIBUF_X115_Y13_N8
-\SW[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(3),
- o => \SW[3]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N1
-\SW[7]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(7),
- o => \SW[7]~input_o\);
-
--- Location: LCCOMB_X114_Y18_N28
-\Adder4Demo|bit3|cout~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit3|cout~0_combout\ = (\Adder4Demo|bit2|cout~0_combout\ & ((\SW[3]~input_o\) # (\SW[7]~input_o\))) # (!\Adder4Demo|bit2|cout~0_combout\ & (\SW[3]~input_o\ & \SW[7]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111101010100000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Adder4Demo|bit2|cout~0_combout\,
- datac => \SW[3]~input_o\,
- datad => \SW[7]~input_o\,
- combout => \Adder4Demo|bit3|cout~0_combout\);
-
--- Location: LCCOMB_X114_Y18_N22
-\Adder4Demo|bit3|s\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit3|s~combout\ = \Adder4Demo|bit2|cout~0_combout\ $ (\SW[3]~input_o\ $ (\SW[7]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010010101011010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Adder4Demo|bit2|cout~0_combout\,
- datac => \SW[3]~input_o\,
- datad => \SW[7]~input_o\,
- combout => \Adder4Demo|bit3|s~combout\);
-
--- Location: LCCOMB_X114_Y18_N0
-\Adder4Demo|bit2|s~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit2|s~0_combout\ = \Adder4Demo|bit1|cout~0_combout\ $ (\SW[6]~input_o\ $ (\SW[2]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100111100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \Adder4Demo|bit1|cout~0_combout\,
- datac => \SW[6]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \Adder4Demo|bit2|s~0_combout\);
-
--- Location: LCCOMB_X114_Y18_N26
-\Adder4Demo|bit1|s~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit1|s~0_combout\ = \SW[1]~input_o\ $ (\SW[5]~input_o\ $ (((\SW[0]~input_o\ & \SW[4]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000111100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[0]~input_o\,
- datab => \SW[1]~input_o\,
- datac => \SW[5]~input_o\,
- datad => \SW[4]~input_o\,
- combout => \Adder4Demo|bit1|s~0_combout\);
-
--- Location: LCCOMB_X114_Y18_N4
-\Adder4Demo|bit0|s~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Adder4Demo|bit0|s~0_combout\ = \SW[0]~input_o\ $ (\SW[4]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000111111110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \SW[0]~input_o\,
- datad => \SW[4]~input_o\,
- combout => \Adder4Demo|bit0|s~0_combout\);
-
-ww_LEDR(4) <= \LEDR[4]~output_o\;
-
-ww_LEDR(3) <= \LEDR[3]~output_o\;
-
-ww_LEDR(2) <= \LEDR[2]~output_o\;
-
-ww_LEDR(1) <= \LEDR[1]~output_o\;
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo_20230308111005.sim.vwf b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo_20230308111005.sim.vwf
deleted file mode 100644
index 2bc58a5..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo_20230308111005.sim.vwf
+++ /dev/null
@@ -1,583 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("a")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 4;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("a[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "a";
-}
-
-SIGNAL("a[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "a";
-}
-
-SIGNAL("a[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "a";
-}
-
-SIGNAL("a[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "a";
-}
-
-SIGNAL("b")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 4;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("b[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "b";
-}
-
-SIGNAL("b[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "b";
-}
-
-SIGNAL("b[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "b";
-}
-
-SIGNAL("b[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "b";
-}
-
-SIGNAL("cin")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("cout")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("s")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 4;
- LSB_INDEX = 0;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("s[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "s";
-}
-
-SIGNAL("s[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "s";
-}
-
-SIGNAL("s[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "s";
-}
-
-SIGNAL("s[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "s";
-}
-
-TRANSITION_LIST("a[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 240.0;
- LEVEL 0 FOR 760.0;
- }
- }
-}
-
-TRANSITION_LIST("a[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 840.0;
- }
- }
-}
-
-TRANSITION_LIST("a[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 240.0;
- LEVEL 0 FOR 760.0;
- }
- }
-}
-
-TRANSITION_LIST("a[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 840.0;
- }
- }
-}
-
-TRANSITION_LIST("b[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 760.0;
- }
- }
-}
-
-TRANSITION_LIST("b[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 760.0;
- }
- }
-}
-
-TRANSITION_LIST("b[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 920.0;
- }
- }
-}
-
-TRANSITION_LIST("b[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 920.0;
- }
- }
-}
-
-TRANSITION_LIST("cin")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 840.0;
- }
- }
-}
-
-TRANSITION_LIST("cout")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 240.0;
- LEVEL 0 FOR 760.0;
- }
- }
-}
-
-TRANSITION_LIST("s[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 920.0;
- }
- }
-}
-
-TRANSITION_LIST("s[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 760.0;
- }
- }
-}
-
-TRANSITION_LIST("s[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 760.0;
- }
- }
-}
-
-TRANSITION_LIST("s[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 1000.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "a";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
- CHILDREN = 1, 2, 3, 4;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "a[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "a[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "a[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "a[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "b";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 5;
- TREE_LEVEL = 0;
- CHILDREN = 6, 7, 8, 9;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "b[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 6;
- TREE_LEVEL = 1;
- PARENT = 5;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "b[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 7;
- TREE_LEVEL = 1;
- PARENT = 5;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "b[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 8;
- TREE_LEVEL = 1;
- PARENT = 5;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "b[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 9;
- TREE_LEVEL = 1;
- PARENT = 5;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "cin";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 10;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "cout";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 11;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "s";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 12;
- TREE_LEVEL = 0;
- CHILDREN = 13, 14, 15, 16;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "s[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 13;
- TREE_LEVEL = 1;
- PARENT = 12;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "s[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 14;
- TREE_LEVEL = 1;
- PARENT = 12;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "s[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 15;
- TREE_LEVEL = 1;
- PARENT = 12;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "s[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 16;
- TREE_LEVEL = 1;
- PARENT = 12;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo_20230308113818.sim.vwf b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo_20230308113818.sim.vwf
deleted file mode 100644
index 9d13628..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo_20230308113818.sim.vwf
+++ /dev/null
@@ -1,519 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("a")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 4;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("a[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "a";
-}
-
-SIGNAL("a[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "a";
-}
-
-SIGNAL("a[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "a";
-}
-
-SIGNAL("a[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "a";
-}
-
-SIGNAL("b")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 4;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("b[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "b";
-}
-
-SIGNAL("b[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "b";
-}
-
-SIGNAL("b[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "b";
-}
-
-SIGNAL("b[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "b";
-}
-
-SIGNAL("cin")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("cout")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("s")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 4;
- LSB_INDEX = 0;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("s[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "s";
-}
-
-SIGNAL("s[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "s";
-}
-
-SIGNAL("s[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "s";
-}
-
-SIGNAL("s[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "s";
-}
-
-TRANSITION_LIST("a[3]")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 240.0;
- LEVEL 0 FOR 760.0;
- }
-}
-
-TRANSITION_LIST("a[2]")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 840.0;
- }
-}
-
-TRANSITION_LIST("a[1]")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 240.0;
- LEVEL 0 FOR 760.0;
- }
-}
-
-TRANSITION_LIST("a[0]")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 840.0;
- }
-}
-
-TRANSITION_LIST("b[3]")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 760.0;
- }
-}
-
-TRANSITION_LIST("b[2]")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 760.0;
- }
-}
-
-TRANSITION_LIST("b[1]")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 920.0;
- }
-}
-
-TRANSITION_LIST("b[0]")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 920.0;
- }
-}
-
-TRANSITION_LIST("cin")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 840.0;
- }
-}
-
-TRANSITION_LIST("cout")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL X FOR 1000.0;
- }
-}
-
-TRANSITION_LIST("s[3]")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL X FOR 1000.0;
- }
-}
-
-TRANSITION_LIST("s[2]")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL X FOR 1000.0;
- }
-}
-
-TRANSITION_LIST("s[1]")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL X FOR 1000.0;
- }
-}
-
-TRANSITION_LIST("s[0]")
-{
- NODE
- {
- REPEAT = 1;
- LEVEL X FOR 1000.0;
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "a";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
- CHILDREN = 1, 2, 3, 4;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "a[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "a[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "a[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "a[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 1;
- PARENT = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "b";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 5;
- TREE_LEVEL = 0;
- CHILDREN = 6, 7, 8, 9;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "b[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 6;
- TREE_LEVEL = 1;
- PARENT = 5;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "b[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 7;
- TREE_LEVEL = 1;
- PARENT = 5;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "b[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 8;
- TREE_LEVEL = 1;
- PARENT = 5;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "b[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 9;
- TREE_LEVEL = 1;
- PARENT = 5;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "cin";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 10;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "cout";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 11;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "s";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 12;
- TREE_LEVEL = 0;
- CHILDREN = 13, 14, 15, 16;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "s[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 13;
- TREE_LEVEL = 1;
- PARENT = 12;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "s[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 14;
- TREE_LEVEL = 1;
- PARENT = 12;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "s[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 15;
- TREE_LEVEL = 1;
- PARENT = 12;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "s[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 16;
- TREE_LEVEL = 1;
- PARENT = 12;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo_modelsim.xrf
deleted file mode 100644
index 0291639..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo_modelsim.xrf
+++ /dev/null
@@ -1,32 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vwf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cbx.xml
-design_name = hard_block
-design_name = AdderDemo
-instance = comp, \LEDR[4]~output\, LEDR[4]~output, AdderDemo, 1
-instance = comp, \LEDR[3]~output\, LEDR[3]~output, AdderDemo, 1
-instance = comp, \LEDR[2]~output\, LEDR[2]~output, AdderDemo, 1
-instance = comp, \LEDR[1]~output\, LEDR[1]~output, AdderDemo, 1
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, AdderDemo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, AdderDemo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, AdderDemo, 1
-instance = comp, \SW[5]~input\, SW[5]~input, AdderDemo, 1
-instance = comp, \SW[4]~input\, SW[4]~input, AdderDemo, 1
-instance = comp, \Adder4Demo|bit1|cout~0\, Adder4Demo|bit1|cout~0, AdderDemo, 1
-instance = comp, \SW[6]~input\, SW[6]~input, AdderDemo, 1
-instance = comp, \SW[2]~input\, SW[2]~input, AdderDemo, 1
-instance = comp, \Adder4Demo|bit2|cout~0\, Adder4Demo|bit2|cout~0, AdderDemo, 1
-instance = comp, \SW[3]~input\, SW[3]~input, AdderDemo, 1
-instance = comp, \SW[7]~input\, SW[7]~input, AdderDemo, 1
-instance = comp, \Adder4Demo|bit3|cout~0\, Adder4Demo|bit3|cout~0, AdderDemo, 1
-instance = comp, \Adder4Demo|bit3|s\, Adder4Demo|bit3|s, AdderDemo, 1
-instance = comp, \Adder4Demo|bit2|s~0\, Adder4Demo|bit2|s~0, AdderDemo, 1
-instance = comp, \Adder4Demo|bit1|s~0\, Adder4Demo|bit1|s~0, AdderDemo, 1
-instance = comp, \Adder4Demo|bit0|s~0\, Adder4Demo|bit0|s~0, AdderDemo, 1
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/transcript
deleted file mode 100644
index f425df4..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/transcript
+++ /dev/null
@@ -1,46 +0,0 @@
-# do AdderDemo.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 11:38:18 on Mar 08,2023
-# vcom -work work AdderDemo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity hard_block
-# -- Compiling architecture structure of hard_block
-# -- Compiling entity AdderDemo
-# -- Compiling architecture structure of AdderDemo
-# End time: 11:38:18 on Mar 08,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 11:38:18 on Mar 08,2023
-# vcom -work work Adder4.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity AdderDemo_vhd_vec_tst
-# -- Compiling architecture AdderDemo_arch of AdderDemo_vhd_vec_tst
-# End time: 11:38:18 on Mar 08,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Adder4_vhd_vec_tst
-# Start time: 11:38:18 on Mar 08,2023
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading work.adder4_vhd_vec_tst(adder4_arch)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading cycloneive.cycloneive_atom_pack(body)
-# Loading cycloneive.cycloneive_components
-# Loading work.adder4(structure)
-# Loading ieee.std_logic_arith(body)
-# Loading cycloneive.cycloneive_io_obuf(arch)
-# Loading cycloneive.cycloneive_io_ibuf(arch)
-# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#33
-# End time: 11:38:18 on Mar 08,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/vwf_sim_transcript
deleted file mode 100644
index 16e9439..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/vwf_sim_transcript
+++ /dev/null
@@ -1,96 +0,0 @@
-Determining the location of the ModelSim executable...
-
-Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
-
-To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
-Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
-
-**** Generating the ModelSim Testbench ****
-
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off AdderDemo -c AdderDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/Adder4.vwf.vht"
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Mar 8 11:38:16 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off AdderDemo -c AdderDemo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/Adder4.vwf.vhtWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Completed successfully.
-
-**** Generating the functional simulation netlist ****
-
-quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/" AdderDemo -c AdderDemo
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Mar 8 11:38:17 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/ AdderDemo -c AdderDemoWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file AdderDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 612 megabytes Info: Processing ended: Wed Mar 8 11:38:17 2023 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00
-Completed successfully.
-
-**** Generating the ModelSim .do script ****
-
-/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.do generated.
-
-Completed successfully.
-
-**** Running the ModelSim simulation ****
-
-/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do AdderDemo.do
-
-Reading pref.tcl
-# 2020.1
-# do AdderDemo.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 11:38:18 on Mar 08,2023# vcom -work work AdderDemo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives# -- Loading package cycloneive_atom_pack# -- Loading package cycloneive_components
-# -- Compiling entity hard_block# -- Compiling architecture structure of hard_block# -- Compiling entity AdderDemo# -- Compiling architecture structure of AdderDemo
-# End time: 11:38:18 on Mar 08,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020# Start time: 11:38:18 on Mar 08,2023# vcom -work work Adder4.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164# -- Compiling entity AdderDemo_vhd_vec_tst# -- Compiling architecture AdderDemo_arch of AdderDemo_vhd_vec_tst
-# End time: 11:38:18 on Mar 08,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Adder4_vhd_vec_tst # Start time: 11:38:18 on Mar 08,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.adder4_vhd_vec_tst(adder4_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.adder4(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# after#33
-# End time: 11:38:18 on Mar 08,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-Completed successfully.
-
-**** Converting ModelSim VCD to vector waveform ****
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vwf...
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo.msim.vcd...
-
-Processing channel transitions...
-
-Warning: a[3] - signal not found in VCD.
-
-Warning: a[2] - signal not found in VCD.
-
-Warning: a[1] - signal not found in VCD.
-
-Warning: a[0] - signal not found in VCD.
-
-Warning: b[3] - signal not found in VCD.
-
-Warning: b[2] - signal not found in VCD.
-
-Warning: b[1] - signal not found in VCD.
-
-Warning: b[0] - signal not found in VCD.
-
-Warning: cin - signal not found in VCD.
-
-Warning: cout - signal not found in VCD.
-
-Warning: s[3] - signal not found in VCD.
-
-Warning: s[2] - signal not found in VCD.
-
-Warning: s[1] - signal not found in VCD.
-
-Warning: s[0] - signal not found in VCD.
-
-Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/AdderDemo_20230308113818.sim.vwf
-
-Finished VCD to VWF conversion.
-
-Completed successfully.
-
-All completed.
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_info
deleted file mode 100644
index df0f49e..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_info
+++ /dev/null
@@ -1,240 +0,0 @@
-m255
-K4
-z2
-!s11e vcom 2020.1 2020.02, Feb 28 2020
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-Z0 d/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim
-Eadder4
-Z1 w1678273804
-Z2 DPx4 ieee 16 vital_primitives 0 22 G>kiXP8Q9dRClKfK1Zn7j1
-Z3 DPx10 cycloneive 20 cycloneive_atom_pack 0 22 WOh:M[al;oVzG5c`D0
-Z4 DPx4 ieee 12 vital_timing 0 22 J>EBealN09f8GzldA[z2>3
-Z5 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
-Z6 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
-Z7 DPx10 cycloneive 21 cycloneive_components 0 22 zGMDhP>8e@2k@f0e:7@GNGcQ?iG?JIfkG1
-!s100 Id0OlbDfnHdU;>6TD3c]32
-Z11 OV;C;2020.1;71
-32
-Z12 !s110 1678273805
-!i10b 1
-Z13 !s108 1678273805.000000
-Z14 !s90 -work|work|AdderDemo.vho|
-Z15 !s107 AdderDemo.vho|
-!i113 1
-Z16 o-work work
-Z17 tExplicit 1 CvgOpt 0
-Astructure
-R2
-R3
-R4
-R5
-R6
-R7
-DEx4 work 6 adder4 0 22 Rz;>:7@GNGcQ?iG?JIfkG1
-!i122 0
-l83
-L45 324
-VOU6S>dP07X?OSGk3
-R11
-32
-R12
-!i10b 1
-R13
-Z22 !s90 -work|work|Adder4.vwf.vht|
-Z23 !s107 Adder4.vwf.vht|
-!i113 1
-R16
-R17
-Aadder4_arch
-R5
-R6
-DEx4 work 18 adder4_vhd_vec_tst 0 22 dLm96M_zXU[dfR1hHTAZ`2
-!i122 1
-l51
-L34 111
-VojQI1]EObRB^Bg4i[;dgo3
-!s100 d00K`b39LKBMZ[Hm7HKoo3
-R11
-32
-R12
-!i10b 1
-R13
-R22
-R23
-!i113 1
-R16
-R17
-Eadderdemo
-Z24 w1678275497
-R2
-R3
-R4
-R5
-R6
-R7
-!i122 2
-R0
-R8
-R9
-l0
-L78 1
-V`Pk]F];cnmeZHlK@>gm>a96NQ0
-R11
-32
-R25
-!i10b 1
-R26
-R22
-R23
-!i113 1
-R16
-R17
-Aadderdemo_arch
-R5
-R6
-DEx4 work 21 adderdemo_vhd_vec_tst 0 22 ?7R5oX6Aa^J5Zzik`8dMM2
-!i122 3
-l45
-L34 19
-VJ`hj[g6jgVX2F5SH3kF?A1
-!s100 3L0VNCF=PB3TBmR?kG8ii2
-R11
-32
-R25
-!i10b 1
-R26
-R22
-R23
-!i113 1
-R16
-R17
-Ehard_block
-R24
-R2
-R3
-R4
-R5
-R6
-R7
-!i122 2
-R0
-R8
-R9
-l0
-R10
-VB]0;STalBkCB1_B4BXQDW2
-!s100 >mXi5[`cD`bFC`UBKA5o7W??azG@W@@eFOTF0
-!s100 [5;Wd8QGQ>@2NGoJ1I]Y43
-R11
-32
-R25
-!i10b 1
-R26
-R14
-R15
-!i113 1
-R16
-R17
diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_lib.qdb b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_lib.qdb
deleted file mode 100644
index fb16ffc..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_lib1_0.qdb b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_lib1_0.qdb
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_lib1_0.qpg b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_lib1_0.qpg
deleted file mode 100644
index 77328a7..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_lib1_0.qtl b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_lib1_0.qtl
deleted file mode 100644
index 6c6eaee..0000000
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diff --git a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_vmake b/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_vmake
deleted file mode 100644
index 37aa36a..0000000
--- a/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/work/_vmake
+++ /dev/null
@@ -1,4 +0,0 @@
-m255
-K4
-z0
-cModel Technology
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd.bak b/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd.bak
deleted file mode 100644
index e69de29..0000000
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qpf b/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qpf
deleted file mode 100644
index 9eb31f6..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 16:44:06 March 16, 2023
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "20.1"
-DATE = "16:44:06 March 16, 2023"
-
-# Revisions
-
-PROJECT_REVISION = "CounterDemo"
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qsf b/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qsf
deleted file mode 100644
index 15a104b..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qsf
+++ /dev/null
@@ -1,588 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 16:44:06 March 16, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# CounterDemo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY CounterDemo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:44:06 MARCH 16, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_global_assignment -name VHDL_FILE CounterUpDown4.vhd
-set_global_assignment -name VHDL_FILE CounterDown4.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE CounterDown4.vwf
-set_global_assignment -name BDF_FILE CounterDemo.bdf
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name VHDL_FILE Bin7SegDecoder.vhd
-set_global_assignment -name VHDL_FILE FreqDivider.vhd
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qsf.bak b/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qsf.bak
deleted file mode 100644
index 797d48f..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qsf.bak
+++ /dev/null
@@ -1,588 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 16:44:06 March 16, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# CounterDemo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY FreqDivider
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:44:06 MARCH 16, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_global_assignment -name VHDL_FILE CounterUpDown4.vhd
-set_global_assignment -name VHDL_FILE CounterDown4.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE CounterDown4.vwf
-set_global_assignment -name BDF_FILE CounterDemo.bdf
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name VHDL_FILE Bin7SegDecoder.vhd
-set_global_assignment -name VHDL_FILE FreqDivider.vhd
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qws b/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qws
deleted file mode 100644
index 8d82a79..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qws and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd.bak b/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd.bak
deleted file mode 100644
index 7da1852..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd.bak
+++ /dev/null
@@ -1,23 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-
-entity CounterDown4 is
- port
- (
- clk: in std_logic;
- count : out std_logic_vector(3 downto 0)
- );
-end CounterDown4;
-
-architecture Behavioral of CounterDown4 is
- signal s_count : unsigned(3 downto 0);
-begin
- process(clk)
- begin
- if (rising_edge(clk)) then
- s_count <= s_count - 1;
- end if;
- end process;
- count <= std_logic_vector(s_count);
-end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd.bak b/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd.bak
deleted file mode 100644
index 7da1852..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd.bak
+++ /dev/null
@@ -1,23 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-
-entity CounterDown4 is
- port
- (
- clk: in std_logic;
- count : out std_logic_vector(3 downto 0)
- );
-end CounterDown4;
-
-architecture Behavioral of CounterDown4 is
- signal s_count : unsigned(3 downto 0);
-begin
- process(clk)
- begin
- if (rising_edge(clk)) then
- s_count <= s_count - 1;
- end if;
- end process;
- count <= std_logic_vector(s_count);
-end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd.bak b/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd.bak
deleted file mode 100644
index 176a292..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd.bak
+++ /dev/null
@@ -1,32 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-
-entity FreqDivider is
- port (clkIn : in std_logic;
- k : in std_logic_vector(31 downto 0);
- clkOut : out std_logic
- );
-end FreqDivider;
-
-architecture Behavioral of FreqDivider is
- signal s_counter : unsigned(31 downto 0);
- signal s_halfWay : unsigned(31 downto 0);
-begin
- s_halfWay <= unsigned(k);
-
- process(clkIn)
- begin
- if (rising_edge(clkIn)) then
- if (s_counter = s_halfWay - 1) then
- clkOut <= '0';
- s_counter <= (others => '0');
- else
- if (s_counter = s_halfWay/2 - 1) then
- clkOut <= '1';
- end if;
- s_counter <= s_counter + 1;
- end if;
- end if;
- end process;
-end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(0).cnf.cdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(0).cnf.cdb
deleted file mode 100644
index cc4a4a3..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(0).cnf.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(0).cnf.hdb
deleted file mode 100644
index c5fb90c..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(1).cnf.cdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(1).cnf.cdb
deleted file mode 100644
index 321a09b..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(1).cnf.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(1).cnf.hdb
deleted file mode 100644
index 55a936a..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(2).cnf.cdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(2).cnf.cdb
deleted file mode 100644
index 162b432..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(2).cnf.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(2).cnf.hdb
deleted file mode 100644
index 181b407..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(3).cnf.cdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(3).cnf.cdb
deleted file mode 100644
index 4f6fc8f..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(3).cnf.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(3).cnf.hdb
deleted file mode 100644
index fba8562..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(4).cnf.cdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(4).cnf.cdb
deleted file mode 100644
index 2010dbe..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(4).cnf.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(4).cnf.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(4).cnf.hdb
deleted file mode 100644
index 9784bd7..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.(4).cnf.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.asm.qmsg b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.asm.qmsg
deleted file mode 100644
index d0c5af5..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.asm.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318129121 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318129121 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:15:29 2023 " "Processing started: Mon Mar 20 13:15:29 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318129121 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1679318129121 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1679318129121 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1679318129243 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1679318130666 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1679318130726 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "364 " "Peak virtual memory: 364 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318130905 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:15:30 2023 " "Processing ended: Mon Mar 20 13:15:30 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318130905 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318130905 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318130905 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1679318130905 ""}
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.asm.rdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.asm.rdb
deleted file mode 100644
index 06e8a5c..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.asm.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.asm_labs.ddb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.asm_labs.ddb
deleted file mode 100644
index 07ccaf8..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.asm_labs.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cbx.xml b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cbx.xml
deleted file mode 100644
index 8ad906f..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.bpm b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.bpm
deleted file mode 100644
index 7c4d55d..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.bpm and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.cdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.cdb
deleted file mode 100644
index 1ec6026..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.hdb
deleted file mode 100644
index 8ae8708..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.idb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.idb
deleted file mode 100644
index fba23b5..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.idb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.logdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.logdb
deleted file mode 100644
index 7a00f28..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.logdb
+++ /dev/null
@@ -1,52 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;10;10;0;0;10;10;0;0;0;0;0;0;7;0;0;0;3;7;0;3;0;0;7;0;10;10;10;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,10;0;0;10;10;0;0;10;10;10;10;10;10;3;10;10;10;7;3;10;7;10;10;3;10;0;0;0;10;10,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CLOCK_50,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.rdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp.rdb
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp_merge.kpt b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cmp_merge.kpt
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.db_info b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.db_info
deleted file mode 100644
index ad7fae0..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Mon Mar 20 12:53:27 2023
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.eda.qmsg b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.eda.qmsg
deleted file mode 100644
index 1fdde22..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318133210 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318133210 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:15:33 2023 " "Processing started: Mon Mar 20 13:15:33 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318133210 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679318133210 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679318133210 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1679318133360 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "CounterDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/ simulation " "Generated file CounterDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1679318133388 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318133399 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:15:33 2023 " "Processing ended: Mon Mar 20 13:15:33 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318133399 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318133399 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318133399 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1679318133399 ""}
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.fit.qmsg b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.fit.qmsg
deleted file mode 100644
index ef084c8..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.fit.qmsg
+++ /dev/null
@@ -1,48 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1679318120848 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1679318120848 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "CounterDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"CounterDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1679318120850 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679318120891 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679318120891 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1679318121107 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1679318121110 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318121138 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318121138 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318121138 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318121138 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318121138 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318121138 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318121138 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318121138 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318121138 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1679318121138 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/" { { 0 { 0 ""} 0 736 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318121140 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/" { { 0 { 0 ""} 0 738 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318121140 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/" { { 0 { 0 ""} 0 740 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318121140 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/" { { 0 { 0 ""} 0 742 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318121140 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/" { { 0 { 0 ""} 0 744 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318121140 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1679318121140 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1679318121141 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "CounterDemo.sdc " "Synopsys Design Constraints File file not found: 'CounterDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1679318121617 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1679318121617 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1679318121619 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1679318121619 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1679318121619 ""}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1679318121626 ""} } { { "CounterDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 176 152 320 192 "CLOCK_50" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/" { { 0 { 0 ""} 0 731 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1679318121626 ""}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "FreqDivider:inst1\|clkOut " "Automatically promoted node FreqDivider:inst1\|clkOut " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1679318121626 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "FreqDivider:inst1\|clkOut~3 " "Destination node FreqDivider:inst1\|clkOut~3" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd" 7 -1 0 } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/" { { 0 { 0 ""} 0 643 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1679318121626 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1679318121626 ""} } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd" 7 -1 0 } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/" { { 0 { 0 ""} 0 598 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1679318121626 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1679318121734 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679318121734 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679318121734 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1679318121735 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1679318121735 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1679318121735 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1679318121735 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1679318121735 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1679318121735 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1679318121735 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1679318121735 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318121755 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1679318121755 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318121762 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1679318121764 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1679318123092 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318123162 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1679318123187 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1679318125341 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318125341 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1679318125460 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X46_Y0 X57_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X57_Y11" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X57_Y11"} { { 12 { 0 ""} 46 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1679318127351 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1679318127351 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1679318127753 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1679318127753 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318127755 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.06 " "Total time spent on timing analysis during the Fitter is 0.06 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1679318127825 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1679318127830 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1679318127981 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1679318127982 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1679318128107 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318128326 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1679318128486 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1679318128520 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 515 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 515 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1158 " "Peak virtual memory: 1158 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318128638 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:15:28 2023 " "Processing ended: Mon Mar 20 13:15:28 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318128638 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318128638 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318128638 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1679318128638 ""}
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.hier_info b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.hier_info
deleted file mode 100644
index bab3793..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.hier_info
+++ /dev/null
@@ -1,139 +0,0 @@
-|CounterDemo
-HEX0[0] <= Bin7SegDecoder:hex.decOut_n[0]
-HEX0[1] <= Bin7SegDecoder:hex.decOut_n[1]
-HEX0[2] <= Bin7SegDecoder:hex.decOut_n[2]
-HEX0[3] <= Bin7SegDecoder:hex.decOut_n[3]
-HEX0[4] <= Bin7SegDecoder:hex.decOut_n[4]
-HEX0[5] <= Bin7SegDecoder:hex.decOut_n[5]
-HEX0[6] <= Bin7SegDecoder:hex.decOut_n[6]
-CLOCK_50 => FreqDivider:inst1.clkIn
-KEY[1] => inst3.IN0
-SW[0] => CounterUpDown4:inst.upDown
-
-
-|CounterDemo|Bin7SegDecoder:hex
-binInput[0] => Equal0.IN3
-binInput[0] => Equal1.IN0
-binInput[0] => Equal2.IN3
-binInput[0] => Equal3.IN1
-binInput[0] => Equal4.IN3
-binInput[0] => Equal5.IN1
-binInput[0] => Equal6.IN3
-binInput[0] => Equal7.IN2
-binInput[0] => Equal8.IN3
-binInput[0] => Equal9.IN1
-binInput[0] => Equal10.IN3
-binInput[0] => Equal11.IN2
-binInput[0] => Equal12.IN3
-binInput[0] => Equal13.IN2
-binInput[0] => Equal14.IN3
-binInput[1] => Equal0.IN2
-binInput[1] => Equal1.IN3
-binInput[1] => Equal2.IN0
-binInput[1] => Equal3.IN0
-binInput[1] => Equal4.IN2
-binInput[1] => Equal5.IN3
-binInput[1] => Equal6.IN1
-binInput[1] => Equal7.IN1
-binInput[1] => Equal8.IN2
-binInput[1] => Equal9.IN3
-binInput[1] => Equal10.IN1
-binInput[1] => Equal11.IN1
-binInput[1] => Equal12.IN2
-binInput[1] => Equal13.IN3
-binInput[1] => Equal14.IN2
-binInput[2] => Equal0.IN1
-binInput[2] => Equal1.IN2
-binInput[2] => Equal2.IN2
-binInput[2] => Equal3.IN3
-binInput[2] => Equal4.IN0
-binInput[2] => Equal5.IN0
-binInput[2] => Equal6.IN0
-binInput[2] => Equal7.IN0
-binInput[2] => Equal8.IN1
-binInput[2] => Equal9.IN2
-binInput[2] => Equal10.IN2
-binInput[2] => Equal11.IN3
-binInput[2] => Equal12.IN1
-binInput[2] => Equal13.IN1
-binInput[2] => Equal14.IN1
-binInput[3] => Equal0.IN0
-binInput[3] => Equal1.IN1
-binInput[3] => Equal2.IN1
-binInput[3] => Equal3.IN2
-binInput[3] => Equal4.IN1
-binInput[3] => Equal5.IN2
-binInput[3] => Equal6.IN2
-binInput[3] => Equal7.IN3
-binInput[3] => Equal8.IN0
-binInput[3] => Equal9.IN0
-binInput[3] => Equal10.IN0
-binInput[3] => Equal11.IN0
-binInput[3] => Equal12.IN0
-binInput[3] => Equal13.IN0
-binInput[3] => Equal14.IN0
-decOut_n[0] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[1] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[2] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[3] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[4] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[5] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-decOut_n[6] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|CounterDemo|CounterUpDown4:inst
-clock => s_count[0].CLK
-clock => s_count[1].CLK
-clock => s_count[2].CLK
-clock => s_count[3].CLK
-reset => s_count[0].ACLR
-reset => s_count[1].ACLR
-reset => s_count[2].ACLR
-reset => s_count[3].ACLR
-upDown => s_count.OUTPUTSELECT
-upDown => s_count.OUTPUTSELECT
-upDown => s_count.OUTPUTSELECT
-upDown => s_count.OUTPUTSELECT
-count[0] <= s_count[0].DB_MAX_OUTPUT_PORT_TYPE
-count[1] <= s_count[1].DB_MAX_OUTPUT_PORT_TYPE
-count[2] <= s_count[2].DB_MAX_OUTPUT_PORT_TYPE
-count[3] <= s_count[3].DB_MAX_OUTPUT_PORT_TYPE
-
-
-|CounterDemo|FreqDivider:inst1
-clkIn => s_counter[0].CLK
-clkIn => s_counter[1].CLK
-clkIn => s_counter[2].CLK
-clkIn => s_counter[3].CLK
-clkIn => s_counter[4].CLK
-clkIn => s_counter[5].CLK
-clkIn => s_counter[6].CLK
-clkIn => s_counter[7].CLK
-clkIn => s_counter[8].CLK
-clkIn => s_counter[9].CLK
-clkIn => s_counter[10].CLK
-clkIn => s_counter[11].CLK
-clkIn => s_counter[12].CLK
-clkIn => s_counter[13].CLK
-clkIn => s_counter[14].CLK
-clkIn => s_counter[15].CLK
-clkIn => s_counter[16].CLK
-clkIn => s_counter[17].CLK
-clkIn => s_counter[18].CLK
-clkIn => s_counter[19].CLK
-clkIn => s_counter[20].CLK
-clkIn => s_counter[21].CLK
-clkIn => s_counter[22].CLK
-clkIn => s_counter[23].CLK
-clkIn => s_counter[24].CLK
-clkIn => s_counter[25].CLK
-clkIn => s_counter[26].CLK
-clkIn => s_counter[27].CLK
-clkIn => s_counter[28].CLK
-clkIn => s_counter[29].CLK
-clkIn => s_counter[30].CLK
-clkIn => s_counter[31].CLK
-clkIn => clkOut~reg0.CLK
-clkOut <= clkOut~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.hif b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.hif
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index b44e252..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.lpc.html b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.lpc.html
deleted file mode 100644
index 58aaef0..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.lpc.html
+++ /dev/null
@@ -1,66 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| inst1 |
-1 |
-0 |
-0 |
-0 |
-1 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
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-| inst |
-3 |
-0 |
-0 |
-0 |
-4 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
-| hex |
-4 |
-0 |
-0 |
-0 |
-7 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.lpc.rdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.lpc.rdb
deleted file mode 100644
index 64804c7..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.lpc.txt b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.lpc.txt
deleted file mode 100644
index 2375715..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.lpc.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; inst1 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; inst ; 3 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; hex ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.ammdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.ammdb
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.bpm b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.bpm
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.cdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.cdb
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.hdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.kpt b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.kpt
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.logdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.qmsg b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.qmsg
deleted file mode 100644
index 0e647b5..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.qmsg
+++ /dev/null
@@ -1,20 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318115039 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318115039 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:15:14 2023 " "Processing started: Mon Mar 20 13:15:14 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318115039 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318115039 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CounterDemo -c CounterDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off CounterDemo -c CounterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318115039 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679318115167 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679318115167 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CounterUpDown4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file CounterUpDown4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CounterUpDown4-Behavioral " "Found design unit 1: CounterUpDown4-Behavioral" { } { { "CounterUpDown4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119662 ""} { "Info" "ISGN_ENTITY_NAME" "1 CounterUpDown4 " "Found entity 1: CounterUpDown4" { } { { "CounterUpDown4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119662 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119662 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CounterDown4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file CounterDown4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CounterDown4-Behavioral " "Found design unit 1: CounterDown4-Behavioral" { } { { "CounterDown4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119662 ""} { "Info" "ISGN_ENTITY_NAME" "1 CounterDown4 " "Found entity 1: CounterDown4" { } { { "CounterDown4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119662 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119662 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CounterDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file CounterDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CounterDemo " "Found entity 1: CounterDemo" { } { { "CounterDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119663 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Bin7SegDecoder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Bin7SegDecoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Bin7SegDecoder-Behavioral " "Found design unit 1: Bin7SegDecoder-Behavioral" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} { "Info" "ISGN_ENTITY_NAME" "1 Bin7SegDecoder " "Found entity 1: Bin7SegDecoder" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119663 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FreqDivider.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FreqDivider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FreqDivider-Behavioral " "Found design unit 1: FreqDivider-Behavioral" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} { "Info" "ISGN_ENTITY_NAME" "1 FreqDivider " "Found entity 1: FreqDivider" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119663 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "CounterDemo " "Elaborating entity \"CounterDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679318119688 ""}
-{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst3 " "Block or symbol \"NOT\" of instance \"inst3\" overlaps another block or symbol" { } { { "CounterDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 224 432 480 256 "inst3" "" } } } } } 0 275011 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "Analysis & Synthesis" 0 -1 1679318119688 ""}
-{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "Bin7SegDecoder hex " "Block or symbol \"Bin7SegDecoder\" of instance \"hex\" overlaps another block or symbol" { } { { "CounterDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 192 672 880 272 "hex" "" } } } } } 0 275011 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "Analysis & Synthesis" 0 -1 1679318119688 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Bin7SegDecoder Bin7SegDecoder:hex " "Elaborating entity \"Bin7SegDecoder\" for hierarchy \"Bin7SegDecoder:hex\"" { } { { "CounterDemo.bdf" "hex" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 192 672 880 272 "hex" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318119690 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CounterUpDown4 CounterUpDown4:inst " "Elaborating entity \"CounterUpDown4\" for hierarchy \"CounterUpDown4:inst\"" { } { { "CounterDemo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 192 488 664 304 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318119691 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FreqDivider FreqDivider:inst1 " "Elaborating entity \"FreqDivider\" for hierarchy \"FreqDivider:inst1\"" { } { { "CounterDemo.bdf" "inst1" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 152 328 472 232 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318119691 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1679318120030 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1679318120333 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318120333 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "82 " "Implemented 82 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1679318120349 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1679318120349 ""} { "Info" "ICUT_CUT_TM_LCELLS" "72 " "Implemented 72 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1679318120349 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1679318120349 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "446 " "Peak virtual memory: 446 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318120352 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:15:20 2023 " "Processing ended: Mon Mar 20 13:15:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318120352 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318120352 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318120352 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318120352 ""}
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.rdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map.rdb
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map_bb.cdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map_bb.cdb
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map_bb.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map_bb.hdb
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map_bb.logdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.pre_map.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.root_partition.map.reg_db.cdb
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.routing.rdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.rtlv.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.smart_action.txt b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.smart_action.txt
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-DONE
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.sta.qmsg b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.sta.qmsg
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-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318131335 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318131336 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:15:31 2023 " "Processing started: Mon Mar 20 13:15:31 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318131336 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131336 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta CounterDemo -c CounterDemo " "Command: quartus_sta CounterDemo -c CounterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131336 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1679318131355 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1679318131412 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1679318131412 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131454 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131454 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "CounterDemo.sdc " "Synopsys Design Constraints File file not found: 'CounterDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1679318131740 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131740 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name FreqDivider:inst1\|clkOut FreqDivider:inst1\|clkOut " "create_clock -period 1.000 -name FreqDivider:inst1\|clkOut FreqDivider:inst1\|clkOut" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1679318131740 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1679318131740 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131740 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131741 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131741 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1679318131741 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1679318131744 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679318131749 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679318131749 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.122 " "Worst-case setup slack is -4.122" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.122 -69.260 CLOCK_50 " " -4.122 -69.260 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.839 -1.988 FreqDivider:inst1\|clkOut " " -0.839 -1.988 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131750 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.408 " "Worst-case hold slack is 0.408" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.408 0.000 FreqDivider:inst1\|clkOut " " 0.408 0.000 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.652 0.000 CLOCK_50 " " 0.652 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131750 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318131751 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318131751 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -5.140 FreqDivider:inst1\|clkOut " " -1.285 -5.140 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131752 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131752 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679318131764 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1679318131776 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1679318131929 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131942 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679318131944 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679318131944 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.714 " "Worst-case setup slack is -3.714" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.714 -59.180 CLOCK_50 " " -3.714 -59.180 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.650 -1.486 FreqDivider:inst1\|clkOut " " -0.650 -1.486 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131944 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.364 " "Worst-case hold slack is 0.364" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.364 0.000 FreqDivider:inst1\|clkOut " " 0.364 0.000 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.596 0.000 CLOCK_50 " " 0.596 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131945 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131945 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318131946 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318131947 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131948 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131948 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131948 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -5.140 FreqDivider:inst1\|clkOut " " -1.285 -5.140 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131948 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131948 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679318131961 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131998 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679318131998 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679318131998 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.587 " "Worst-case setup slack is -1.587" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131999 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131999 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.587 -18.604 CLOCK_50 " " -1.587 -18.604 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131999 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.109 0.000 FreqDivider:inst1\|clkOut " " 0.109 0.000 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131999 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131999 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.188 " "Worst-case hold slack is 0.188" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132000 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132000 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.188 0.000 FreqDivider:inst1\|clkOut " " 0.188 0.000 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132000 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.297 0.000 CLOCK_50 " " 0.297 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132000 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318132000 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318132001 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318132002 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132003 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132003 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -38.022 CLOCK_50 " " -3.000 -38.022 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132003 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -4.000 FreqDivider:inst1\|clkOut " " -1.000 -4.000 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132003 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318132003 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679318132228 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679318132228 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "538 " "Peak virtual memory: 538 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318132244 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:15:32 2023 " "Processing ended: Mon Mar 20 13:15:32 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318132244 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318132244 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318132244 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1679318132244 ""}
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.sta.rdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.sta.rdb
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.sta_cmp.7_slow_1200mv_85c.tdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.tis_db_list.ddb
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index 73e5ec9..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index 80662d1..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index 439080f..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index 79d39a0..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.tmw_info b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.tmw_info
deleted file mode 100644
index ded09fb..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.tmw_info
+++ /dev/null
@@ -1,7 +0,0 @@
-start_full_compilation:s:00:00:19
-start_analysis_synthesis:s:00:00:06-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:08-start_full_compilation
-start_assembler:s:00:00:02-start_full_compilation
-start_timing_analyzer:s:00:00:02-start_full_compilation
-start_eda_netlist_writer:s:00:00:01-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.vpr.ammdb b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.vpr.ammdb
deleted file mode 100644
index e06cb66..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo_partition_pins.json b/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo_partition_pins.json
deleted file mode 100644
index 1b542e3..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo_partition_pins.json
+++ /dev/null
@@ -1,49 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "HEX0[6]",
- "strict" : false
- },
- {
- "name" : "HEX0[5]",
- "strict" : false
- },
- {
- "name" : "HEX0[4]",
- "strict" : false
- },
- {
- "name" : "HEX0[3]",
- "strict" : false
- },
- {
- "name" : "HEX0[2]",
- "strict" : false
- },
- {
- "name" : "HEX0[1]",
- "strict" : false
- },
- {
- "name" : "HEX0[0]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- },
- {
- "name" : "KEY[1]",
- "strict" : false
- },
- {
- "name" : "CLOCK_50",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/db/prev_cmp_CounterDemo.qmsg b/1ano/2semestre/lsd/pratica04/CounterDemo/db/prev_cmp_CounterDemo.qmsg
deleted file mode 100644
index af0a0ce..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/db/prev_cmp_CounterDemo.qmsg
+++ /dev/null
@@ -1,4 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318059500 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus Prime " "Running Quartus Prime Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318059500 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:14:19 2023 " "Processing started: Mon Mar 20 13:14:19 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318059500 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1679318059500 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CounterDemo -c CounterDemo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd " "Command: quartus_map --read_settings_files=on --write_settings_files=off CounterDemo -c CounterDemo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1679318059500 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus Prime " "Quartus Prime Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "696 " "Peak virtual memory: 696 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318059832 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:14:19 2023 " "Processing ended: Mon Mar 20 13:14:19 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318059832 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318059832 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318059832 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1679318059832 ""}
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/README b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.db_info b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.db_info
deleted file mode 100644
index 63a1566..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Thu Mar 16 16:46:48 2023
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.ammdb
deleted file mode 100644
index 67f6ffd..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.cdb
deleted file mode 100644
index d87b28f..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.hdb
deleted file mode 100644
index 955b97a..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.cmp.rcfdb
deleted file mode 100644
index 5aed546..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.cdb
deleted file mode 100644
index 4c58de0..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.dpi
deleted file mode 100644
index 0da534b..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.hbdb.cdb
deleted file mode 100644
index 2920f48..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.hbdb.hdb
deleted file mode 100644
index 2f40e25..0000000
Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.hdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.root_partition.map.kpt
deleted file mode 100644
index 02f009d..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.rrp.hdb b/1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.rrp.hdb
deleted file mode 100644
index c1c61fb..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.asm.rpt b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.asm.rpt
deleted file mode 100644
index c508e70..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for CounterDemo
-Mon Mar 20 13:15:30 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: CounterDemo.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Mon Mar 20 13:15:30 2023 ;
-; Revision Name ; CounterDemo ;
-; Top-level Entity Name ; CounterDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+--------------------------------------------------------------------------------------------------------+
-; File Name ;
-+--------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sof ;
-+--------------------------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------+
-; Assembler Device Options: CounterDemo.sof ;
-+----------------+--------------------------+
-; Option ; Setting ;
-+----------------+--------------------------+
-; JTAG usercode ; 0x0056A839 ;
-; Checksum ; 0x0056A839 ;
-+----------------+--------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Mon Mar 20 13:15:29 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 364 megabytes
- Info: Processing ended: Mon Mar 20 13:15:30 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.cdf b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.cdf
deleted file mode 100644
index 0717c53..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.cdf
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition */
-JedecChain;
- FileRevision(JESD32A);
- DefaultMfr(6E);
-
- P ActionCode(Cfg)
- Device PartName(EP4CE115F29) Path("/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/") File("CounterDemo.sof") MfrSpec(OpMask(1));
-
-ChainEnd;
-
-AlteraBegin;
- ChainType(JTAG);
-AlteraEnd;
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.done b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.done
deleted file mode 100644
index 77f79b9..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.done
+++ /dev/null
@@ -1 +0,0 @@
-Mon Mar 20 13:15:33 2023
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.eda.rpt b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.eda.rpt
deleted file mode 100644
index ab4943a..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.eda.rpt
+++ /dev/null
@@ -1,94 +0,0 @@
-EDA Netlist Writer report for CounterDemo
-Mon Mar 20 13:15:33 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Mon Mar 20 13:15:33 2023 ;
-; Revision Name ; CounterDemo ;
-; Top-level Entity Name ; CounterDemo ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+---------------------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+---------------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/CounterDemo.vho ;
-+---------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Mon Mar 20 13:15:33 2023
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file CounterDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 612 megabytes
- Info: Processing ended: Mon Mar 20 13:15:33 2023
- Info: Elapsed time: 00:00:00
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.fit.rpt b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.fit.rpt
deleted file mode 100644
index 433d25b..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.fit.rpt
+++ /dev/null
@@ -1,2676 +0,0 @@
-Fitter report for CounterDemo
-Mon Mar 20 13:15:28 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Control Signals
- 22. Global & Other Fast Signals
- 23. Routing Usage Summary
- 24. LAB Logic Elements
- 25. LAB-wide Signals
- 26. LAB Signals Sourced
- 27. LAB Signals Sourced Out
- 28. LAB Distinct Inputs
- 29. I/O Rules Summary
- 30. I/O Rules Details
- 31. I/O Rules Matrix
- 32. Fitter Device Options
- 33. Operating Settings and Conditions
- 34. Estimated Delay Added for Hold Timing Summary
- 35. Estimated Delay Added for Hold Timing Details
- 36. Fitter Messages
- 37. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Mon Mar 20 13:15:28 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; CounterDemo ;
-; Top-level Entity Name ; CounterDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 73 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 72 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 37 / 114,480 ( < 1 % ) ;
-; Total registers ; 37 ;
-; Total pins ; 10 / 529 ( 2 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.1% ;
-; Processors 3-4 ; 0.1% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[0] ; PIN_M23 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[0] ; PIN_E21 ; QSF Assignment ;
-; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
-; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
-; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[0] ; PIN_G19 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[1] ; PIN_F19 ; QSF Assignment ;
-; Location ; ; ; LEDR[2] ; PIN_E19 ; QSF Assignment ;
-; Location ; ; ; LEDR[3] ; PIN_F21 ; QSF Assignment ;
-; Location ; ; ; LEDR[4] ; PIN_F18 ; QSF Assignment ;
-; Location ; ; ; LEDR[5] ; PIN_E18 ; QSF Assignment ;
-; Location ; ; ; LEDR[6] ; PIN_J19 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_H19 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; SW[10] ; PIN_AC24 ; QSF Assignment ;
-; Location ; ; ; SW[11] ; PIN_AB24 ; QSF Assignment ;
-; Location ; ; ; SW[12] ; PIN_AB23 ; QSF Assignment ;
-; Location ; ; ; SW[13] ; PIN_AA24 ; QSF Assignment ;
-; Location ; ; ; SW[14] ; PIN_AA23 ; QSF Assignment ;
-; Location ; ; ; SW[15] ; PIN_AA22 ; QSF Assignment ;
-; Location ; ; ; SW[16] ; PIN_Y24 ; QSF Assignment ;
-; Location ; ; ; SW[17] ; PIN_Y23 ; QSF Assignment ;
-; Location ; ; ; SW[1] ; PIN_AC28 ; QSF Assignment ;
-; Location ; ; ; SW[2] ; PIN_AC27 ; QSF Assignment ;
-; Location ; ; ; SW[3] ; PIN_AD27 ; QSF Assignment ;
-; Location ; ; ; SW[4] ; PIN_AB27 ; QSF Assignment ;
-; Location ; ; ; SW[5] ; PIN_AC26 ; QSF Assignment ;
-; Location ; ; ; SW[6] ; PIN_AD26 ; QSF Assignment ;
-; Location ; ; ; SW[7] ; PIN_AB26 ; QSF Assignment ;
-; Location ; ; ; SW[8] ; PIN_AC25 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AB25 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 142 ) ; 0.00 % ( 0 / 142 ) ; 0.00 % ( 0 / 142 ) ;
-; -- Achieved ; 0.00 % ( 0 / 142 ) ; 0.00 % ( 0 / 142 ) ; 0.00 % ( 0 / 142 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+--------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 132 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.pin.
-
-
-+----------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+------------------------+
-; Total logic elements ; 73 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 36 ;
-; -- Register only ; 1 ;
-; -- Combinational with a register ; 36 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 19 ;
-; -- 3 input functions ; 6 ;
-; -- <=2 input functions ; 47 ;
-; -- Register only ; 1 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 38 ;
-; -- arithmetic mode ; 34 ;
-; ; ;
-; Total registers* ; 37 / 117,053 ( < 1 % ) ;
-; -- Dedicated logic registers ; 37 / 114,480 ( < 1 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 7 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 10 / 529 ( 2 % ) ;
-; -- Clock pins ; 1 / 7 ( 14 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 2 ;
-; -- Global clocks ; 2 / 20 ( 10 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.3% / 0.4% / 0.3% ;
-; Maximum fan-out ; 33 ;
-; Highest non-global fan-out ; 12 ;
-; Total fan-out ; 289 ;
-; Average fan-out ; 2.04 ;
-+---------------------------------------------+------------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 73 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 36 ; 0 ;
-; -- Register only ; 1 ; 0 ;
-; -- Combinational with a register ; 36 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 19 ; 0 ;
-; -- 3 input functions ; 6 ; 0 ;
-; -- <=2 input functions ; 47 ; 0 ;
-; -- Register only ; 1 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 38 ; 0 ;
-; -- arithmetic mode ; 34 ; 0 ;
-; ; ; ;
-; Total registers ; 37 ; 0 ;
-; -- Dedicated logic registers ; 37 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 7 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 10 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; Clock control block ; 2 / 24 ( 8 % ) ; 0 / 24 ( 0 % ) ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 284 ; 5 ;
-; -- Registered Connections ; 108 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 3 ; 0 ;
-; -- Output Ports ; 7 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+-----------------------+--------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; CLOCK_50 ; Y2 ; 2 ; 0 ; 36 ; 14 ; 33 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; KEY[1] ; M21 ; 6 ; 115 ; 53 ; 14 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; HEX0[0] ; G18 ; 7 ; 69 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[1] ; F22 ; 7 ; 107 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[2] ; E17 ; 7 ; 67 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[3] ; L26 ; 6 ; 115 ; 50 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[4] ; L25 ; 6 ; 115 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[5] ; J22 ; 6 ; 115 ; 67 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; HEX0[6] ; H22 ; 6 ; 115 ; 69 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+-----------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+-----------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+-----------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 1 / 63 ( 2 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 1 / 65 ( 2 % ) ; 2.5V ; -- ;
-; 6 ; 6 / 58 ( 10 % ) ; 2.5V ; -- ;
-; 7 ; 3 / 72 ( 4 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+-----------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA23 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA24 ; 279 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB24 ; 274 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB25 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB26 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB27 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC25 ; 272 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC26 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC27 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC28 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD27 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E18 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F22 ; 409 ; 7 ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; HEX0[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G19 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; HEX0[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; HEX0[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; HEX0[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; L26 ; 363 ; 6 ; HEX0[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; KEY[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; CLOCK_50 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y24 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; HEX0[6] ; Incomplete set of assignments ;
-; HEX0[5] ; Incomplete set of assignments ;
-; HEX0[4] ; Incomplete set of assignments ;
-; HEX0[3] ; Incomplete set of assignments ;
-; HEX0[2] ; Incomplete set of assignments ;
-; HEX0[1] ; Incomplete set of assignments ;
-; HEX0[0] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-; KEY[1] ; Incomplete set of assignments ;
-; CLOCK_50 ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------+----------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------+----------------+--------------+
-; |CounterDemo ; 73 (0) ; 37 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 ; 0 ; 36 (0) ; 1 (0) ; 36 (0) ; |CounterDemo ; CounterDemo ; work ;
-; |Bin7SegDecoder:hex| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; |CounterDemo|Bin7SegDecoder:hex ; Bin7SegDecoder ; work ;
-; |CounterUpDown4:inst| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |CounterDemo|CounterUpDown4:inst ; CounterUpDown4 ; work ;
-; |FreqDivider:inst1| ; 61 (61) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (28) ; 1 (1) ; 32 (32) ; |CounterDemo|FreqDivider:inst1 ; FreqDivider ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------+----------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+----------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+----------+----------+---------------+---------------+-----------------------+-----+------+
-; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; KEY[1] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; CLOCK_50 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
-+----------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+-----------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+-----------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+-----------------------------------------+-------------------+---------+
-; SW[0] ; ; ;
-; - CounterUpDown4:inst|s_count[1]~5 ; 0 ; 6 ;
-; - CounterUpDown4:inst|s_count[3]~9 ; 0 ; 6 ;
-; - CounterUpDown4:inst|s_count[2]~7 ; 0 ; 6 ;
-; KEY[1] ; ; ;
-; - CounterUpDown4:inst|s_count[0] ; 1 ; 6 ;
-; - CounterUpDown4:inst|s_count[1] ; 1 ; 6 ;
-; - CounterUpDown4:inst|s_count[3] ; 1 ; 6 ;
-; - CounterUpDown4:inst|s_count[2] ; 1 ; 6 ;
-; CLOCK_50 ; ; ;
-+-----------------------------------------+-------------------+---------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+--------------------------+---------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+--------------------------+---------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_Y2 ; 33 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ;
-; FreqDivider:inst1|clkOut ; FF_X54_Y3_N25 ; 4 ; Clock ; yes ; Global Clock ; GCLK18 ; -- ;
-; KEY[1] ; PIN_M21 ; 4 ; Async. clear ; no ; -- ; -- ; -- ;
-+--------------------------+---------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals ;
-+--------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+--------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_Y2 ; 33 ; 0 ; Global Clock ; GCLK4 ; -- ;
-; FreqDivider:inst1|clkOut ; FF_X54_Y3_N25 ; 4 ; 1 ; Global Clock ; GCLK18 ; -- ;
-+--------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-
-
-+------------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+------------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+------------------------+
-; Block interconnects ; 73 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 4 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 25 / 209,544 ( < 1 % ) ;
-; Direct links ; 41 / 342,891 ( < 1 % ) ;
-; Global clocks ; 2 / 20 ( 10 % ) ;
-; Local interconnects ; 41 / 119,088 ( < 1 % ) ;
-; R24 interconnects ; 4 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 38 / 289,782 ( < 1 % ) ;
-+-----------------------+------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+---------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 10.43) ; Number of LABs (Total = 7) ;
-+---------------------------------------------+-----------------------------+
-; 1 ; 0 ;
-; 2 ; 1 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 1 ;
-; 6 ; 1 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 1 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 3 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------------------------------+
-; LAB-wide Signals ;
-+------------------------------------+-----------------------------+
-; LAB-wide Signals (Average = 1.14) ; Number of LABs (Total = 7) ;
-+------------------------------------+-----------------------------+
-; 1 Async. clear ; 1 ;
-; 1 Clock ; 7 ;
-+------------------------------------+-----------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+----------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 15.57) ; Number of LABs (Total = 7) ;
-+----------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-; 9 ; 0 ;
-; 10 ; 1 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 1 ;
-; 16 ; 0 ;
-; 17 ; 0 ;
-; 18 ; 0 ;
-; 19 ; 0 ;
-; 20 ; 0 ;
-; 21 ; 1 ;
-; 22 ; 0 ;
-; 23 ; 0 ;
-; 24 ; 0 ;
-; 25 ; 1 ;
-; 26 ; 0 ;
-; 27 ; 1 ;
-+----------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 8.29) ; Number of LABs (Total = 7) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 1 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 1 ;
-; 6 ; 2 ;
-; 7 ; 1 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 2 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 9.43) ; Number of LABs (Total = 7) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 2 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 1 ;
-; 10 ; 0 ;
-; 11 ; 1 ;
-; 12 ; 1 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-; 17 ; 0 ;
-; 18 ; 0 ;
-; 19 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 10 ; 10 ; 0 ; 0 ; 10 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 3 ; 7 ; 0 ; 3 ; 0 ; 0 ; 7 ; 0 ; 10 ; 10 ; 10 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 10 ; 0 ; 0 ; 10 ; 10 ; 0 ; 0 ; 10 ; 10 ; 10 ; 10 ; 10 ; 10 ; 3 ; 10 ; 10 ; 10 ; 7 ; 3 ; 10 ; 7 ; 10 ; 10 ; 3 ; 10 ; 0 ; 0 ; 0 ; 10 ; 10 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; HEX0[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; HEX0[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; CLOCK_50 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary ;
-+-----------------+----------------------+-------------------+
-; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-; CLOCK_50 ; CLOCK_50 ; 4.2 ;
-+-----------------+----------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
-
-
-+--------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details ;
-+---------------------------------+--------------------------+-------------------+
-; Source Register ; Destination Register ; Delay Added in ns ;
-+---------------------------------+--------------------------+-------------------+
-; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 4.194 ;
-; FreqDivider:inst1|s_counter[31] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[29] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[22] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[21] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[20] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[19] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[17] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[16] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[15] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[18] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[13] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|clkOut ; 1.701 ;
-; FreqDivider:inst1|s_counter[10] ; FreqDivider:inst1|clkOut ; 1.701 ;
-+---------------------------------+--------------------------+-------------------+
-Note: This table only shows the top 33 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "CounterDemo"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'CounterDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
-Info (176353): Automatically promoted node FreqDivider:inst1|clkOut File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd Line: 7
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
- Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
- Info (176357): Destination node FreqDivider:inst1|clkOut~3 File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd Line: 7
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X57_Y11
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.06 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 515 warnings
- Info: Peak virtual memory: 1158 megabytes
- Info: Processing ended: Mon Mar 20 13:15:28 2023
- Info: Elapsed time: 00:00:08
- Info: Total CPU time (on all processors): 00:00:13
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.fit.smsg b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.fit.summary b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.fit.summary
deleted file mode 100644
index 911261d..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Mon Mar 20 13:15:28 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : CounterDemo
-Top-level Entity Name : CounterDemo
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 73 / 114,480 ( < 1 % )
- Total combinational functions : 72 / 114,480 ( < 1 % )
- Dedicated logic registers : 37 / 114,480 ( < 1 % )
-Total registers : 37
-Total pins : 10 / 529 ( 2 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.flow.rpt b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.flow.rpt
deleted file mode 100644
index 849fd17..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.flow.rpt
+++ /dev/null
@@ -1,136 +0,0 @@
-Flow report for CounterDemo
-Mon Mar 20 13:15:33 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Mon Mar 20 13:15:33 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; CounterDemo ;
-; Top-level Entity Name ; CounterDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 73 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 72 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 37 / 114,480 ( < 1 % ) ;
-; Total registers ; 37 ;
-; Total pins ; 10 / 529 ( 2 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/20/2023 13:15:15 ;
-; Main task ; Compilation ;
-; Revision Name ; CounterDemo ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 198516037997543.167931811520291 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 440 MB ; 00:00:13 ;
-; Fitter ; 00:00:08 ; 1.0 ; 1158 MB ; 00:00:13 ;
-; Assembler ; 00:00:01 ; 1.0 ; 364 MB ; 00:00:02 ;
-; Timing Analyzer ; 00:00:01 ; 1.0 ; 538 MB ; 00:00:01 ;
-; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 612 MB ; 00:00:00 ;
-; Total ; 00:00:16 ; -- ; -- ; 00:00:29 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off CounterDemo -c CounterDemo
-quartus_fit --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo
-quartus_asm --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo
-quartus_sta CounterDemo -c CounterDemo
-quartus_eda --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo
-
-
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.jdi b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.jdi
deleted file mode 100644
index 56d3b93..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.map.rpt b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.map.rpt
deleted file mode 100644
index d6f86bc..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.map.rpt
+++ /dev/null
@@ -1,325 +0,0 @@
-Analysis & Synthesis report for CounterDemo
-Mon Mar 20 13:15:20 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Multiplexer Restructuring Statistics (Restructuring Performed)
- 10. Post-Synthesis Netlist Statistics for Top Partition
- 11. Elapsed Time Per Partition
- 12. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Mon Mar 20 13:15:20 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; CounterDemo ;
-; Top-level Entity Name ; CounterDemo ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 72 ;
-; Total combinational functions ; 72 ;
-; Dedicated logic registers ; 37 ;
-; Total registers ; 37 ;
-; Total pins ; 10 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; CounterDemo ; CounterDemo ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.0% ;
-; Processors 3-4 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------+---------+
-; CounterUpDown4.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd ; ;
-; CounterDemo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf ; ;
-; Bin7SegDecoder.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd ; ;
-; FreqDivider.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd ; ;
-+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------+---------+
-
-
-+--------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+----------------+
-; Resource ; Usage ;
-+---------------------------------------------+----------------+
-; Estimated Total logic elements ; 72 ;
-; ; ;
-; Total combinational functions ; 72 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 19 ;
-; -- 3 input functions ; 6 ;
-; -- <=2 input functions ; 47 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 38 ;
-; -- arithmetic mode ; 34 ;
-; ; ;
-; Total registers ; 37 ;
-; -- Dedicated logic registers ; 37 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 10 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; CLOCK_50~input ;
-; Maximum fan-out ; 33 ;
-; Total fan-out ; 281 ;
-; Average fan-out ; 2.18 ;
-+---------------------------------------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------+----------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------+----------------+--------------+
-; |CounterDemo ; 72 (0) ; 37 (0) ; 0 ; 0 ; 0 ; 0 ; 10 ; 0 ; |CounterDemo ; CounterDemo ; work ;
-; |Bin7SegDecoder:hex| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CounterDemo|Bin7SegDecoder:hex ; Bin7SegDecoder ; work ;
-; |CounterUpDown4:inst| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CounterDemo|CounterUpDown4:inst ; CounterUpDown4 ; work ;
-; |FreqDivider:inst1| ; 60 (60) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CounterDemo|FreqDivider:inst1 ; FreqDivider ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------+----------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 37 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 4 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------+
-; 16:1 ; 2 bits ; 20 LEs ; 16 LEs ; 4 LEs ; No ; |CounterDemo|Bin7SegDecoder:hex|decOut_n[3] ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 10 ;
-; cycloneiii_ff ; 37 ;
-; CLR ; 4 ;
-; plain ; 33 ;
-; cycloneiii_lcell_comb ; 72 ;
-; arith ; 34 ;
-; 2 data inputs ; 32 ;
-; 3 data inputs ; 2 ;
-; normal ; 38 ;
-; 1 data inputs ; 2 ;
-; 2 data inputs ; 13 ;
-; 3 data inputs ; 4 ;
-; 4 data inputs ; 19 ;
-; ; ;
-; Max LUT depth ; 4.40 ;
-; Average LUT depth ; 3.35 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Mon Mar 20 13:15:14 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CounterDemo -c CounterDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 2 design units, including 1 entities, in source file CounterUpDown4.vhd
- Info (12022): Found design unit 1: CounterUpDown4-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd Line: 15
- Info (12023): Found entity 1: CounterUpDown4 File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd Line: 5
-Info (12021): Found 2 design units, including 1 entities, in source file CounterDown4.vhd
- Info (12022): Found design unit 1: CounterDown4-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd Line: 13
- Info (12023): Found entity 1: CounterDown4 File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd Line: 5
-Info (12021): Found 1 design units, including 1 entities, in source file CounterDemo.bdf
- Info (12023): Found entity 1: CounterDemo
-Info (12021): Found 2 design units, including 1 entities, in source file Bin7SegDecoder.vhd
- Info (12022): Found design unit 1: Bin7SegDecoder-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd Line: 12
- Info (12023): Found entity 1: Bin7SegDecoder File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd Line: 4
-Info (12021): Found 2 design units, including 1 entities, in source file FreqDivider.vhd
- Info (12022): Found design unit 1: FreqDivider-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd Line: 11
- Info (12023): Found entity 1: FreqDivider File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd Line: 5
-Info (12127): Elaborating entity "CounterDemo" for the top level hierarchy
-Warning (275011): Block or symbol "NOT" of instance "inst3" overlaps another block or symbol
-Warning (275011): Block or symbol "Bin7SegDecoder" of instance "hex" overlaps another block or symbol
-Info (12128): Elaborating entity "Bin7SegDecoder" for hierarchy "Bin7SegDecoder:hex"
-Info (12128): Elaborating entity "CounterUpDown4" for hierarchy "CounterUpDown4:inst"
-Info (12128): Elaborating entity "FreqDivider" for hierarchy "FreqDivider:inst1"
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 82 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 3 input pins
- Info (21059): Implemented 7 output pins
- Info (21061): Implemented 72 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings
- Info: Peak virtual memory: 446 megabytes
- Info: Processing ended: Mon Mar 20 13:15:20 2023
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:13
-
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.map.summary b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.map.summary
deleted file mode 100644
index 9b49abd..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Mon Mar 20 13:15:20 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : CounterDemo
-Top-level Entity Name : CounterDemo
-Family : Cyclone IV E
-Total logic elements : 72
- Total combinational functions : 72
- Dedicated logic registers : 37
-Total registers : 37
-Total pins : 10
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.pin b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.pin
deleted file mode 100644
index 772b7b5..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "CounterDemo" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5 :
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-HEX0[2] : E17 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7 :
-VCCIO7 : E20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
-VCCIO7 : E23 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7 :
-GND : F20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7 :
-HEX0[1] : F22 : output : 2.5 V : : 7 : Y
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-HEX0[0] : G18 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
-VCCIO7 : H18 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-HEX0[6] : H22 : output : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7 :
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-HEX0[5] : J22 : output : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-HEX0[4] : L25 : output : 2.5 V : : 6 : Y
-HEX0[3] : L26 : output : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-KEY[1] : M21 : input : 2.5 V : : 6 : Y
-MSEL2 : M22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-CLOCK_50 : Y2 : input : 2.5 V : : 2 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sld b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sta.rpt b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sta.rpt
deleted file mode 100644
index 3a2b916..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sta.rpt
+++ /dev/null
@@ -1,1355 +0,0 @@
-Timing Analyzer report for CounterDemo
-Mon Mar 20 13:15:32 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Setup: 'CLOCK_50'
- 13. Slow 1200mV 85C Model Setup: 'FreqDivider:inst1|clkOut'
- 14. Slow 1200mV 85C Model Hold: 'FreqDivider:inst1|clkOut'
- 15. Slow 1200mV 85C Model Hold: 'CLOCK_50'
- 16. Slow 1200mV 85C Model Metastability Summary
- 17. Slow 1200mV 0C Model Fmax Summary
- 18. Slow 1200mV 0C Model Setup Summary
- 19. Slow 1200mV 0C Model Hold Summary
- 20. Slow 1200mV 0C Model Recovery Summary
- 21. Slow 1200mV 0C Model Removal Summary
- 22. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 23. Slow 1200mV 0C Model Setup: 'CLOCK_50'
- 24. Slow 1200mV 0C Model Setup: 'FreqDivider:inst1|clkOut'
- 25. Slow 1200mV 0C Model Hold: 'FreqDivider:inst1|clkOut'
- 26. Slow 1200mV 0C Model Hold: 'CLOCK_50'
- 27. Slow 1200mV 0C Model Metastability Summary
- 28. Fast 1200mV 0C Model Setup Summary
- 29. Fast 1200mV 0C Model Hold Summary
- 30. Fast 1200mV 0C Model Recovery Summary
- 31. Fast 1200mV 0C Model Removal Summary
- 32. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 33. Fast 1200mV 0C Model Setup: 'CLOCK_50'
- 34. Fast 1200mV 0C Model Setup: 'FreqDivider:inst1|clkOut'
- 35. Fast 1200mV 0C Model Hold: 'FreqDivider:inst1|clkOut'
- 36. Fast 1200mV 0C Model Hold: 'CLOCK_50'
- 37. Fast 1200mV 0C Model Metastability Summary
- 38. Multicorner Timing Analysis Summary
- 39. Board Trace Model Assignments
- 40. Input Transition Times
- 41. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 42. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 43. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 44. Setup Transfers
- 45. Hold Transfers
- 46. Report TCCS
- 47. Report RSKM
- 48. Unconstrained Paths Summary
- 49. Clock Status Summary
- 50. Unconstrained Input Ports
- 51. Unconstrained Output Ports
- 52. Unconstrained Input Ports
- 53. Unconstrained Output Ports
- 54. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; CounterDemo ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.3% ;
-; Processors 3-4 ; 0.3% ;
-+----------------------------+-------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks ;
-+--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
-; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
-+--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
-; CLOCK_50 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;
-; FreqDivider:inst1|clkOut ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { FreqDivider:inst1|clkOut } ;
-+--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Fmax Summary ;
-+------------+-----------------+--------------------------+------------------------------------------------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+--------------------------+------------------------------------------------+
-; 195.24 MHz ; 195.24 MHz ; CLOCK_50 ; ;
-; 543.77 MHz ; 437.64 MHz ; FreqDivider:inst1|clkOut ; limit due to minimum period restriction (tmin) ;
-+------------+-----------------+--------------------------+------------------------------------------------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
-+---------------------------------------------------+
-; Slow 1200mV 85C Model Setup Summary ;
-+--------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+--------+---------------+
-; CLOCK_50 ; -4.122 ; -69.260 ;
-; FreqDivider:inst1|clkOut ; -0.839 ; -1.988 ;
-+--------------------------+--------+---------------+
-
-
-+--------------------------------------------------+
-; Slow 1200mV 85C Model Hold Summary ;
-+--------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+-------+---------------+
-; FreqDivider:inst1|clkOut ; 0.408 ; 0.000 ;
-; CLOCK_50 ; 0.652 ; 0.000 ;
-+--------------------------+-------+---------------+
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
-+--------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+--------+---------------+
-; CLOCK_50 ; -3.000 ; -45.405 ;
-; FreqDivider:inst1|clkOut ; -1.285 ; -5.140 ;
-+--------------------------+--------+---------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Setup: 'CLOCK_50' ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; -4.122 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 5.041 ;
-; -4.116 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 5.034 ;
-; -4.115 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 5.034 ;
-; -4.020 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.939 ;
-; -3.963 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.881 ;
-; -3.939 ; FreqDivider:inst1|s_counter[31] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.857 ;
-; -3.900 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.819 ;
-; -3.899 ; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.817 ;
-; -3.894 ; FreqDivider:inst1|s_counter[21] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.812 ;
-; -3.879 ; FreqDivider:inst1|s_counter[20] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.797 ;
-; -3.870 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.788 ;
-; -3.805 ; FreqDivider:inst1|s_counter[19] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.723 ;
-; -3.788 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.707 ;
-; -3.780 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.698 ;
-; -3.778 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.697 ;
-; -3.766 ; FreqDivider:inst1|s_counter[13] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.685 ;
-; -3.746 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 4.666 ;
-; -3.662 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.581 ;
-; -3.625 ; FreqDivider:inst1|s_counter[29] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.543 ;
-; -3.584 ; FreqDivider:inst1|s_counter[18] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.501 ;
-; -3.584 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.503 ;
-; -3.567 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.485 ;
-; -3.472 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.391 ;
-; -3.431 ; FreqDivider:inst1|s_counter[15] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.350 ;
-; -3.430 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.347 ;
-; -3.428 ; FreqDivider:inst1|s_counter[10] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.347 ;
-; -3.427 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.346 ;
-; -3.347 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.266 ;
-; -3.326 ; FreqDivider:inst1|s_counter[16] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.243 ;
-; -3.301 ; FreqDivider:inst1|s_counter[22] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.218 ;
-; -3.268 ; FreqDivider:inst1|s_counter[17] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.186 ;
-; -3.183 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.102 ;
-; -2.947 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.866 ;
-; -2.899 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.815 ;
-; -2.897 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.813 ;
-; -2.871 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.788 ;
-; -2.869 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.786 ;
-; -2.864 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.781 ;
-; -2.862 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.779 ;
-; -2.857 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.774 ;
-; -2.856 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.775 ;
-; -2.855 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.772 ;
-; -2.835 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.754 ;
-; -2.813 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.732 ;
-; -2.803 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.720 ;
-; -2.801 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.718 ;
-; -2.788 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.707 ;
-; -2.746 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.662 ;
-; -2.744 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.660 ;
-; -2.744 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.663 ;
-; -2.725 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.644 ;
-; -2.722 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.639 ;
-; -2.722 ; FreqDivider:inst1|s_counter[31] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.638 ;
-; -2.720 ; FreqDivider:inst1|s_counter[31] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.636 ;
-; -2.701 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.620 ;
-; -2.700 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.619 ;
-; -2.699 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.615 ;
-; -2.699 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.616 ;
-; -2.697 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.616 ;
-; -2.694 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.612 ;
-; -2.683 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.601 ;
-; -2.683 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.600 ;
-; -2.682 ; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.598 ;
-; -2.681 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.600 ;
-; -2.681 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.598 ;
-; -2.680 ; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.596 ;
-; -2.676 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.593 ;
-; -2.671 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.588 ;
-; -2.667 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.584 ;
-; -2.665 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.582 ;
-; -2.664 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.582 ;
-; -2.664 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.581 ;
-; -2.657 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.574 ;
-; -2.654 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.573 ;
-; -2.653 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.569 ;
-; -2.651 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.567 ;
-; -2.651 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.567 ;
-; -2.649 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.565 ;
-; -2.636 ; FreqDivider:inst1|s_counter[21] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.552 ;
-; -2.634 ; FreqDivider:inst1|s_counter[21] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.550 ;
-; -2.631 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.548 ;
-; -2.621 ; FreqDivider:inst1|s_counter[20] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.537 ;
-; -2.619 ; FreqDivider:inst1|s_counter[20] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.535 ;
-; -2.613 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.532 ;
-; -2.609 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.528 ;
-; -2.604 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.524 ;
-; -2.603 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.520 ;
-; -2.598 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[6] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.513 ;
-; -2.594 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.513 ;
-; -2.592 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.510 ;
-; -2.588 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.505 ;
-; -2.580 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[11] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.497 ;
-; -2.579 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[11] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.495 ;
-; -2.578 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[6] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.494 ;
-; -2.576 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[12] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.493 ;
-; -2.576 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[12] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.492 ;
-; -2.575 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.492 ;
-; -2.575 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.491 ;
-; -2.573 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[11] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.490 ;
-; -2.571 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[6] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.082 ; 3.487 ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Setup: 'FreqDivider:inst1|clkOut' ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; -0.839 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.080 ; 1.757 ;
-; -0.754 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.080 ; 1.672 ;
-; -0.714 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[1] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.080 ; 1.632 ;
-; -0.435 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; 0.331 ; 1.764 ;
-; -0.409 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; 0.331 ; 1.738 ;
-; -0.335 ; CounterUpDown4:inst|s_count[2] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; 0.331 ; 1.664 ;
-; -0.283 ; CounterUpDown4:inst|s_count[2] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.080 ; 1.201 ;
-; -0.235 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[1] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.080 ; 1.153 ;
-; 0.032 ; CounterUpDown4:inst|s_count[3] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.096 ; 0.870 ;
-; 0.153 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[0] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.080 ; 0.765 ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Hold: 'FreqDivider:inst1|clkOut' ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; 0.408 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[0] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.080 ; 0.674 ;
-; 0.453 ; CounterUpDown4:inst|s_count[3] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.096 ; 0.735 ;
-; 0.590 ; CounterUpDown4:inst|s_count[2] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.507 ; 1.283 ;
-; 0.663 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[1] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.080 ; 0.929 ;
-; 0.671 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.507 ; 1.364 ;
-; 0.685 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.507 ; 1.378 ;
-; 0.688 ; CounterUpDown4:inst|s_count[2] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.080 ; 0.954 ;
-; 0.977 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.080 ; 1.243 ;
-; 0.986 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[1] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.080 ; 1.252 ;
-; 0.991 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.080 ; 1.257 ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Hold: 'CLOCK_50' ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; 0.652 ; FreqDivider:inst1|s_counter[15] ; FreqDivider:inst1|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.920 ;
-; 0.653 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.921 ;
-; 0.653 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.921 ;
-; 0.654 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.922 ;
-; 0.655 ; FreqDivider:inst1|s_counter[29] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.922 ;
-; 0.656 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.923 ;
-; 0.656 ; FreqDivider:inst1|s_counter[17] ; FreqDivider:inst1|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.923 ;
-; 0.656 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.924 ;
-; 0.656 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.924 ;
-; 0.657 ; FreqDivider:inst1|s_counter[31] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.924 ;
-; 0.658 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.925 ;
-; 0.658 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.925 ;
-; 0.658 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.926 ;
-; 0.659 ; FreqDivider:inst1|s_counter[10] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.927 ;
-; 0.659 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.927 ;
-; 0.659 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.927 ;
-; 0.661 ; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.928 ;
-; 0.661 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.928 ;
-; 0.661 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.928 ;
-; 0.680 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.948 ;
-; 0.971 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.239 ;
-; 0.971 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.239 ;
-; 0.973 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.241 ;
-; 0.973 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.241 ;
-; 0.973 ; FreqDivider:inst1|s_counter[29] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.240 ;
-; 0.974 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.241 ;
-; 0.975 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.242 ;
-; 0.984 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.252 ;
-; 0.985 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.253 ;
-; 0.986 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.254 ;
-; 0.986 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.254 ;
-; 0.988 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.255 ;
-; 0.988 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.255 ;
-; 0.988 ; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.255 ;
-; 0.989 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.257 ;
-; 0.990 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.258 ;
-; 0.991 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.259 ;
-; 0.993 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.260 ;
-; 0.993 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.260 ;
-; 1.090 ; FreqDivider:inst1|s_counter[15] ; FreqDivider:inst1|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.083 ; 1.359 ;
-; 1.092 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.360 ;
-; 1.092 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.360 ;
-; 1.092 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.360 ;
-; 1.094 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.362 ;
-; 1.094 ; FreqDivider:inst1|s_counter[29] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.361 ;
-; 1.095 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.362 ;
-; 1.096 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.363 ;
-; 1.096 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.363 ;
-; 1.097 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.365 ;
-; 1.097 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.365 ;
-; 1.099 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.367 ;
-; 1.100 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.367 ;
-; 1.101 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.368 ;
-; 1.101 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.368 ;
-; 1.110 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.378 ;
-; 1.111 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.379 ;
-; 1.112 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.380 ;
-; 1.114 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.381 ;
-; 1.114 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.381 ;
-; 1.115 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.383 ;
-; 1.117 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.385 ;
-; 1.119 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.386 ;
-; 1.148 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.415 ;
-; 1.148 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.416 ;
-; 1.153 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.421 ;
-; 1.155 ; FreqDivider:inst1|s_counter[16] ; FreqDivider:inst1|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.421 ;
-; 1.191 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.457 ;
-; 1.197 ; FreqDivider:inst1|s_counter[22] ; FreqDivider:inst1|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.463 ;
-; 1.200 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.466 ;
-; 1.218 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.486 ;
-; 1.218 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.486 ;
-; 1.218 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.486 ;
-; 1.221 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.488 ;
-; 1.222 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.489 ;
-; 1.222 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.489 ;
-; 1.223 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.491 ;
-; 1.223 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.491 ;
-; 1.227 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.494 ;
-; 1.227 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.494 ;
-; 1.236 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.504 ;
-; 1.237 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.505 ;
-; 1.238 ; FreqDivider:inst1|s_counter[10] ; FreqDivider:inst1|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.506 ;
-; 1.238 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.506 ;
-; 1.240 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.507 ;
-; 1.242 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.510 ;
-; 1.243 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.511 ;
-; 1.246 ; FreqDivider:inst1|s_counter[21] ; FreqDivider:inst1|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.514 ;
-; 1.252 ; FreqDivider:inst1|s_counter[20] ; FreqDivider:inst1|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.520 ;
-; 1.273 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.541 ;
-; 1.274 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.542 ;
-; 1.279 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.547 ;
-; 1.317 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.583 ;
-; 1.318 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.585 ;
-; 1.323 ; FreqDivider:inst1|s_counter[22] ; FreqDivider:inst1|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.589 ;
-; 1.326 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.592 ;
-; 1.328 ; FreqDivider:inst1|s_counter[22] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.594 ;
-; 1.344 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.612 ;
-; 1.344 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.612 ;
-; 1.345 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.612 ;
-; 1.346 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.614 ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Fmax Summary ;
-+------------+-----------------+--------------------------+------------------------------------------------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+--------------------------+------------------------------------------------+
-; 212.13 MHz ; 212.13 MHz ; CLOCK_50 ; ;
-; 606.06 MHz ; 437.64 MHz ; FreqDivider:inst1|clkOut ; limit due to minimum period restriction (tmin) ;
-+------------+-----------------+--------------------------+------------------------------------------------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+---------------------------------------------------+
-; Slow 1200mV 0C Model Setup Summary ;
-+--------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+--------+---------------+
-; CLOCK_50 ; -3.714 ; -59.180 ;
-; FreqDivider:inst1|clkOut ; -0.650 ; -1.486 ;
-+--------------------------+--------+---------------+
-
-
-+--------------------------------------------------+
-; Slow 1200mV 0C Model Hold Summary ;
-+--------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+-------+---------------+
-; FreqDivider:inst1|clkOut ; 0.364 ; 0.000 ;
-; CLOCK_50 ; 0.596 ; 0.000 ;
-+--------------------------+-------+---------------+
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-+--------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+--------+---------------+
-; CLOCK_50 ; -3.000 ; -45.405 ;
-; FreqDivider:inst1|clkOut ; -1.285 ; -5.140 ;
-+--------------------------+--------+---------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Setup: 'CLOCK_50' ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; -3.714 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.641 ;
-; -3.665 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.594 ;
-; -3.661 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.590 ;
-; -3.639 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.568 ;
-; -3.586 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.513 ;
-; -3.554 ; FreqDivider:inst1|s_counter[31] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.481 ;
-; -3.526 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.455 ;
-; -3.521 ; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.448 ;
-; -3.505 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.432 ;
-; -3.480 ; FreqDivider:inst1|s_counter[21] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 4.408 ;
-; -3.446 ; FreqDivider:inst1|s_counter[20] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 4.374 ;
-; -3.417 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.344 ;
-; -3.405 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.334 ;
-; -3.391 ; FreqDivider:inst1|s_counter[19] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 4.319 ;
-; -3.378 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.069 ; 4.308 ;
-; -3.364 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.293 ;
-; -3.360 ; FreqDivider:inst1|s_counter[13] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.289 ;
-; -3.308 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.237 ;
-; -3.277 ; FreqDivider:inst1|s_counter[29] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.204 ;
-; -3.202 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.129 ;
-; -3.187 ; FreqDivider:inst1|s_counter[18] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 4.113 ;
-; -3.174 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.103 ;
-; -3.157 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.086 ;
-; -3.081 ; FreqDivider:inst1|s_counter[15] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.010 ;
-; -3.074 ; FreqDivider:inst1|s_counter[10] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.003 ;
-; -3.053 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.979 ;
-; -3.050 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.979 ;
-; -2.982 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.911 ;
-; -2.955 ; FreqDivider:inst1|s_counter[16] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.881 ;
-; -2.939 ; FreqDivider:inst1|s_counter[22] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.865 ;
-; -2.927 ; FreqDivider:inst1|s_counter[17] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.854 ;
-; -2.856 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.785 ;
-; -2.575 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.501 ;
-; -2.573 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.499 ;
-; -2.538 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.467 ;
-; -2.500 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.428 ;
-; -2.498 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.426 ;
-; -2.493 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.421 ;
-; -2.491 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.419 ;
-; -2.467 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.395 ;
-; -2.465 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.393 ;
-; -2.462 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.390 ;
-; -2.460 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.389 ;
-; -2.460 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.388 ;
-; -2.459 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.388 ;
-; -2.447 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.373 ;
-; -2.445 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.371 ;
-; -2.419 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.348 ;
-; -2.417 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.346 ;
-; -2.415 ; FreqDivider:inst1|s_counter[31] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.341 ;
-; -2.413 ; FreqDivider:inst1|s_counter[31] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.339 ;
-; -2.390 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.316 ;
-; -2.387 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.315 ;
-; -2.385 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.313 ;
-; -2.382 ; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.308 ;
-; -2.381 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.310 ;
-; -2.380 ; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.306 ;
-; -2.370 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.298 ;
-; -2.368 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.296 ;
-; -2.366 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.292 ;
-; -2.364 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.290 ;
-; -2.346 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.274 ;
-; -2.344 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.273 ;
-; -2.341 ; FreqDivider:inst1|s_counter[21] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.268 ;
-; -2.341 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.270 ;
-; -2.339 ; FreqDivider:inst1|s_counter[21] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.266 ;
-; -2.338 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.267 ;
-; -2.336 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.262 ;
-; -2.334 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.260 ;
-; -2.329 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.257 ;
-; -2.317 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.246 ;
-; -2.315 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.243 ;
-; -2.308 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.236 ;
-; -2.304 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.233 ;
-; -2.298 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.227 ;
-; -2.297 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[6] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.220 ;
-; -2.292 ; FreqDivider:inst1|s_counter[20] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.219 ;
-; -2.290 ; FreqDivider:inst1|s_counter[20] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.217 ;
-; -2.287 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.216 ;
-; -2.284 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.212 ;
-; -2.282 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.210 ;
-; -2.278 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.204 ;
-; -2.276 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.202 ;
-; -2.268 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[11] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.074 ; 3.193 ;
-; -2.267 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.196 ;
-; -2.267 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.195 ;
-; -2.266 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.195 ;
-; -2.265 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[12] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.074 ; 3.190 ;
-; -2.264 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.074 ; 3.189 ;
-; -2.262 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.188 ;
-; -2.260 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.188 ;
-; -2.252 ; FreqDivider:inst1|s_counter[19] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.179 ;
-; -2.250 ; FreqDivider:inst1|s_counter[19] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.177 ;
-; -2.238 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.069 ; 3.168 ;
-; -2.238 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.167 ;
-; -2.238 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.167 ;
-; -2.237 ; FreqDivider:inst1|s_counter[10] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.165 ;
-; -2.235 ; FreqDivider:inst1|s_counter[10] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.163 ;
-; -2.230 ; FreqDivider:inst1|s_counter[31] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.156 ;
-; -2.228 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.157 ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Setup: 'FreqDivider:inst1|clkOut' ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; -0.650 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.073 ; 1.576 ;
-; -0.577 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.073 ; 1.503 ;
-; -0.549 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[1] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.073 ; 1.475 ;
-; -0.287 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; 0.305 ; 1.591 ;
-; -0.243 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; 0.305 ; 1.547 ;
-; -0.198 ; CounterUpDown4:inst|s_count[2] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; 0.305 ; 1.502 ;
-; -0.147 ; CounterUpDown4:inst|s_count[2] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.073 ; 1.073 ;
-; -0.113 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[1] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.073 ; 1.039 ;
-; 0.124 ; CounterUpDown4:inst|s_count[3] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.089 ; 0.786 ;
-; 0.243 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[0] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.073 ; 0.683 ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Hold: 'FreqDivider:inst1|clkOut' ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; 0.364 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[0] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.073 ; 0.608 ;
-; 0.406 ; CounterUpDown4:inst|s_count[3] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.089 ; 0.666 ;
-; 0.521 ; CounterUpDown4:inst|s_count[2] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.467 ; 1.159 ;
-; 0.595 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.467 ; 1.233 ;
-; 0.605 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[1] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.073 ; 0.849 ;
-; 0.605 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.467 ; 1.243 ;
-; 0.626 ; CounterUpDown4:inst|s_count[2] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.073 ; 0.870 ;
-; 0.889 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[1] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.073 ; 1.133 ;
-; 0.890 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.073 ; 1.134 ;
-; 0.900 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.073 ; 1.144 ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Hold: 'CLOCK_50' ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; 0.596 ; FreqDivider:inst1|s_counter[15] ; FreqDivider:inst1|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.840 ;
-; 0.597 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.841 ;
-; 0.597 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.841 ;
-; 0.599 ; FreqDivider:inst1|s_counter[29] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.842 ;
-; 0.600 ; FreqDivider:inst1|s_counter[31] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.843 ;
-; 0.600 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.843 ;
-; 0.600 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.844 ;
-; 0.601 ; FreqDivider:inst1|s_counter[17] ; FreqDivider:inst1|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.844 ;
-; 0.601 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.845 ;
-; 0.601 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.845 ;
-; 0.602 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.846 ;
-; 0.603 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.846 ;
-; 0.603 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.846 ;
-; 0.603 ; FreqDivider:inst1|s_counter[10] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.847 ;
-; 0.603 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.847 ;
-; 0.603 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.847 ;
-; 0.604 ; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.847 ;
-; 0.605 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.848 ;
-; 0.605 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.848 ;
-; 0.622 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.866 ;
-; 0.883 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.127 ;
-; 0.885 ; FreqDivider:inst1|s_counter[29] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.128 ;
-; 0.886 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.129 ;
-; 0.887 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.131 ;
-; 0.888 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.132 ;
-; 0.888 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.132 ;
-; 0.889 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.133 ;
-; 0.890 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.133 ;
-; 0.890 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.134 ;
-; 0.891 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.135 ;
-; 0.891 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.135 ;
-; 0.892 ; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.135 ;
-; 0.893 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.136 ;
-; 0.893 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.136 ;
-; 0.900 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.144 ;
-; 0.901 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.145 ;
-; 0.902 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.146 ;
-; 0.904 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.147 ;
-; 0.904 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.147 ;
-; 0.979 ; FreqDivider:inst1|s_counter[15] ; FreqDivider:inst1|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 1.225 ;
-; 0.982 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.226 ;
-; 0.982 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.226 ;
-; 0.984 ; FreqDivider:inst1|s_counter[29] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.227 ;
-; 0.985 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.228 ;
-; 0.986 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.230 ;
-; 0.987 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.231 ;
-; 0.989 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.232 ;
-; 0.989 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.232 ;
-; 0.993 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.237 ;
-; 0.996 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.239 ;
-; 0.997 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.241 ;
-; 0.998 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.242 ;
-; 0.999 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.243 ;
-; 1.000 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.243 ;
-; 1.000 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.243 ;
-; 1.000 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.244 ;
-; 1.001 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.245 ;
-; 1.003 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.246 ;
-; 1.003 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.246 ;
-; 1.010 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.254 ;
-; 1.012 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.256 ;
-; 1.014 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.257 ;
-; 1.040 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 1.285 ;
-; 1.050 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.293 ;
-; 1.054 ; FreqDivider:inst1|s_counter[16] ; FreqDivider:inst1|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.297 ;
-; 1.060 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 1.305 ;
-; 1.061 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.304 ;
-; 1.066 ; FreqDivider:inst1|s_counter[22] ; FreqDivider:inst1|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.309 ;
-; 1.092 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.336 ;
-; 1.092 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.336 ;
-; 1.095 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.338 ;
-; 1.096 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.340 ;
-; 1.099 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.342 ;
-; 1.099 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.342 ;
-; 1.103 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.347 ;
-; 1.103 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.347 ;
-; 1.107 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.350 ;
-; 1.109 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.353 ;
-; 1.110 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.353 ;
-; 1.110 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.353 ;
-; 1.110 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.354 ;
-; 1.111 ; FreqDivider:inst1|s_counter[10] ; FreqDivider:inst1|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.355 ;
-; 1.111 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.355 ;
-; 1.113 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.356 ;
-; 1.114 ; FreqDivider:inst1|s_counter[21] ; FreqDivider:inst1|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.358 ;
-; 1.121 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.365 ;
-; 1.122 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.366 ;
-; 1.125 ; FreqDivider:inst1|s_counter[20] ; FreqDivider:inst1|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.369 ;
-; 1.150 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 1.395 ;
-; 1.158 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 1.403 ;
-; 1.170 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 1.415 ;
-; 1.171 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.414 ;
-; 1.176 ; FreqDivider:inst1|s_counter[22] ; FreqDivider:inst1|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.419 ;
-; 1.202 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.446 ;
-; 1.206 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.450 ;
-; 1.207 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.451 ;
-; 1.207 ; FreqDivider:inst1|s_counter[17] ; FreqDivider:inst1|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.450 ;
-; 1.208 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.451 ;
-; 1.209 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.452 ;
-; 1.209 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.452 ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+---------------------------------------------------+
-; Fast 1200mV 0C Model Setup Summary ;
-+--------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+--------+---------------+
-; CLOCK_50 ; -1.587 ; -18.604 ;
-; FreqDivider:inst1|clkOut ; 0.109 ; 0.000 ;
-+--------------------------+--------+---------------+
-
-
-+--------------------------------------------------+
-; Fast 1200mV 0C Model Hold Summary ;
-+--------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+-------+---------------+
-; FreqDivider:inst1|clkOut ; 0.188 ; 0.000 ;
-; CLOCK_50 ; 0.297 ; 0.000 ;
-+--------------------------+-------+---------------+
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-+--------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+--------+---------------+
-; CLOCK_50 ; -3.000 ; -38.022 ;
-; FreqDivider:inst1|clkOut ; -1.000 ; -4.000 ;
-+--------------------------+--------+---------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Setup: 'CLOCK_50' ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; -1.587 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.534 ;
-; -1.586 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.533 ;
-; -1.512 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.459 ;
-; -1.510 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.455 ;
-; -1.466 ; FreqDivider:inst1|s_counter[20] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.411 ;
-; -1.458 ; FreqDivider:inst1|s_counter[21] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.403 ;
-; -1.452 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.399 ;
-; -1.435 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.380 ;
-; -1.423 ; FreqDivider:inst1|s_counter[31] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.368 ;
-; -1.420 ; FreqDivider:inst1|s_counter[19] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.365 ;
-; -1.419 ; FreqDivider:inst1|s_counter[13] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.366 ;
-; -1.401 ; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.346 ;
-; -1.395 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.340 ;
-; -1.365 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.312 ;
-; -1.360 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.307 ;
-; -1.348 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.293 ;
-; -1.340 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.287 ;
-; -1.308 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.255 ;
-; -1.301 ; FreqDivider:inst1|s_counter[18] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.246 ;
-; -1.277 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.224 ;
-; -1.276 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.221 ;
-; -1.265 ; FreqDivider:inst1|s_counter[29] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.210 ;
-; -1.243 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.190 ;
-; -1.241 ; FreqDivider:inst1|s_counter[10] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.188 ;
-; -1.238 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.185 ;
-; -1.235 ; FreqDivider:inst1|s_counter[15] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.182 ;
-; -1.191 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.138 ;
-; -1.144 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.089 ;
-; -1.138 ; FreqDivider:inst1|s_counter[17] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.083 ;
-; -1.115 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 2.062 ;
-; -1.081 ; FreqDivider:inst1|s_counter[22] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.026 ;
-; -1.072 ; FreqDivider:inst1|s_counter[16] ; FreqDivider:inst1|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.017 ;
-; -0.957 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.904 ;
-; -0.954 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.901 ;
-; -0.952 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.899 ;
-; -0.942 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.889 ;
-; -0.941 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.888 ;
-; -0.940 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.887 ;
-; -0.939 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.886 ;
-; -0.909 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.856 ;
-; -0.892 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.839 ;
-; -0.886 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.833 ;
-; -0.881 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.828 ;
-; -0.867 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.814 ;
-; -0.866 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.813 ;
-; -0.865 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.810 ;
-; -0.865 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.812 ;
-; -0.864 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.811 ;
-; -0.863 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.808 ;
-; -0.845 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.792 ;
-; -0.844 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.791 ;
-; -0.843 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.790 ;
-; -0.842 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.789 ;
-; -0.839 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.786 ;
-; -0.839 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.786 ;
-; -0.833 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.780 ;
-; -0.832 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.779 ;
-; -0.829 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.776 ;
-; -0.827 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.774 ;
-; -0.827 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.774 ;
-; -0.826 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.773 ;
-; -0.821 ; FreqDivider:inst1|s_counter[20] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.766 ;
-; -0.821 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.768 ;
-; -0.819 ; FreqDivider:inst1|s_counter[20] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.764 ;
-; -0.818 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.765 ;
-; -0.818 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.765 ;
-; -0.813 ; FreqDivider:inst1|s_counter[21] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.758 ;
-; -0.811 ; FreqDivider:inst1|s_counter[21] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.756 ;
-; -0.810 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.757 ;
-; -0.807 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.754 ;
-; -0.805 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.752 ;
-; -0.801 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[6] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.746 ;
-; -0.797 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.744 ;
-; -0.794 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[11] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.740 ;
-; -0.791 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[12] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.737 ;
-; -0.791 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.738 ;
-; -0.790 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.735 ;
-; -0.789 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.735 ;
-; -0.789 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[6] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.734 ;
-; -0.788 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.733 ;
-; -0.788 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.733 ;
-; -0.788 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|s_counter[6] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.733 ;
-; -0.786 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.731 ;
-; -0.782 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[11] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.728 ;
-; -0.781 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|s_counter[11] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.727 ;
-; -0.780 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.727 ;
-; -0.779 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.726 ;
-; -0.779 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[12] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.725 ;
-; -0.778 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|s_counter[12] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.724 ;
-; -0.777 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.724 ;
-; -0.777 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.723 ;
-; -0.776 ; FreqDivider:inst1|s_counter[12] ; FreqDivider:inst1|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.722 ;
-; -0.775 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.722 ;
-; -0.775 ; FreqDivider:inst1|s_counter[19] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.720 ;
-; -0.774 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.721 ;
-; -0.774 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.721 ;
-; -0.774 ; FreqDivider:inst1|s_counter[13] ; FreqDivider:inst1|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.721 ;
-; -0.773 ; FreqDivider:inst1|s_counter[19] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.718 ;
-; -0.772 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.719 ;
-; -0.772 ; FreqDivider:inst1|s_counter[13] ; FreqDivider:inst1|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.040 ; 1.719 ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Setup: 'FreqDivider:inst1|clkOut' ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; 0.109 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.042 ; 0.836 ;
-; 0.156 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.042 ; 0.789 ;
-; 0.187 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[1] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.042 ; 0.758 ;
-; 0.299 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; 0.152 ; 0.840 ;
-; 0.313 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; 0.152 ; 0.826 ;
-; 0.360 ; CounterUpDown4:inst|s_count[2] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; 0.152 ; 0.779 ;
-; 0.371 ; CounterUpDown4:inst|s_count[2] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.042 ; 0.574 ;
-; 0.394 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[1] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.042 ; 0.551 ;
-; 0.528 ; CounterUpDown4:inst|s_count[3] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.050 ; 0.409 ;
-; 0.586 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[0] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 1.000 ; -0.042 ; 0.359 ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Hold: 'FreqDivider:inst1|clkOut' ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; 0.188 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[0] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.042 ; 0.314 ;
-; 0.204 ; CounterUpDown4:inst|s_count[3] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.050 ; 0.338 ;
-; 0.277 ; CounterUpDown4:inst|s_count[2] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.244 ; 0.605 ;
-; 0.302 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[1] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.042 ; 0.428 ;
-; 0.311 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.244 ; 0.639 ;
-; 0.320 ; CounterUpDown4:inst|s_count[2] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.042 ; 0.446 ;
-; 0.323 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[3] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.244 ; 0.651 ;
-; 0.450 ; CounterUpDown4:inst|s_count[1] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.042 ; 0.576 ;
-; 0.459 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[1] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.042 ; 0.585 ;
-; 0.462 ; CounterUpDown4:inst|s_count[0] ; CounterUpDown4:inst|s_count[2] ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 0.000 ; 0.042 ; 0.588 ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Hold: 'CLOCK_50' ;
-+-------+---------------------------------+---------------------------------+--------------------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+---------------------------------+---------------------------------+--------------------------+-------------+--------------+------------+------------+
-; 0.297 ; FreqDivider:inst1|s_counter[15] ; FreqDivider:inst1|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.423 ;
-; 0.298 ; FreqDivider:inst1|s_counter[31] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.424 ;
-; 0.298 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.424 ;
-; 0.298 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.424 ;
-; 0.299 ; FreqDivider:inst1|s_counter[29] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ;
-; 0.299 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ;
-; 0.299 ; FreqDivider:inst1|s_counter[17] ; FreqDivider:inst1|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ;
-; 0.299 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ;
-; 0.299 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ;
-; 0.300 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.426 ;
-; 0.300 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.426 ;
-; 0.300 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.426 ;
-; 0.300 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.426 ;
-; 0.300 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.426 ;
-; 0.301 ; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.427 ;
-; 0.301 ; FreqDivider:inst1|s_counter[10] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.427 ;
-; 0.301 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.427 ;
-; 0.302 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.428 ;
-; 0.302 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.428 ;
-; 0.310 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.436 ;
-; 0.391 ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; CLOCK_50 ; 0.000 ; 1.651 ; 2.261 ;
-; 0.447 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.573 ;
-; 0.448 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.574 ;
-; 0.448 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.574 ;
-; 0.448 ; FreqDivider:inst1|s_counter[29] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.574 ;
-; 0.448 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.574 ;
-; 0.449 ; FreqDivider:inst1|s_counter[9] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.575 ;
-; 0.449 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.575 ;
-; 0.457 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.583 ;
-; 0.458 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.584 ;
-; 0.458 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.584 ;
-; 0.459 ; FreqDivider:inst1|s_counter[30] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.585 ;
-; 0.459 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.585 ;
-; 0.460 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.586 ;
-; 0.460 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.586 ;
-; 0.460 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.586 ;
-; 0.461 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.587 ;
-; 0.461 ; FreqDivider:inst1|s_counter[8] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.587 ;
-; 0.463 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.589 ;
-; 0.463 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.589 ;
-; 0.507 ; FreqDivider:inst1|s_counter[15] ; FreqDivider:inst1|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 0.635 ;
-; 0.510 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.636 ;
-; 0.510 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.636 ;
-; 0.511 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ;
-; 0.511 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ;
-; 0.511 ; FreqDivider:inst1|s_counter[29] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ;
-; 0.511 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ;
-; 0.512 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.638 ;
-; 0.512 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.638 ;
-; 0.513 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.639 ;
-; 0.514 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.640 ;
-; 0.514 ; FreqDivider:inst1|s_counter[7] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.640 ;
-; 0.514 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.640 ;
-; 0.515 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.641 ;
-; 0.515 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.641 ;
-; 0.523 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.649 ;
-; 0.524 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.650 ;
-; 0.525 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.651 ;
-; 0.525 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.651 ;
-; 0.526 ; FreqDivider:inst1|s_counter[28] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.652 ;
-; 0.526 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.652 ;
-; 0.526 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.652 ;
-; 0.527 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.652 ;
-; 0.528 ; FreqDivider:inst1|s_counter[16] ; FreqDivider:inst1|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.654 ;
-; 0.528 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.654 ;
-; 0.528 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.654 ;
-; 0.529 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.655 ;
-; 0.542 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.668 ;
-; 0.544 ; FreqDivider:inst1|s_counter[22] ; FreqDivider:inst1|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.670 ;
-; 0.545 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.671 ;
-; 0.576 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.702 ;
-; 0.576 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.702 ;
-; 0.577 ; FreqDivider:inst1|s_counter[1] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.703 ;
-; 0.577 ; FreqDivider:inst1|s_counter[27] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.703 ;
-; 0.578 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.704 ;
-; 0.578 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.704 ;
-; 0.578 ; FreqDivider:inst1|s_counter[21] ; FreqDivider:inst1|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.704 ;
-; 0.579 ; FreqDivider:inst1|s_counter[5] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.705 ;
-; 0.579 ; FreqDivider:inst1|s_counter[3] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.705 ;
-; 0.581 ; FreqDivider:inst1|s_counter[23] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.707 ;
-; 0.581 ; FreqDivider:inst1|s_counter[25] ; FreqDivider:inst1|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.707 ;
-; 0.582 ; FreqDivider:inst1|s_counter[20] ; FreqDivider:inst1|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.708 ;
-; 0.588 ; FreqDivider:inst1|s_counter[11] ; FreqDivider:inst1|s_counter[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.713 ;
-; 0.589 ; FreqDivider:inst1|s_counter[0] ; FreqDivider:inst1|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.715 ;
-; 0.590 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.716 ;
-; 0.591 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 0.718 ;
-; 0.591 ; FreqDivider:inst1|s_counter[10] ; FreqDivider:inst1|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.717 ;
-; 0.591 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.717 ;
-; 0.591 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.717 ;
-; 0.592 ; FreqDivider:inst1|s_counter[26] ; FreqDivider:inst1|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.718 ;
-; 0.593 ; FreqDivider:inst1|s_counter[2] ; FreqDivider:inst1|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.719 ;
-; 0.594 ; FreqDivider:inst1|s_counter[14] ; FreqDivider:inst1|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.719 ;
-; 0.594 ; FreqDivider:inst1|s_counter[6] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.720 ;
-; 0.594 ; FreqDivider:inst1|s_counter[4] ; FreqDivider:inst1|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.720 ;
-; 0.597 ; FreqDivider:inst1|s_counter[19] ; FreqDivider:inst1|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.723 ;
-; 0.608 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.734 ;
-; 0.610 ; FreqDivider:inst1|s_counter[22] ; FreqDivider:inst1|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.736 ;
-; 0.611 ; FreqDivider:inst1|s_counter[24] ; FreqDivider:inst1|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.737 ;
-; 0.613 ; FreqDivider:inst1|s_counter[22] ; FreqDivider:inst1|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.739 ;
-; 0.613 ; FreqDivider:inst1|s_counter[22] ; FreqDivider:inst1|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.739 ;
-+-------+---------------------------------+---------------------------------+--------------------------+-------------+--------------+------------+------------+
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+---------------------------+---------+-------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+---------------------------+---------+-------+----------+---------+---------------------+
-; Worst-case Slack ; -4.122 ; 0.188 ; N/A ; N/A ; -3.000 ;
-; CLOCK_50 ; -4.122 ; 0.297 ; N/A ; N/A ; -3.000 ;
-; FreqDivider:inst1|clkOut ; -0.839 ; 0.188 ; N/A ; N/A ; -1.285 ;
-; Design-wide TNS ; -71.248 ; 0.0 ; 0.0 ; 0.0 ; -50.545 ;
-; CLOCK_50 ; -69.260 ; 0.000 ; N/A ; N/A ; -45.405 ;
-; FreqDivider:inst1|clkOut ; -1.988 ; 0.000 ; N/A ; N/A ; -5.140 ;
-+---------------------------+---------+-------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; CLOCK_50 ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ;
-; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ;
-; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ;
-; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ;
-; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ;
-; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ;
-; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ;
-; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ;
-; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ;
-; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ;
-; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ;
-; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ;
-; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Setup Transfers ;
-+--------------------------+--------------------------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+--------------------------+--------------------------+----------+----------+----------+----------+
-; CLOCK_50 ; CLOCK_50 ; 953 ; 0 ; 0 ; 0 ;
-; FreqDivider:inst1|clkOut ; CLOCK_50 ; 1 ; 1 ; 0 ; 0 ;
-; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 10 ; 0 ; 0 ; 0 ;
-+--------------------------+--------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-------------------------------------------------------------------------------------------------+
-; Hold Transfers ;
-+--------------------------+--------------------------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+--------------------------+--------------------------+----------+----------+----------+----------+
-; CLOCK_50 ; CLOCK_50 ; 953 ; 0 ; 0 ; 0 ;
-; FreqDivider:inst1|clkOut ; CLOCK_50 ; 1 ; 1 ; 0 ; 0 ;
-; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; 10 ; 0 ; 0 ; 0 ;
-+--------------------------+--------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 2 ; 2 ;
-; Unconstrained Input Port Paths ; 7 ; 7 ;
-; Unconstrained Output Ports ; 7 ; 7 ;
-; Unconstrained Output Port Paths ; 28 ; 28 ;
-+---------------------------------+-------+------+
-
-
-+--------------------------------------------------------------------------+
-; Clock Status Summary ;
-+--------------------------+--------------------------+------+-------------+
-; Target ; Clock ; Type ; Status ;
-+--------------------------+--------------------------+------+-------------+
-; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ;
-; FreqDivider:inst1|clkOut ; FreqDivider:inst1|clkOut ; Base ; Constrained ;
-+--------------------------+--------------------------+------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Mon Mar 20 13:15:31 2023
-Info: Command: quartus_sta CounterDemo -c CounterDemo
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'CounterDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
- Info (332105): create_clock -period 1.000 -name FreqDivider:inst1|clkOut FreqDivider:inst1|clkOut
- Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1200mV 85C Model
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case setup slack is -4.122
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -4.122 -69.260 CLOCK_50
- Info (332119): -0.839 -1.988 FreqDivider:inst1|clkOut
-Info (332146): Worst-case hold slack is 0.408
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.408 0.000 FreqDivider:inst1|clkOut
- Info (332119): 0.652 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -45.405 CLOCK_50
- Info (332119): -1.285 -5.140 FreqDivider:inst1|clkOut
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.714
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.714 -59.180 CLOCK_50
- Info (332119): -0.650 -1.486 FreqDivider:inst1|clkOut
-Info (332146): Worst-case hold slack is 0.364
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.364 0.000 FreqDivider:inst1|clkOut
- Info (332119): 0.596 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -45.405 CLOCK_50
- Info (332119): -1.285 -5.140 FreqDivider:inst1|clkOut
-Info: Analyzing Fast 1200mV 0C Model
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.587
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -1.587 -18.604 CLOCK_50
- Info (332119): 0.109 0.000 FreqDivider:inst1|clkOut
-Info (332146): Worst-case hold slack is 0.188
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.188 0.000 FreqDivider:inst1|clkOut
- Info (332119): 0.297 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -38.022 CLOCK_50
- Info (332119): -1.000 -4.000 FreqDivider:inst1|clkOut
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 538 megabytes
- Info: Processing ended: Mon Mar 20 13:15:32 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sta.summary b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sta.summary
deleted file mode 100644
index 57d3d1b..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sta.summary
+++ /dev/null
@@ -1,77 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-Type : Slow 1200mV 85C Model Setup 'CLOCK_50'
-Slack : -4.122
-TNS : -69.260
-
-Type : Slow 1200mV 85C Model Setup 'FreqDivider:inst1|clkOut'
-Slack : -0.839
-TNS : -1.988
-
-Type : Slow 1200mV 85C Model Hold 'FreqDivider:inst1|clkOut'
-Slack : 0.408
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Hold 'CLOCK_50'
-Slack : 0.652
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -3.000
-TNS : -45.405
-
-Type : Slow 1200mV 85C Model Minimum Pulse Width 'FreqDivider:inst1|clkOut'
-Slack : -1.285
-TNS : -5.140
-
-Type : Slow 1200mV 0C Model Setup 'CLOCK_50'
-Slack : -3.714
-TNS : -59.180
-
-Type : Slow 1200mV 0C Model Setup 'FreqDivider:inst1|clkOut'
-Slack : -0.650
-TNS : -1.486
-
-Type : Slow 1200mV 0C Model Hold 'FreqDivider:inst1|clkOut'
-Slack : 0.364
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Hold 'CLOCK_50'
-Slack : 0.596
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -3.000
-TNS : -45.405
-
-Type : Slow 1200mV 0C Model Minimum Pulse Width 'FreqDivider:inst1|clkOut'
-Slack : -1.285
-TNS : -5.140
-
-Type : Fast 1200mV 0C Model Setup 'CLOCK_50'
-Slack : -1.587
-TNS : -18.604
-
-Type : Fast 1200mV 0C Model Setup 'FreqDivider:inst1|clkOut'
-Slack : 0.109
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Hold 'FreqDivider:inst1|clkOut'
-Slack : 0.188
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
-Slack : 0.297
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -3.000
-TNS : -38.022
-
-Type : Fast 1200mV 0C Model Minimum Pulse Width 'FreqDivider:inst1|clkOut'
-Slack : -1.000
-TNS : -4.000
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/CounterDemo.sft b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/CounterDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/CounterDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/CounterDemo.vho b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/CounterDemo.vho
deleted file mode 100644
index 597b6cf..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/CounterDemo.vho
+++ /dev/null
@@ -1,2183 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/20/2023 13:15:33"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY ALTERA;
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY CounterDemo IS
- PORT (
- HEX0 : OUT std_logic_vector(6 DOWNTO 0);
- CLOCK_50 : IN std_logic;
- KEY : IN std_logic_vector(1 DOWNTO 1);
- SW : IN std_logic_vector(0 DOWNTO 0)
- );
-END CounterDemo;
-
--- Design Ports Information
--- HEX0[6] => Location: PIN_H22, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[5] => Location: PIN_J22, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[4] => Location: PIN_L25, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[3] => Location: PIN_L26, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[2] => Location: PIN_E17, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[1] => Location: PIN_F22, I/O Standard: 2.5 V, Current Strength: Default
--- HEX0[0] => Location: PIN_G18, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
--- CLOCK_50 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF CounterDemo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_HEX0 : std_logic_vector(6 DOWNTO 0);
-SIGNAL ww_CLOCK_50 : std_logic;
-SIGNAL ww_KEY : std_logic_vector(1 DOWNTO 1);
-SIGNAL ww_SW : std_logic_vector(0 DOWNTO 0);
-SIGNAL \CLOCK_50~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
-SIGNAL \inst1|clkOut~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
-SIGNAL \HEX0[6]~output_o\ : std_logic;
-SIGNAL \HEX0[5]~output_o\ : std_logic;
-SIGNAL \HEX0[4]~output_o\ : std_logic;
-SIGNAL \HEX0[3]~output_o\ : std_logic;
-SIGNAL \HEX0[2]~output_o\ : std_logic;
-SIGNAL \HEX0[1]~output_o\ : std_logic;
-SIGNAL \HEX0[0]~output_o\ : std_logic;
-SIGNAL \CLOCK_50~input_o\ : std_logic;
-SIGNAL \CLOCK_50~inputclkctrl_outclk\ : std_logic;
-SIGNAL \inst1|Add2~0_combout\ : std_logic;
-SIGNAL \inst1|Add2~1\ : std_logic;
-SIGNAL \inst1|Add2~2_combout\ : std_logic;
-SIGNAL \inst1|Add2~3\ : std_logic;
-SIGNAL \inst1|Add2~4_combout\ : std_logic;
-SIGNAL \inst1|Add2~5\ : std_logic;
-SIGNAL \inst1|Add2~6_combout\ : std_logic;
-SIGNAL \inst1|Add2~7\ : std_logic;
-SIGNAL \inst1|Add2~8_combout\ : std_logic;
-SIGNAL \inst1|Add2~9\ : std_logic;
-SIGNAL \inst1|Add2~10_combout\ : std_logic;
-SIGNAL \inst1|Equal0~6_combout\ : std_logic;
-SIGNAL \inst1|Add2~47\ : std_logic;
-SIGNAL \inst1|Add2~48_combout\ : std_logic;
-SIGNAL \inst1|s_counter~0_combout\ : std_logic;
-SIGNAL \inst1|Add2~11\ : std_logic;
-SIGNAL \inst1|Add2~12_combout\ : std_logic;
-SIGNAL \inst1|s_counter~11_combout\ : std_logic;
-SIGNAL \inst1|Add2~13\ : std_logic;
-SIGNAL \inst1|Add2~14_combout\ : std_logic;
-SIGNAL \inst1|Add2~15\ : std_logic;
-SIGNAL \inst1|Add2~16_combout\ : std_logic;
-SIGNAL \inst1|Add2~17\ : std_logic;
-SIGNAL \inst1|Add2~18_combout\ : std_logic;
-SIGNAL \inst1|Add2~19\ : std_logic;
-SIGNAL \inst1|Add2~20_combout\ : std_logic;
-SIGNAL \inst1|Add2~21\ : std_logic;
-SIGNAL \inst1|Add2~22_combout\ : std_logic;
-SIGNAL \inst1|s_counter~10_combout\ : std_logic;
-SIGNAL \inst1|Add2~23\ : std_logic;
-SIGNAL \inst1|Add2~24_combout\ : std_logic;
-SIGNAL \inst1|s_counter~9_combout\ : std_logic;
-SIGNAL \inst1|Add2~25\ : std_logic;
-SIGNAL \inst1|Add2~26_combout\ : std_logic;
-SIGNAL \inst1|s_counter~8_combout\ : std_logic;
-SIGNAL \inst1|Add2~27\ : std_logic;
-SIGNAL \inst1|Add2~28_combout\ : std_logic;
-SIGNAL \inst1|s_counter~3_combout\ : std_logic;
-SIGNAL \inst1|Add2~29\ : std_logic;
-SIGNAL \inst1|Add2~30_combout\ : std_logic;
-SIGNAL \inst1|Add2~31\ : std_logic;
-SIGNAL \inst1|Add2~32_combout\ : std_logic;
-SIGNAL \inst1|s_counter~2_combout\ : std_logic;
-SIGNAL \inst1|Add2~33\ : std_logic;
-SIGNAL \inst1|Add2~34_combout\ : std_logic;
-SIGNAL \inst1|Equal0~8_combout\ : std_logic;
-SIGNAL \inst1|Equal0~9_combout\ : std_logic;
-SIGNAL \inst1|Equal0~10_combout\ : std_logic;
-SIGNAL \inst1|Equal0~5_combout\ : std_logic;
-SIGNAL \inst1|Equal0~3_combout\ : std_logic;
-SIGNAL \inst1|Add2~35\ : std_logic;
-SIGNAL \inst1|Add2~36_combout\ : std_logic;
-SIGNAL \inst1|s_counter~7_combout\ : std_logic;
-SIGNAL \inst1|Add2~37\ : std_logic;
-SIGNAL \inst1|Add2~38_combout\ : std_logic;
-SIGNAL \inst1|s_counter~6_combout\ : std_logic;
-SIGNAL \inst1|Add2~39\ : std_logic;
-SIGNAL \inst1|Add2~40_combout\ : std_logic;
-SIGNAL \inst1|s_counter~5_combout\ : std_logic;
-SIGNAL \inst1|Equal0~2_combout\ : std_logic;
-SIGNAL \inst1|Add2~41\ : std_logic;
-SIGNAL \inst1|Add2~42_combout\ : std_logic;
-SIGNAL \inst1|s_counter~4_combout\ : std_logic;
-SIGNAL \inst1|Add2~49\ : std_logic;
-SIGNAL \inst1|Add2~50_combout\ : std_logic;
-SIGNAL \inst1|Add2~51\ : std_logic;
-SIGNAL \inst1|Add2~52_combout\ : std_logic;
-SIGNAL \inst1|Add2~53\ : std_logic;
-SIGNAL \inst1|Add2~54_combout\ : std_logic;
-SIGNAL \inst1|Equal0~1_combout\ : std_logic;
-SIGNAL \inst1|Add2~55\ : std_logic;
-SIGNAL \inst1|Add2~56_combout\ : std_logic;
-SIGNAL \inst1|Add2~57\ : std_logic;
-SIGNAL \inst1|Add2~58_combout\ : std_logic;
-SIGNAL \inst1|Add2~59\ : std_logic;
-SIGNAL \inst1|Add2~60_combout\ : std_logic;
-SIGNAL \inst1|Add2~61\ : std_logic;
-SIGNAL \inst1|Add2~62_combout\ : std_logic;
-SIGNAL \inst1|Equal0~0_combout\ : std_logic;
-SIGNAL \inst1|Equal0~4_combout\ : std_logic;
-SIGNAL \inst1|Equal0~11_combout\ : std_logic;
-SIGNAL \inst1|Add2~43\ : std_logic;
-SIGNAL \inst1|Add2~44_combout\ : std_logic;
-SIGNAL \inst1|s_counter~1_combout\ : std_logic;
-SIGNAL \inst1|Add2~45\ : std_logic;
-SIGNAL \inst1|Add2~46_combout\ : std_logic;
-SIGNAL \inst1|clkOut~0_combout\ : std_logic;
-SIGNAL \inst1|clkOut~1_combout\ : std_logic;
-SIGNAL \inst1|clkOut~2_combout\ : std_logic;
-SIGNAL \inst1|Equal0~7_combout\ : std_logic;
-SIGNAL \inst1|clkOut~3_combout\ : std_logic;
-SIGNAL \inst1|clkOut~feeder_combout\ : std_logic;
-SIGNAL \inst1|clkOut~q\ : std_logic;
-SIGNAL \inst1|clkOut~clkctrl_outclk\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \inst|s_count[0]~11_combout\ : std_logic;
-SIGNAL \KEY[1]~input_o\ : std_logic;
-SIGNAL \inst|s_count[1]~4_cout\ : std_logic;
-SIGNAL \inst|s_count[1]~5_combout\ : std_logic;
-SIGNAL \inst|s_count[1]~6\ : std_logic;
-SIGNAL \inst|s_count[2]~7_combout\ : std_logic;
-SIGNAL \inst|s_count[2]~8\ : std_logic;
-SIGNAL \inst|s_count[3]~9_combout\ : std_logic;
-SIGNAL \hex|decOut_n[6]~0_combout\ : std_logic;
-SIGNAL \hex|decOut_n[5]~1_combout\ : std_logic;
-SIGNAL \hex|decOut_n[4]~2_combout\ : std_logic;
-SIGNAL \hex|decOut_n[3]~3_combout\ : std_logic;
-SIGNAL \hex|decOut_n[2]~4_combout\ : std_logic;
-SIGNAL \hex|decOut_n[1]~5_combout\ : std_logic;
-SIGNAL \hex|decOut_n[0]~6_combout\ : std_logic;
-SIGNAL \inst1|s_counter\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \inst|s_count\ : std_logic_vector(3 DOWNTO 0);
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-HEX0 <= ww_HEX0;
-ww_CLOCK_50 <= CLOCK_50;
-ww_KEY <= KEY;
-ww_SW <= SW;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
-\CLOCK_50~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLOCK_50~input_o\);
-
-\inst1|clkOut~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst1|clkOut~q\);
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X115_Y69_N2
-\HEX0[6]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \hex|decOut_n[6]~0_combout\,
- devoe => ww_devoe,
- o => \HEX0[6]~output_o\);
-
--- Location: IOOBUF_X115_Y67_N16
-\HEX0[5]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \hex|decOut_n[5]~1_combout\,
- devoe => ww_devoe,
- o => \HEX0[5]~output_o\);
-
--- Location: IOOBUF_X115_Y54_N16
-\HEX0[4]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \hex|decOut_n[4]~2_combout\,
- devoe => ww_devoe,
- o => \HEX0[4]~output_o\);
-
--- Location: IOOBUF_X115_Y50_N2
-\HEX0[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \hex|decOut_n[3]~3_combout\,
- devoe => ww_devoe,
- o => \HEX0[3]~output_o\);
-
--- Location: IOOBUF_X67_Y73_N23
-\HEX0[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \hex|decOut_n[2]~4_combout\,
- devoe => ww_devoe,
- o => \HEX0[2]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N23
-\HEX0[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \hex|decOut_n[1]~5_combout\,
- devoe => ww_devoe,
- o => \HEX0[1]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N23
-\HEX0[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \hex|decOut_n[0]~6_combout\,
- devoe => ww_devoe,
- o => \HEX0[0]~output_o\);
-
--- Location: IOIBUF_X0_Y36_N15
-\CLOCK_50~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_CLOCK_50,
- o => \CLOCK_50~input_o\);
-
--- Location: CLKCTRL_G4
-\CLOCK_50~inputclkctrl\ : cycloneive_clkctrl
--- pragma translate_off
-GENERIC MAP (
- clock_type => "global clock",
- ena_register_mode => "none")
--- pragma translate_on
-PORT MAP (
- inclk => \CLOCK_50~inputclkctrl_INCLK_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- outclk => \CLOCK_50~inputclkctrl_outclk\);
-
--- Location: LCCOMB_X53_Y4_N0
-\inst1|Add2~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~0_combout\ = \inst1|s_counter\(0) $ (VCC)
--- \inst1|Add2~1\ = CARRY(\inst1|s_counter\(0))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011001111001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(0),
- datad => VCC,
- combout => \inst1|Add2~0_combout\,
- cout => \inst1|Add2~1\);
-
--- Location: FF_X53_Y4_N1
-\inst1|s_counter[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(0));
-
--- Location: LCCOMB_X53_Y4_N2
-\inst1|Add2~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~2_combout\ = (\inst1|s_counter\(1) & (!\inst1|Add2~1\)) # (!\inst1|s_counter\(1) & ((\inst1|Add2~1\) # (GND)))
--- \inst1|Add2~3\ = CARRY((!\inst1|Add2~1\) # (!\inst1|s_counter\(1)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(1),
- datad => VCC,
- cin => \inst1|Add2~1\,
- combout => \inst1|Add2~2_combout\,
- cout => \inst1|Add2~3\);
-
--- Location: FF_X53_Y4_N3
-\inst1|s_counter[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(1));
-
--- Location: LCCOMB_X53_Y4_N4
-\inst1|Add2~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~4_combout\ = (\inst1|s_counter\(2) & (\inst1|Add2~3\ $ (GND))) # (!\inst1|s_counter\(2) & (!\inst1|Add2~3\ & VCC))
--- \inst1|Add2~5\ = CARRY((\inst1|s_counter\(2) & !\inst1|Add2~3\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(2),
- datad => VCC,
- cin => \inst1|Add2~3\,
- combout => \inst1|Add2~4_combout\,
- cout => \inst1|Add2~5\);
-
--- Location: FF_X53_Y4_N5
-\inst1|s_counter[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(2));
-
--- Location: LCCOMB_X53_Y4_N6
-\inst1|Add2~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~6_combout\ = (\inst1|s_counter\(3) & (!\inst1|Add2~5\)) # (!\inst1|s_counter\(3) & ((\inst1|Add2~5\) # (GND)))
--- \inst1|Add2~7\ = CARRY((!\inst1|Add2~5\) # (!\inst1|s_counter\(3)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(3),
- datad => VCC,
- cin => \inst1|Add2~5\,
- combout => \inst1|Add2~6_combout\,
- cout => \inst1|Add2~7\);
-
--- Location: FF_X53_Y4_N7
-\inst1|s_counter[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(3));
-
--- Location: LCCOMB_X53_Y4_N8
-\inst1|Add2~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~8_combout\ = (\inst1|s_counter\(4) & (\inst1|Add2~7\ $ (GND))) # (!\inst1|s_counter\(4) & (!\inst1|Add2~7\ & VCC))
--- \inst1|Add2~9\ = CARRY((\inst1|s_counter\(4) & !\inst1|Add2~7\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(4),
- datad => VCC,
- cin => \inst1|Add2~7\,
- combout => \inst1|Add2~8_combout\,
- cout => \inst1|Add2~9\);
-
--- Location: FF_X53_Y4_N9
-\inst1|s_counter[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(4));
-
--- Location: LCCOMB_X53_Y4_N10
-\inst1|Add2~10\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~10_combout\ = (\inst1|s_counter\(5) & (!\inst1|Add2~9\)) # (!\inst1|s_counter\(5) & ((\inst1|Add2~9\) # (GND)))
--- \inst1|Add2~11\ = CARRY((!\inst1|Add2~9\) # (!\inst1|s_counter\(5)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(5),
- datad => VCC,
- cin => \inst1|Add2~9\,
- combout => \inst1|Add2~10_combout\,
- cout => \inst1|Add2~11\);
-
--- Location: FF_X53_Y4_N11
-\inst1|s_counter[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~10_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(5));
-
--- Location: LCCOMB_X54_Y4_N30
-\inst1|Equal0~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Equal0~6_combout\ = (\inst1|s_counter\(2) & (\inst1|s_counter\(0) & \inst1|s_counter\(1)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(2),
- datac => \inst1|s_counter\(0),
- datad => \inst1|s_counter\(1),
- combout => \inst1|Equal0~6_combout\);
-
--- Location: LCCOMB_X53_Y3_N14
-\inst1|Add2~46\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~46_combout\ = (\inst1|s_counter\(23) & (!\inst1|Add2~45\)) # (!\inst1|s_counter\(23) & ((\inst1|Add2~45\) # (GND)))
--- \inst1|Add2~47\ = CARRY((!\inst1|Add2~45\) # (!\inst1|s_counter\(23)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(23),
- datad => VCC,
- cin => \inst1|Add2~45\,
- combout => \inst1|Add2~46_combout\,
- cout => \inst1|Add2~47\);
-
--- Location: LCCOMB_X53_Y3_N16
-\inst1|Add2~48\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~48_combout\ = (\inst1|s_counter\(24) & (\inst1|Add2~47\ $ (GND))) # (!\inst1|s_counter\(24) & (!\inst1|Add2~47\ & VCC))
--- \inst1|Add2~49\ = CARRY((\inst1|s_counter\(24) & !\inst1|Add2~47\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(24),
- datad => VCC,
- cin => \inst1|Add2~47\,
- combout => \inst1|Add2~48_combout\,
- cout => \inst1|Add2~49\);
-
--- Location: LCCOMB_X54_Y3_N14
-\inst1|s_counter~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|s_counter~0_combout\ = (\inst1|Add2~48_combout\ & !\inst1|Equal0~11_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000011110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \inst1|Add2~48_combout\,
- datad => \inst1|Equal0~11_combout\,
- combout => \inst1|s_counter~0_combout\);
-
--- Location: FF_X54_Y3_N15
-\inst1|s_counter[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|s_counter~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(24));
-
--- Location: LCCOMB_X53_Y4_N12
-\inst1|Add2~12\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~12_combout\ = (\inst1|s_counter\(6) & (\inst1|Add2~11\ $ (GND))) # (!\inst1|s_counter\(6) & (!\inst1|Add2~11\ & VCC))
--- \inst1|Add2~13\ = CARRY((\inst1|s_counter\(6) & !\inst1|Add2~11\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010010100001010",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(6),
- datad => VCC,
- cin => \inst1|Add2~11\,
- combout => \inst1|Add2~12_combout\,
- cout => \inst1|Add2~13\);
-
--- Location: LCCOMB_X52_Y4_N16
-\inst1|s_counter~11\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|s_counter~11_combout\ = (\inst1|Add2~12_combout\ & !\inst1|Equal0~11_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000011110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \inst1|Add2~12_combout\,
- datad => \inst1|Equal0~11_combout\,
- combout => \inst1|s_counter~11_combout\);
-
--- Location: FF_X52_Y4_N17
-\inst1|s_counter[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|s_counter~11_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(6));
-
--- Location: LCCOMB_X53_Y4_N14
-\inst1|Add2~14\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~14_combout\ = (\inst1|s_counter\(7) & (!\inst1|Add2~13\)) # (!\inst1|s_counter\(7) & ((\inst1|Add2~13\) # (GND)))
--- \inst1|Add2~15\ = CARRY((!\inst1|Add2~13\) # (!\inst1|s_counter\(7)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(7),
- datad => VCC,
- cin => \inst1|Add2~13\,
- combout => \inst1|Add2~14_combout\,
- cout => \inst1|Add2~15\);
-
--- Location: FF_X53_Y4_N15
-\inst1|s_counter[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~14_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(7));
-
--- Location: LCCOMB_X53_Y4_N16
-\inst1|Add2~16\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~16_combout\ = (\inst1|s_counter\(8) & (\inst1|Add2~15\ $ (GND))) # (!\inst1|s_counter\(8) & (!\inst1|Add2~15\ & VCC))
--- \inst1|Add2~17\ = CARRY((\inst1|s_counter\(8) & !\inst1|Add2~15\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(8),
- datad => VCC,
- cin => \inst1|Add2~15\,
- combout => \inst1|Add2~16_combout\,
- cout => \inst1|Add2~17\);
-
--- Location: FF_X53_Y4_N17
-\inst1|s_counter[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~16_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(8));
-
--- Location: LCCOMB_X53_Y4_N18
-\inst1|Add2~18\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~18_combout\ = (\inst1|s_counter\(9) & (!\inst1|Add2~17\)) # (!\inst1|s_counter\(9) & ((\inst1|Add2~17\) # (GND)))
--- \inst1|Add2~19\ = CARRY((!\inst1|Add2~17\) # (!\inst1|s_counter\(9)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(9),
- datad => VCC,
- cin => \inst1|Add2~17\,
- combout => \inst1|Add2~18_combout\,
- cout => \inst1|Add2~19\);
-
--- Location: FF_X53_Y4_N19
-\inst1|s_counter[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~18_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(9));
-
--- Location: LCCOMB_X53_Y4_N20
-\inst1|Add2~20\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~20_combout\ = (\inst1|s_counter\(10) & (\inst1|Add2~19\ $ (GND))) # (!\inst1|s_counter\(10) & (!\inst1|Add2~19\ & VCC))
--- \inst1|Add2~21\ = CARRY((\inst1|s_counter\(10) & !\inst1|Add2~19\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(10),
- datad => VCC,
- cin => \inst1|Add2~19\,
- combout => \inst1|Add2~20_combout\,
- cout => \inst1|Add2~21\);
-
--- Location: FF_X53_Y4_N21
-\inst1|s_counter[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~20_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(10));
-
--- Location: LCCOMB_X53_Y4_N22
-\inst1|Add2~22\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~22_combout\ = (\inst1|s_counter\(11) & (!\inst1|Add2~21\)) # (!\inst1|s_counter\(11) & ((\inst1|Add2~21\) # (GND)))
--- \inst1|Add2~23\ = CARRY((!\inst1|Add2~21\) # (!\inst1|s_counter\(11)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(11),
- datad => VCC,
- cin => \inst1|Add2~21\,
- combout => \inst1|Add2~22_combout\,
- cout => \inst1|Add2~23\);
-
--- Location: LCCOMB_X54_Y4_N6
-\inst1|s_counter~10\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|s_counter~10_combout\ = (!\inst1|Equal0~11_combout\ & \inst1|Add2~22_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011001100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|Equal0~11_combout\,
- datad => \inst1|Add2~22_combout\,
- combout => \inst1|s_counter~10_combout\);
-
--- Location: FF_X54_Y4_N7
-\inst1|s_counter[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|s_counter~10_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(11));
-
--- Location: LCCOMB_X53_Y4_N24
-\inst1|Add2~24\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~24_combout\ = (\inst1|s_counter\(12) & (\inst1|Add2~23\ $ (GND))) # (!\inst1|s_counter\(12) & (!\inst1|Add2~23\ & VCC))
--- \inst1|Add2~25\ = CARRY((\inst1|s_counter\(12) & !\inst1|Add2~23\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010010100001010",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(12),
- datad => VCC,
- cin => \inst1|Add2~23\,
- combout => \inst1|Add2~24_combout\,
- cout => \inst1|Add2~25\);
-
--- Location: LCCOMB_X54_Y4_N16
-\inst1|s_counter~9\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|s_counter~9_combout\ = (!\inst1|Equal0~11_combout\ & \inst1|Add2~24_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011001100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|Equal0~11_combout\,
- datad => \inst1|Add2~24_combout\,
- combout => \inst1|s_counter~9_combout\);
-
--- Location: FF_X54_Y4_N17
-\inst1|s_counter[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|s_counter~9_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(12));
-
--- Location: LCCOMB_X53_Y4_N26
-\inst1|Add2~26\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~26_combout\ = (\inst1|s_counter\(13) & (!\inst1|Add2~25\)) # (!\inst1|s_counter\(13) & ((\inst1|Add2~25\) # (GND)))
--- \inst1|Add2~27\ = CARRY((!\inst1|Add2~25\) # (!\inst1|s_counter\(13)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(13),
- datad => VCC,
- cin => \inst1|Add2~25\,
- combout => \inst1|Add2~26_combout\,
- cout => \inst1|Add2~27\);
-
--- Location: LCCOMB_X54_Y4_N26
-\inst1|s_counter~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|s_counter~8_combout\ = (\inst1|Add2~26_combout\ & !\inst1|Equal0~11_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000011110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \inst1|Add2~26_combout\,
- datad => \inst1|Equal0~11_combout\,
- combout => \inst1|s_counter~8_combout\);
-
--- Location: FF_X54_Y4_N27
-\inst1|s_counter[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|s_counter~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(13));
-
--- Location: LCCOMB_X53_Y4_N28
-\inst1|Add2~28\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~28_combout\ = (\inst1|s_counter\(14) & (\inst1|Add2~27\ $ (GND))) # (!\inst1|s_counter\(14) & (!\inst1|Add2~27\ & VCC))
--- \inst1|Add2~29\ = CARRY((\inst1|s_counter\(14) & !\inst1|Add2~27\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010010100001010",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(14),
- datad => VCC,
- cin => \inst1|Add2~27\,
- combout => \inst1|Add2~28_combout\,
- cout => \inst1|Add2~29\);
-
--- Location: LCCOMB_X54_Y4_N20
-\inst1|s_counter~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|s_counter~3_combout\ = (!\inst1|Equal0~11_combout\ & \inst1|Add2~28_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011001100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|Equal0~11_combout\,
- datad => \inst1|Add2~28_combout\,
- combout => \inst1|s_counter~3_combout\);
-
--- Location: FF_X54_Y4_N21
-\inst1|s_counter[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|s_counter~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(14));
-
--- Location: LCCOMB_X53_Y4_N30
-\inst1|Add2~30\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~30_combout\ = (\inst1|s_counter\(15) & (!\inst1|Add2~29\)) # (!\inst1|s_counter\(15) & ((\inst1|Add2~29\) # (GND)))
--- \inst1|Add2~31\ = CARRY((!\inst1|Add2~29\) # (!\inst1|s_counter\(15)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(15),
- datad => VCC,
- cin => \inst1|Add2~29\,
- combout => \inst1|Add2~30_combout\,
- cout => \inst1|Add2~31\);
-
--- Location: FF_X53_Y4_N31
-\inst1|s_counter[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~30_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(15));
-
--- Location: LCCOMB_X53_Y3_N0
-\inst1|Add2~32\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~32_combout\ = (\inst1|s_counter\(16) & (\inst1|Add2~31\ $ (GND))) # (!\inst1|s_counter\(16) & (!\inst1|Add2~31\ & VCC))
--- \inst1|Add2~33\ = CARRY((\inst1|s_counter\(16) & !\inst1|Add2~31\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010010100001010",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(16),
- datad => VCC,
- cin => \inst1|Add2~31\,
- combout => \inst1|Add2~32_combout\,
- cout => \inst1|Add2~33\);
-
--- Location: LCCOMB_X54_Y3_N2
-\inst1|s_counter~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|s_counter~2_combout\ = (\inst1|Add2~32_combout\ & !\inst1|Equal0~11_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000010101010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|Add2~32_combout\,
- datad => \inst1|Equal0~11_combout\,
- combout => \inst1|s_counter~2_combout\);
-
--- Location: FF_X54_Y3_N3
-\inst1|s_counter[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|s_counter~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(16));
-
--- Location: LCCOMB_X53_Y3_N2
-\inst1|Add2~34\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~34_combout\ = (\inst1|s_counter\(17) & (!\inst1|Add2~33\)) # (!\inst1|s_counter\(17) & ((\inst1|Add2~33\) # (GND)))
--- \inst1|Add2~35\ = CARRY((!\inst1|Add2~33\) # (!\inst1|s_counter\(17)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(17),
- datad => VCC,
- cin => \inst1|Add2~33\,
- combout => \inst1|Add2~34_combout\,
- cout => \inst1|Add2~35\);
-
--- Location: FF_X53_Y3_N3
-\inst1|s_counter[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(17));
-
--- Location: LCCOMB_X54_Y3_N30
-\inst1|Equal0~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Equal0~8_combout\ = (!\inst1|s_counter\(23) & (\inst1|s_counter\(24) & (\inst1|s_counter\(22) & !\inst1|s_counter\(17))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000001000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(23),
- datab => \inst1|s_counter\(24),
- datac => \inst1|s_counter\(22),
- datad => \inst1|s_counter\(17),
- combout => \inst1|Equal0~8_combout\);
-
--- Location: LCCOMB_X54_Y3_N10
-\inst1|Equal0~9\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Equal0~9_combout\ = (\inst1|s_counter\(14) & (\inst1|s_counter\(16) & (!\inst1|s_counter\(15) & !\inst1|s_counter\(10))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(14),
- datab => \inst1|s_counter\(16),
- datac => \inst1|s_counter\(15),
- datad => \inst1|s_counter\(10),
- combout => \inst1|Equal0~9_combout\);
-
--- Location: LCCOMB_X54_Y3_N28
-\inst1|Equal0~10\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Equal0~10_combout\ = (\inst1|s_counter\(5) & (\inst1|Equal0~8_combout\ & \inst1|Equal0~9_combout\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(5),
- datac => \inst1|Equal0~8_combout\,
- datad => \inst1|Equal0~9_combout\,
- combout => \inst1|Equal0~10_combout\);
-
--- Location: LCCOMB_X52_Y4_N30
-\inst1|Equal0~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Equal0~5_combout\ = (!\inst1|s_counter\(6) & (!\inst1|s_counter\(7) & (\inst1|s_counter\(4) & \inst1|s_counter\(3))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0001000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(6),
- datab => \inst1|s_counter\(7),
- datac => \inst1|s_counter\(4),
- datad => \inst1|s_counter\(3),
- combout => \inst1|Equal0~5_combout\);
-
--- Location: LCCOMB_X54_Y4_N12
-\inst1|Equal0~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Equal0~3_combout\ = (\inst1|s_counter\(11) & (\inst1|s_counter\(12) & (!\inst1|s_counter\(8) & !\inst1|s_counter\(9))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(11),
- datab => \inst1|s_counter\(12),
- datac => \inst1|s_counter\(8),
- datad => \inst1|s_counter\(9),
- combout => \inst1|Equal0~3_combout\);
-
--- Location: LCCOMB_X53_Y3_N4
-\inst1|Add2~36\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~36_combout\ = (\inst1|s_counter\(18) & (\inst1|Add2~35\ $ (GND))) # (!\inst1|s_counter\(18) & (!\inst1|Add2~35\ & VCC))
--- \inst1|Add2~37\ = CARRY((\inst1|s_counter\(18) & !\inst1|Add2~35\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(18),
- datad => VCC,
- cin => \inst1|Add2~35\,
- combout => \inst1|Add2~36_combout\,
- cout => \inst1|Add2~37\);
-
--- Location: LCCOMB_X54_Y3_N22
-\inst1|s_counter~7\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|s_counter~7_combout\ = (\inst1|Add2~36_combout\ & !\inst1|Equal0~11_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000011110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \inst1|Add2~36_combout\,
- datad => \inst1|Equal0~11_combout\,
- combout => \inst1|s_counter~7_combout\);
-
--- Location: FF_X54_Y3_N23
-\inst1|s_counter[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|s_counter~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(18));
-
--- Location: LCCOMB_X53_Y3_N6
-\inst1|Add2~38\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~38_combout\ = (\inst1|s_counter\(19) & (!\inst1|Add2~37\)) # (!\inst1|s_counter\(19) & ((\inst1|Add2~37\) # (GND)))
--- \inst1|Add2~39\ = CARRY((!\inst1|Add2~37\) # (!\inst1|s_counter\(19)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(19),
- datad => VCC,
- cin => \inst1|Add2~37\,
- combout => \inst1|Add2~38_combout\,
- cout => \inst1|Add2~39\);
-
--- Location: LCCOMB_X52_Y3_N24
-\inst1|s_counter~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|s_counter~6_combout\ = (!\inst1|Equal0~11_combout\ & \inst1|Add2~38_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000111100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \inst1|Equal0~11_combout\,
- datad => \inst1|Add2~38_combout\,
- combout => \inst1|s_counter~6_combout\);
-
--- Location: FF_X52_Y3_N25
-\inst1|s_counter[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|s_counter~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(19));
-
--- Location: LCCOMB_X53_Y3_N8
-\inst1|Add2~40\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~40_combout\ = (\inst1|s_counter\(20) & (\inst1|Add2~39\ $ (GND))) # (!\inst1|s_counter\(20) & (!\inst1|Add2~39\ & VCC))
--- \inst1|Add2~41\ = CARRY((\inst1|s_counter\(20) & !\inst1|Add2~39\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(20),
- datad => VCC,
- cin => \inst1|Add2~39\,
- combout => \inst1|Add2~40_combout\,
- cout => \inst1|Add2~41\);
-
--- Location: LCCOMB_X52_Y3_N30
-\inst1|s_counter~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|s_counter~5_combout\ = (!\inst1|Equal0~11_combout\ & \inst1|Add2~40_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011000000110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|Equal0~11_combout\,
- datac => \inst1|Add2~40_combout\,
- combout => \inst1|s_counter~5_combout\);
-
--- Location: FF_X52_Y3_N31
-\inst1|s_counter[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|s_counter~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(20));
-
--- Location: LCCOMB_X54_Y3_N20
-\inst1|Equal0~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Equal0~2_combout\ = (\inst1|s_counter\(18) & (\inst1|s_counter\(20) & (\inst1|s_counter\(19) & \inst1|s_counter\(13))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(18),
- datab => \inst1|s_counter\(20),
- datac => \inst1|s_counter\(19),
- datad => \inst1|s_counter\(13),
- combout => \inst1|Equal0~2_combout\);
-
--- Location: LCCOMB_X53_Y3_N10
-\inst1|Add2~42\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~42_combout\ = (\inst1|s_counter\(21) & (!\inst1|Add2~41\)) # (!\inst1|s_counter\(21) & ((\inst1|Add2~41\) # (GND)))
--- \inst1|Add2~43\ = CARRY((!\inst1|Add2~41\) # (!\inst1|s_counter\(21)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(21),
- datad => VCC,
- cin => \inst1|Add2~41\,
- combout => \inst1|Add2~42_combout\,
- cout => \inst1|Add2~43\);
-
--- Location: LCCOMB_X52_Y3_N22
-\inst1|s_counter~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|s_counter~4_combout\ = (!\inst1|Equal0~11_combout\ & \inst1|Add2~42_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011000000110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|Equal0~11_combout\,
- datac => \inst1|Add2~42_combout\,
- combout => \inst1|s_counter~4_combout\);
-
--- Location: FF_X52_Y3_N23
-\inst1|s_counter[21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|s_counter~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(21));
-
--- Location: LCCOMB_X53_Y3_N18
-\inst1|Add2~50\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~50_combout\ = (\inst1|s_counter\(25) & (!\inst1|Add2~49\)) # (!\inst1|s_counter\(25) & ((\inst1|Add2~49\) # (GND)))
--- \inst1|Add2~51\ = CARRY((!\inst1|Add2~49\) # (!\inst1|s_counter\(25)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(25),
- datad => VCC,
- cin => \inst1|Add2~49\,
- combout => \inst1|Add2~50_combout\,
- cout => \inst1|Add2~51\);
-
--- Location: FF_X53_Y3_N19
-\inst1|s_counter[25]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~50_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(25));
-
--- Location: LCCOMB_X53_Y3_N20
-\inst1|Add2~52\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~52_combout\ = (\inst1|s_counter\(26) & (\inst1|Add2~51\ $ (GND))) # (!\inst1|s_counter\(26) & (!\inst1|Add2~51\ & VCC))
--- \inst1|Add2~53\ = CARRY((\inst1|s_counter\(26) & !\inst1|Add2~51\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(26),
- datad => VCC,
- cin => \inst1|Add2~51\,
- combout => \inst1|Add2~52_combout\,
- cout => \inst1|Add2~53\);
-
--- Location: FF_X53_Y3_N21
-\inst1|s_counter[26]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~52_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(26));
-
--- Location: LCCOMB_X53_Y3_N22
-\inst1|Add2~54\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~54_combout\ = (\inst1|s_counter\(27) & (!\inst1|Add2~53\)) # (!\inst1|s_counter\(27) & ((\inst1|Add2~53\) # (GND)))
--- \inst1|Add2~55\ = CARRY((!\inst1|Add2~53\) # (!\inst1|s_counter\(27)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(27),
- datad => VCC,
- cin => \inst1|Add2~53\,
- combout => \inst1|Add2~54_combout\,
- cout => \inst1|Add2~55\);
-
--- Location: FF_X53_Y3_N23
-\inst1|s_counter[27]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~54_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(27));
-
--- Location: LCCOMB_X52_Y3_N28
-\inst1|Equal0~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Equal0~1_combout\ = (\inst1|s_counter\(21) & (!\inst1|s_counter\(25) & (!\inst1|s_counter\(26) & !\inst1|s_counter\(27))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000000010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(21),
- datab => \inst1|s_counter\(25),
- datac => \inst1|s_counter\(26),
- datad => \inst1|s_counter\(27),
- combout => \inst1|Equal0~1_combout\);
-
--- Location: LCCOMB_X53_Y3_N24
-\inst1|Add2~56\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~56_combout\ = (\inst1|s_counter\(28) & (\inst1|Add2~55\ $ (GND))) # (!\inst1|s_counter\(28) & (!\inst1|Add2~55\ & VCC))
--- \inst1|Add2~57\ = CARRY((\inst1|s_counter\(28) & !\inst1|Add2~55\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(28),
- datad => VCC,
- cin => \inst1|Add2~55\,
- combout => \inst1|Add2~56_combout\,
- cout => \inst1|Add2~57\);
-
--- Location: FF_X53_Y3_N25
-\inst1|s_counter[28]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~56_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(28));
-
--- Location: LCCOMB_X53_Y3_N26
-\inst1|Add2~58\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~58_combout\ = (\inst1|s_counter\(29) & (!\inst1|Add2~57\)) # (!\inst1|s_counter\(29) & ((\inst1|Add2~57\) # (GND)))
--- \inst1|Add2~59\ = CARRY((!\inst1|Add2~57\) # (!\inst1|s_counter\(29)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(29),
- datad => VCC,
- cin => \inst1|Add2~57\,
- combout => \inst1|Add2~58_combout\,
- cout => \inst1|Add2~59\);
-
--- Location: FF_X53_Y3_N27
-\inst1|s_counter[29]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~58_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(29));
-
--- Location: LCCOMB_X53_Y3_N28
-\inst1|Add2~60\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~60_combout\ = (\inst1|s_counter\(30) & (\inst1|Add2~59\ $ (GND))) # (!\inst1|s_counter\(30) & (!\inst1|Add2~59\ & VCC))
--- \inst1|Add2~61\ = CARRY((\inst1|s_counter\(30) & !\inst1|Add2~59\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(30),
- datad => VCC,
- cin => \inst1|Add2~59\,
- combout => \inst1|Add2~60_combout\,
- cout => \inst1|Add2~61\);
-
--- Location: FF_X53_Y3_N29
-\inst1|s_counter[30]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~60_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(30));
-
--- Location: LCCOMB_X53_Y3_N30
-\inst1|Add2~62\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~62_combout\ = \inst1|s_counter\(31) $ (\inst1|Add2~61\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011010",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(31),
- cin => \inst1|Add2~61\,
- combout => \inst1|Add2~62_combout\);
-
--- Location: FF_X53_Y3_N31
-\inst1|s_counter[31]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~62_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(31));
-
--- Location: LCCOMB_X52_Y3_N16
-\inst1|Equal0~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Equal0~0_combout\ = (!\inst1|s_counter\(31) & (!\inst1|s_counter\(30) & (!\inst1|s_counter\(28) & !\inst1|s_counter\(29))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000000001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(31),
- datab => \inst1|s_counter\(30),
- datac => \inst1|s_counter\(28),
- datad => \inst1|s_counter\(29),
- combout => \inst1|Equal0~0_combout\);
-
--- Location: LCCOMB_X54_Y3_N16
-\inst1|Equal0~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Equal0~4_combout\ = (\inst1|Equal0~3_combout\ & (\inst1|Equal0~2_combout\ & (\inst1|Equal0~1_combout\ & \inst1|Equal0~0_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|Equal0~3_combout\,
- datab => \inst1|Equal0~2_combout\,
- datac => \inst1|Equal0~1_combout\,
- datad => \inst1|Equal0~0_combout\,
- combout => \inst1|Equal0~4_combout\);
-
--- Location: LCCOMB_X54_Y3_N0
-\inst1|Equal0~11\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Equal0~11_combout\ = (\inst1|Equal0~6_combout\ & (\inst1|Equal0~10_combout\ & (\inst1|Equal0~5_combout\ & \inst1|Equal0~4_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|Equal0~6_combout\,
- datab => \inst1|Equal0~10_combout\,
- datac => \inst1|Equal0~5_combout\,
- datad => \inst1|Equal0~4_combout\,
- combout => \inst1|Equal0~11_combout\);
-
--- Location: LCCOMB_X53_Y3_N12
-\inst1|Add2~44\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Add2~44_combout\ = (\inst1|s_counter\(22) & (\inst1|Add2~43\ $ (GND))) # (!\inst1|s_counter\(22) & (!\inst1|Add2~43\ & VCC))
--- \inst1|Add2~45\ = CARRY((\inst1|s_counter\(22) & !\inst1|Add2~43\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(22),
- datad => VCC,
- cin => \inst1|Add2~43\,
- combout => \inst1|Add2~44_combout\,
- cout => \inst1|Add2~45\);
-
--- Location: LCCOMB_X54_Y3_N26
-\inst1|s_counter~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|s_counter~1_combout\ = (!\inst1|Equal0~11_combout\ & \inst1|Add2~44_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011001100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|Equal0~11_combout\,
- datad => \inst1|Add2~44_combout\,
- combout => \inst1|s_counter~1_combout\);
-
--- Location: FF_X54_Y3_N27
-\inst1|s_counter[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|s_counter~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(22));
-
--- Location: FF_X53_Y3_N15
-\inst1|s_counter[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|Add2~46_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|s_counter\(23));
-
--- Location: LCCOMB_X54_Y3_N4
-\inst1|clkOut~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|clkOut~0_combout\ = (\inst1|s_counter\(23) & (!\inst1|s_counter\(24) & (!\inst1|s_counter\(22) & \inst1|s_counter\(17))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000001000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(23),
- datab => \inst1|s_counter\(24),
- datac => \inst1|s_counter\(22),
- datad => \inst1|s_counter\(17),
- combout => \inst1|clkOut~0_combout\);
-
--- Location: LCCOMB_X54_Y3_N18
-\inst1|clkOut~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|clkOut~1_combout\ = (!\inst1|s_counter\(14) & (!\inst1|s_counter\(16) & (\inst1|s_counter\(15) & \inst1|s_counter\(10))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0001000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|s_counter\(14),
- datab => \inst1|s_counter\(16),
- datac => \inst1|s_counter\(15),
- datad => \inst1|s_counter\(10),
- combout => \inst1|clkOut~1_combout\);
-
--- Location: LCCOMB_X54_Y3_N6
-\inst1|clkOut~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|clkOut~2_combout\ = (!\inst1|s_counter\(5) & (\inst1|clkOut~0_combout\ & \inst1|clkOut~1_combout\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|s_counter\(5),
- datac => \inst1|clkOut~0_combout\,
- datad => \inst1|clkOut~1_combout\,
- combout => \inst1|clkOut~2_combout\);
-
--- Location: LCCOMB_X54_Y3_N12
-\inst1|Equal0~7\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|Equal0~7_combout\ = (\inst1|Equal0~5_combout\ & (\inst1|Equal0~6_combout\ & \inst1|Equal0~4_combout\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|Equal0~5_combout\,
- datac => \inst1|Equal0~6_combout\,
- datad => \inst1|Equal0~4_combout\,
- combout => \inst1|Equal0~7_combout\);
-
--- Location: LCCOMB_X54_Y3_N8
-\inst1|clkOut~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|clkOut~3_combout\ = (\inst1|Equal0~7_combout\ & (!\inst1|Equal0~10_combout\ & ((\inst1|clkOut~2_combout\) # (\inst1|clkOut~q\)))) # (!\inst1|Equal0~7_combout\ & (((\inst1|clkOut~q\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011001011110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst1|clkOut~2_combout\,
- datab => \inst1|Equal0~10_combout\,
- datac => \inst1|clkOut~q\,
- datad => \inst1|Equal0~7_combout\,
- combout => \inst1|clkOut~3_combout\);
-
--- Location: LCCOMB_X54_Y3_N24
-\inst1|clkOut~feeder\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst1|clkOut~feeder_combout\ = \inst1|clkOut~3_combout\
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100110011001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst1|clkOut~3_combout\,
- combout => \inst1|clkOut~feeder_combout\);
-
--- Location: FF_X54_Y3_N25
-\inst1|clkOut\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst1|clkOut~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst1|clkOut~q\);
-
--- Location: CLKCTRL_G18
-\inst1|clkOut~clkctrl\ : cycloneive_clkctrl
--- pragma translate_off
-GENERIC MAP (
- clock_type => "global clock",
- ena_register_mode => "none")
--- pragma translate_on
-PORT MAP (
- inclk => \inst1|clkOut~clkctrl_INCLK_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- outclk => \inst1|clkOut~clkctrl_outclk\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: LCCOMB_X114_Y65_N12
-\inst|s_count[0]~11\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|s_count[0]~11_combout\ = !\inst|s_count\(0)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000111100001111",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \inst|s_count\(0),
- combout => \inst|s_count[0]~11_combout\);
-
--- Location: IOIBUF_X115_Y53_N15
-\KEY[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY(1),
- o => \KEY[1]~input_o\);
-
--- Location: FF_X114_Y65_N13
-\inst|s_count[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst1|clkOut~clkctrl_outclk\,
- d => \inst|s_count[0]~11_combout\,
- clrn => \KEY[1]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|s_count\(0));
-
--- Location: LCCOMB_X114_Y65_N18
-\inst|s_count[1]~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|s_count[1]~4_cout\ = CARRY(\inst|s_count\(0))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000010101010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|s_count\(0),
- datad => VCC,
- cout => \inst|s_count[1]~4_cout\);
-
--- Location: LCCOMB_X114_Y65_N20
-\inst|s_count[1]~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|s_count[1]~5_combout\ = (\SW[0]~input_o\ & ((\inst|s_count\(1) & (\inst|s_count[1]~4_cout\ & VCC)) # (!\inst|s_count\(1) & (!\inst|s_count[1]~4_cout\)))) # (!\SW[0]~input_o\ & ((\inst|s_count\(1) & (!\inst|s_count[1]~4_cout\)) # (!\inst|s_count\(1)
--- & ((\inst|s_count[1]~4_cout\) # (GND)))))
--- \inst|s_count[1]~6\ = CARRY((\SW[0]~input_o\ & (!\inst|s_count\(1) & !\inst|s_count[1]~4_cout\)) # (!\SW[0]~input_o\ & ((!\inst|s_count[1]~4_cout\) # (!\inst|s_count\(1)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[0]~input_o\,
- datab => \inst|s_count\(1),
- datad => VCC,
- cin => \inst|s_count[1]~4_cout\,
- combout => \inst|s_count[1]~5_combout\,
- cout => \inst|s_count[1]~6\);
-
--- Location: FF_X114_Y65_N21
-\inst|s_count[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst1|clkOut~clkctrl_outclk\,
- d => \inst|s_count[1]~5_combout\,
- clrn => \KEY[1]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|s_count\(1));
-
--- Location: LCCOMB_X114_Y65_N22
-\inst|s_count[2]~7\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|s_count[2]~7_combout\ = ((\inst|s_count\(2) $ (\SW[0]~input_o\ $ (!\inst|s_count[1]~6\)))) # (GND)
--- \inst|s_count[2]~8\ = CARRY((\inst|s_count\(2) & ((\SW[0]~input_o\) # (!\inst|s_count[1]~6\))) # (!\inst|s_count\(2) & (\SW[0]~input_o\ & !\inst|s_count[1]~6\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|s_count\(2),
- datab => \SW[0]~input_o\,
- datad => VCC,
- cin => \inst|s_count[1]~6\,
- combout => \inst|s_count[2]~7_combout\,
- cout => \inst|s_count[2]~8\);
-
--- Location: FF_X114_Y65_N23
-\inst|s_count[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst1|clkOut~clkctrl_outclk\,
- d => \inst|s_count[2]~7_combout\,
- clrn => \KEY[1]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|s_count\(2));
-
--- Location: LCCOMB_X114_Y65_N24
-\inst|s_count[3]~9\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|s_count[3]~9_combout\ = \SW[0]~input_o\ $ (\inst|s_count[2]~8\ $ (\inst|s_count\(3)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010010101011010",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[0]~input_o\,
- datad => \inst|s_count\(3),
- cin => \inst|s_count[2]~8\,
- combout => \inst|s_count[3]~9_combout\);
-
--- Location: FF_X114_Y65_N25
-\inst|s_count[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst1|clkOut~clkctrl_outclk\,
- d => \inst|s_count[3]~9_combout\,
- clrn => \KEY[1]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|s_count\(3));
-
--- Location: LCCOMB_X114_Y65_N26
-\hex|decOut_n[6]~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \hex|decOut_n[6]~0_combout\ = (\inst|s_count\(0) & (!\inst|s_count\(3) & (\inst|s_count\(1) $ (!\inst|s_count\(2))))) # (!\inst|s_count\(0) & (!\inst|s_count\(1) & (\inst|s_count\(2) $ (!\inst|s_count\(3)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0001000010000101",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|s_count\(1),
- datab => \inst|s_count\(0),
- datac => \inst|s_count\(2),
- datad => \inst|s_count\(3),
- combout => \hex|decOut_n[6]~0_combout\);
-
--- Location: LCCOMB_X114_Y65_N0
-\hex|decOut_n[5]~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \hex|decOut_n[5]~1_combout\ = (\inst|s_count\(1) & (!\inst|s_count\(3) & ((\inst|s_count\(0)) # (!\inst|s_count\(2))))) # (!\inst|s_count\(1) & (\inst|s_count\(0) & (\inst|s_count\(2) $ (!\inst|s_count\(3)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0100000010001110",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|s_count\(1),
- datab => \inst|s_count\(0),
- datac => \inst|s_count\(2),
- datad => \inst|s_count\(3),
- combout => \hex|decOut_n[5]~1_combout\);
-
--- Location: LCCOMB_X114_Y65_N14
-\hex|decOut_n[4]~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \hex|decOut_n[4]~2_combout\ = (\inst|s_count\(1) & (\inst|s_count\(0) & ((!\inst|s_count\(3))))) # (!\inst|s_count\(1) & ((\inst|s_count\(2) & ((!\inst|s_count\(3)))) # (!\inst|s_count\(2) & (\inst|s_count\(0)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000010011011100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|s_count\(1),
- datab => \inst|s_count\(0),
- datac => \inst|s_count\(2),
- datad => \inst|s_count\(3),
- combout => \hex|decOut_n[4]~2_combout\);
-
--- Location: LCCOMB_X114_Y65_N4
-\hex|decOut_n[3]~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \hex|decOut_n[3]~3_combout\ = (\inst|s_count\(1) & ((\inst|s_count\(0) & (\inst|s_count\(2))) # (!\inst|s_count\(0) & (!\inst|s_count\(2) & \inst|s_count\(3))))) # (!\inst|s_count\(1) & (!\inst|s_count\(3) & (\inst|s_count\(0) $ (\inst|s_count\(2)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000001010010100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|s_count\(1),
- datab => \inst|s_count\(0),
- datac => \inst|s_count\(2),
- datad => \inst|s_count\(3),
- combout => \hex|decOut_n[3]~3_combout\);
-
--- Location: LCCOMB_X114_Y65_N10
-\hex|decOut_n[2]~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \hex|decOut_n[2]~4_combout\ = (\inst|s_count\(2) & (\inst|s_count\(3) & ((\inst|s_count\(1)) # (!\inst|s_count\(0))))) # (!\inst|s_count\(2) & (\inst|s_count\(1) & (!\inst|s_count\(0) & !\inst|s_count\(3))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1011000000000010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|s_count\(1),
- datab => \inst|s_count\(0),
- datac => \inst|s_count\(2),
- datad => \inst|s_count\(3),
- combout => \hex|decOut_n[2]~4_combout\);
-
--- Location: LCCOMB_X114_Y65_N8
-\hex|decOut_n[1]~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \hex|decOut_n[1]~5_combout\ = (\inst|s_count\(1) & ((\inst|s_count\(0) & ((\inst|s_count\(3)))) # (!\inst|s_count\(0) & (\inst|s_count\(2))))) # (!\inst|s_count\(1) & (\inst|s_count\(2) & (\inst|s_count\(0) $ (\inst|s_count\(3)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1011100001100000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|s_count\(1),
- datab => \inst|s_count\(0),
- datac => \inst|s_count\(2),
- datad => \inst|s_count\(3),
- combout => \hex|decOut_n[1]~5_combout\);
-
--- Location: LCCOMB_X114_Y65_N2
-\hex|decOut_n[0]~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \hex|decOut_n[0]~6_combout\ = (\inst|s_count\(2) & (!\inst|s_count\(1) & (\inst|s_count\(0) $ (!\inst|s_count\(3))))) # (!\inst|s_count\(2) & (\inst|s_count\(0) & (\inst|s_count\(1) $ (!\inst|s_count\(3)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0100100000010100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|s_count\(1),
- datab => \inst|s_count\(0),
- datac => \inst|s_count\(2),
- datad => \inst|s_count\(3),
- combout => \hex|decOut_n[0]~6_combout\);
-
-ww_HEX0(6) <= \HEX0[6]~output_o\;
-
-ww_HEX0(5) <= \HEX0[5]~output_o\;
-
-ww_HEX0(4) <= \HEX0[4]~output_o\;
-
-ww_HEX0(3) <= \HEX0[3]~output_o\;
-
-ww_HEX0(2) <= \HEX0[2]~output_o\;
-
-ww_HEX0(1) <= \HEX0[1]~output_o\;
-
-ww_HEX0(0) <= \HEX0[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/CounterDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/CounterDemo_modelsim.xrf
deleted file mode 100644
index e80e46f..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/CounterDemo_modelsim.xrf
+++ /dev/null
@@ -1,136 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vwf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cbx.xml
-design_name = hard_block
-design_name = CounterDemo
-instance = comp, \HEX0[6]~output\, HEX0[6]~output, CounterDemo, 1
-instance = comp, \HEX0[5]~output\, HEX0[5]~output, CounterDemo, 1
-instance = comp, \HEX0[4]~output\, HEX0[4]~output, CounterDemo, 1
-instance = comp, \HEX0[3]~output\, HEX0[3]~output, CounterDemo, 1
-instance = comp, \HEX0[2]~output\, HEX0[2]~output, CounterDemo, 1
-instance = comp, \HEX0[1]~output\, HEX0[1]~output, CounterDemo, 1
-instance = comp, \HEX0[0]~output\, HEX0[0]~output, CounterDemo, 1
-instance = comp, \CLOCK_50~input\, CLOCK_50~input, CounterDemo, 1
-instance = comp, \CLOCK_50~inputclkctrl\, CLOCK_50~inputclkctrl, CounterDemo, 1
-instance = comp, \inst1|Add2~0\, inst1|Add2~0, CounterDemo, 1
-instance = comp, \inst1|s_counter[0]\, inst1|s_counter[0], CounterDemo, 1
-instance = comp, \inst1|Add2~2\, inst1|Add2~2, CounterDemo, 1
-instance = comp, \inst1|s_counter[1]\, inst1|s_counter[1], CounterDemo, 1
-instance = comp, \inst1|Add2~4\, inst1|Add2~4, CounterDemo, 1
-instance = comp, \inst1|s_counter[2]\, inst1|s_counter[2], CounterDemo, 1
-instance = comp, \inst1|Add2~6\, inst1|Add2~6, CounterDemo, 1
-instance = comp, \inst1|s_counter[3]\, inst1|s_counter[3], CounterDemo, 1
-instance = comp, \inst1|Add2~8\, inst1|Add2~8, CounterDemo, 1
-instance = comp, \inst1|s_counter[4]\, inst1|s_counter[4], CounterDemo, 1
-instance = comp, \inst1|Add2~10\, inst1|Add2~10, CounterDemo, 1
-instance = comp, \inst1|s_counter[5]\, inst1|s_counter[5], CounterDemo, 1
-instance = comp, \inst1|Equal0~6\, inst1|Equal0~6, CounterDemo, 1
-instance = comp, \inst1|Add2~46\, inst1|Add2~46, CounterDemo, 1
-instance = comp, \inst1|Add2~48\, inst1|Add2~48, CounterDemo, 1
-instance = comp, \inst1|s_counter~0\, inst1|s_counter~0, CounterDemo, 1
-instance = comp, \inst1|s_counter[24]\, inst1|s_counter[24], CounterDemo, 1
-instance = comp, \inst1|Add2~12\, inst1|Add2~12, CounterDemo, 1
-instance = comp, \inst1|s_counter~11\, inst1|s_counter~11, CounterDemo, 1
-instance = comp, \inst1|s_counter[6]\, inst1|s_counter[6], CounterDemo, 1
-instance = comp, \inst1|Add2~14\, inst1|Add2~14, CounterDemo, 1
-instance = comp, \inst1|s_counter[7]\, inst1|s_counter[7], CounterDemo, 1
-instance = comp, \inst1|Add2~16\, inst1|Add2~16, CounterDemo, 1
-instance = comp, \inst1|s_counter[8]\, inst1|s_counter[8], CounterDemo, 1
-instance = comp, \inst1|Add2~18\, inst1|Add2~18, CounterDemo, 1
-instance = comp, \inst1|s_counter[9]\, inst1|s_counter[9], CounterDemo, 1
-instance = comp, \inst1|Add2~20\, inst1|Add2~20, CounterDemo, 1
-instance = comp, \inst1|s_counter[10]\, inst1|s_counter[10], CounterDemo, 1
-instance = comp, \inst1|Add2~22\, inst1|Add2~22, CounterDemo, 1
-instance = comp, \inst1|s_counter~10\, inst1|s_counter~10, CounterDemo, 1
-instance = comp, \inst1|s_counter[11]\, inst1|s_counter[11], CounterDemo, 1
-instance = comp, \inst1|Add2~24\, inst1|Add2~24, CounterDemo, 1
-instance = comp, \inst1|s_counter~9\, inst1|s_counter~9, CounterDemo, 1
-instance = comp, \inst1|s_counter[12]\, inst1|s_counter[12], CounterDemo, 1
-instance = comp, \inst1|Add2~26\, inst1|Add2~26, CounterDemo, 1
-instance = comp, \inst1|s_counter~8\, inst1|s_counter~8, CounterDemo, 1
-instance = comp, \inst1|s_counter[13]\, inst1|s_counter[13], CounterDemo, 1
-instance = comp, \inst1|Add2~28\, inst1|Add2~28, CounterDemo, 1
-instance = comp, \inst1|s_counter~3\, inst1|s_counter~3, CounterDemo, 1
-instance = comp, \inst1|s_counter[14]\, inst1|s_counter[14], CounterDemo, 1
-instance = comp, \inst1|Add2~30\, inst1|Add2~30, CounterDemo, 1
-instance = comp, \inst1|s_counter[15]\, inst1|s_counter[15], CounterDemo, 1
-instance = comp, \inst1|Add2~32\, inst1|Add2~32, CounterDemo, 1
-instance = comp, \inst1|s_counter~2\, inst1|s_counter~2, CounterDemo, 1
-instance = comp, \inst1|s_counter[16]\, inst1|s_counter[16], CounterDemo, 1
-instance = comp, \inst1|Add2~34\, inst1|Add2~34, CounterDemo, 1
-instance = comp, \inst1|s_counter[17]\, inst1|s_counter[17], CounterDemo, 1
-instance = comp, \inst1|Equal0~8\, inst1|Equal0~8, CounterDemo, 1
-instance = comp, \inst1|Equal0~9\, inst1|Equal0~9, CounterDemo, 1
-instance = comp, \inst1|Equal0~10\, inst1|Equal0~10, CounterDemo, 1
-instance = comp, \inst1|Equal0~5\, inst1|Equal0~5, CounterDemo, 1
-instance = comp, \inst1|Equal0~3\, inst1|Equal0~3, CounterDemo, 1
-instance = comp, \inst1|Add2~36\, inst1|Add2~36, CounterDemo, 1
-instance = comp, \inst1|s_counter~7\, inst1|s_counter~7, CounterDemo, 1
-instance = comp, \inst1|s_counter[18]\, inst1|s_counter[18], CounterDemo, 1
-instance = comp, \inst1|Add2~38\, inst1|Add2~38, CounterDemo, 1
-instance = comp, \inst1|s_counter~6\, inst1|s_counter~6, CounterDemo, 1
-instance = comp, \inst1|s_counter[19]\, inst1|s_counter[19], CounterDemo, 1
-instance = comp, \inst1|Add2~40\, inst1|Add2~40, CounterDemo, 1
-instance = comp, \inst1|s_counter~5\, inst1|s_counter~5, CounterDemo, 1
-instance = comp, \inst1|s_counter[20]\, inst1|s_counter[20], CounterDemo, 1
-instance = comp, \inst1|Equal0~2\, inst1|Equal0~2, CounterDemo, 1
-instance = comp, \inst1|Add2~42\, inst1|Add2~42, CounterDemo, 1
-instance = comp, \inst1|s_counter~4\, inst1|s_counter~4, CounterDemo, 1
-instance = comp, \inst1|s_counter[21]\, inst1|s_counter[21], CounterDemo, 1
-instance = comp, \inst1|Add2~50\, inst1|Add2~50, CounterDemo, 1
-instance = comp, \inst1|s_counter[25]\, inst1|s_counter[25], CounterDemo, 1
-instance = comp, \inst1|Add2~52\, inst1|Add2~52, CounterDemo, 1
-instance = comp, \inst1|s_counter[26]\, inst1|s_counter[26], CounterDemo, 1
-instance = comp, \inst1|Add2~54\, inst1|Add2~54, CounterDemo, 1
-instance = comp, \inst1|s_counter[27]\, inst1|s_counter[27], CounterDemo, 1
-instance = comp, \inst1|Equal0~1\, inst1|Equal0~1, CounterDemo, 1
-instance = comp, \inst1|Add2~56\, inst1|Add2~56, CounterDemo, 1
-instance = comp, \inst1|s_counter[28]\, inst1|s_counter[28], CounterDemo, 1
-instance = comp, \inst1|Add2~58\, inst1|Add2~58, CounterDemo, 1
-instance = comp, \inst1|s_counter[29]\, inst1|s_counter[29], CounterDemo, 1
-instance = comp, \inst1|Add2~60\, inst1|Add2~60, CounterDemo, 1
-instance = comp, \inst1|s_counter[30]\, inst1|s_counter[30], CounterDemo, 1
-instance = comp, \inst1|Add2~62\, inst1|Add2~62, CounterDemo, 1
-instance = comp, \inst1|s_counter[31]\, inst1|s_counter[31], CounterDemo, 1
-instance = comp, \inst1|Equal0~0\, inst1|Equal0~0, CounterDemo, 1
-instance = comp, \inst1|Equal0~4\, inst1|Equal0~4, CounterDemo, 1
-instance = comp, \inst1|Equal0~11\, inst1|Equal0~11, CounterDemo, 1
-instance = comp, \inst1|Add2~44\, inst1|Add2~44, CounterDemo, 1
-instance = comp, \inst1|s_counter~1\, inst1|s_counter~1, CounterDemo, 1
-instance = comp, \inst1|s_counter[22]\, inst1|s_counter[22], CounterDemo, 1
-instance = comp, \inst1|s_counter[23]\, inst1|s_counter[23], CounterDemo, 1
-instance = comp, \inst1|clkOut~0\, inst1|clkOut~0, CounterDemo, 1
-instance = comp, \inst1|clkOut~1\, inst1|clkOut~1, CounterDemo, 1
-instance = comp, \inst1|clkOut~2\, inst1|clkOut~2, CounterDemo, 1
-instance = comp, \inst1|Equal0~7\, inst1|Equal0~7, CounterDemo, 1
-instance = comp, \inst1|clkOut~3\, inst1|clkOut~3, CounterDemo, 1
-instance = comp, \inst1|clkOut~feeder\, inst1|clkOut~feeder, CounterDemo, 1
-instance = comp, \inst1|clkOut\, inst1|clkOut, CounterDemo, 1
-instance = comp, \inst1|clkOut~clkctrl\, inst1|clkOut~clkctrl, CounterDemo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, CounterDemo, 1
-instance = comp, \inst|s_count[0]~11\, inst|s_count[0]~11, CounterDemo, 1
-instance = comp, \KEY[1]~input\, KEY[1]~input, CounterDemo, 1
-instance = comp, \inst|s_count[0]\, inst|s_count[0], CounterDemo, 1
-instance = comp, \inst|s_count[1]~4\, inst|s_count[1]~4, CounterDemo, 1
-instance = comp, \inst|s_count[1]~5\, inst|s_count[1]~5, CounterDemo, 1
-instance = comp, \inst|s_count[1]\, inst|s_count[1], CounterDemo, 1
-instance = comp, \inst|s_count[2]~7\, inst|s_count[2]~7, CounterDemo, 1
-instance = comp, \inst|s_count[2]\, inst|s_count[2], CounterDemo, 1
-instance = comp, \inst|s_count[3]~9\, inst|s_count[3]~9, CounterDemo, 1
-instance = comp, \inst|s_count[3]\, inst|s_count[3], CounterDemo, 1
-instance = comp, \hex|decOut_n[6]~0\, hex|decOut_n[6]~0, CounterDemo, 1
-instance = comp, \hex|decOut_n[5]~1\, hex|decOut_n[5]~1, CounterDemo, 1
-instance = comp, \hex|decOut_n[4]~2\, hex|decOut_n[4]~2, CounterDemo, 1
-instance = comp, \hex|decOut_n[3]~3\, hex|decOut_n[3]~3, CounterDemo, 1
-instance = comp, \hex|decOut_n[2]~4\, hex|decOut_n[2]~4, CounterDemo, 1
-instance = comp, \hex|decOut_n[1]~5\, hex|decOut_n[1]~5, CounterDemo, 1
-instance = comp, \hex|decOut_n[0]~6\, hex|decOut_n[0]~6, CounterDemo, 1
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.do b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.do
deleted file mode 100644
index 4ecc143..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.do
+++ /dev/null
@@ -1,17 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vcom -work work CounterDemo.vho
-vcom -work work CounterDown4.vwf.vht
-vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CounterDown4_vhd_vec_tst
-vcd file -direction CounterDemo.msim.vcd
-vcd add -internal CounterDown4_vhd_vec_tst/*
-vcd add -internal CounterDown4_vhd_vec_tst/i1/*
-proc simTimestamp {} {
- echo "Simulation time: $::now ps"
- if { [string equal running [runStatus]] } {
- after 2500 simTimestamp
- }
-}
-after 2500 simTimestamp
-run -all
-quit -f
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.msim.vcd b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.msim.vcd
deleted file mode 100644
index 3bad311..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.msim.vcd
+++ /dev/null
@@ -1,526 +0,0 @@
-$comment
- File created using the following command:
- vcd file CounterDemo.msim.vcd -direction
-$end
-$date
- Thu Mar 16 16:48:06 2023
-$end
-$version
- ModelSim Version 2020.1
-$end
-$timescale
- 1ps
-$end
-
-$scope module counterdown4_vhd_vec_tst $end
-$var wire 1 ! clk $end
-$var wire 1 " count [3] $end
-$var wire 1 # count [2] $end
-$var wire 1 $ count [1] $end
-$var wire 1 % count [0] $end
-
-$scope module i1 $end
-$var wire 1 & gnd $end
-$var wire 1 ' vcc $end
-$var wire 1 ( unknown $end
-$var wire 1 ) devoe $end
-$var wire 1 * devclrn $end
-$var wire 1 + devpor $end
-$var wire 1 , ww_devoe $end
-$var wire 1 - ww_devclrn $end
-$var wire 1 . ww_devpor $end
-$var wire 1 / ww_clk $end
-$var wire 1 0 ww_count [3] $end
-$var wire 1 1 ww_count [2] $end
-$var wire 1 2 ww_count [1] $end
-$var wire 1 3 ww_count [0] $end
-$var wire 1 4 \count[0]~output_o\ $end
-$var wire 1 5 \count[1]~output_o\ $end
-$var wire 1 6 \count[2]~output_o\ $end
-$var wire 1 7 \count[3]~output_o\ $end
-$var wire 1 8 \clk~input_o\ $end
-$var wire 1 9 \s_count[0]~0_combout\ $end
-$var wire 1 : \Add0~0_combout\ $end
-$var wire 1 ; \Add0~1_combout\ $end
-$var wire 1 < \Add0~2_combout\ $end
-$var wire 1 = s_count [3] $end
-$var wire 1 > s_count [2] $end
-$var wire 1 ? s_count [1] $end
-$var wire 1 @ s_count [0] $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0!
-0&
-1'
-x(
-1)
-1*
-1+
-1,
-1-
-1.
-0/
-04
-05
-06
-07
-08
-19
-1:
-1;
-1<
-00
-01
-02
-03
-0=
-0>
-0?
-0@
-0"
-0#
-0$
-0%
-$end
-#20000
-1!
-1/
-18
-1@
-1?
-1>
-1=
-09
-17
-16
-15
-14
-10
-11
-12
-13
-1%
-1$
-1#
-1"
-#40000
-0!
-0/
-08
-#60000
-1!
-1/
-18
-0@
-19
-0:
-04
-03
-0%
-#80000
-0!
-0/
-08
-#100000
-1!
-1/
-18
-1@
-0?
-09
-05
-14
-02
-13
-1%
-0$
-#120000
-0!
-0/
-08
-#140000
-1!
-1/
-18
-0@
-19
-1:
-0;
-04
-03
-0%
-#160000
-0!
-0/
-08
-#180000
-1!
-1/
-18
-1@
-1?
-0>
-09
-06
-15
-14
-01
-12
-13
-1%
-1$
-0#
-#200000
-0!
-0/
-08
-#220000
-1!
-1/
-18
-0@
-19
-0:
-04
-03
-0%
-#240000
-0!
-0/
-08
-#260000
-1!
-1/
-18
-1@
-0?
-09
-05
-14
-02
-13
-1%
-0$
-#280000
-0!
-0/
-08
-#300000
-1!
-1/
-18
-0@
-19
-1:
-1;
-0<
-04
-03
-0%
-#320000
-0!
-0/
-08
-#340000
-1!
-1/
-18
-1@
-1?
-1>
-0=
-09
-07
-16
-15
-14
-00
-11
-12
-13
-1%
-1$
-1#
-0"
-#360000
-0!
-0/
-08
-#380000
-1!
-1/
-18
-0@
-19
-0:
-04
-03
-0%
-#400000
-0!
-0/
-08
-#420000
-1!
-1/
-18
-1@
-0?
-09
-05
-14
-02
-13
-1%
-0$
-#440000
-0!
-0/
-08
-#460000
-1!
-1/
-18
-0@
-19
-1:
-0;
-04
-03
-0%
-#480000
-0!
-0/
-08
-#500000
-1!
-1/
-18
-1@
-1?
-0>
-09
-06
-15
-14
-01
-12
-13
-1%
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-0!
-0/
-08
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-04
-03
-0%
-#560000
-0!
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-08
-#580000
-1!
-1/
-18
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-0?
-09
-05
-14
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-1%
-0$
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-0!
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-08
-#620000
-1!
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-18
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-19
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-1<
-04
-03
-0%
-#640000
-0!
-0/
-08
-#660000
-1!
-1/
-18
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-1>
-1=
-09
-17
-16
-15
-14
-10
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-1%
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-1#
-1"
-#680000
-0!
-0/
-08
-#700000
-1!
-1/
-18
-0@
-19
-0:
-04
-03
-0%
-#720000
-0!
-0/
-08
-#740000
-1!
-1/
-18
-1@
-0?
-09
-05
-14
-02
-13
-1%
-0$
-#760000
-0!
-0/
-08
-#780000
-1!
-1/
-18
-0@
-19
-1:
-0;
-04
-03
-0%
-#800000
-0!
-0/
-08
-#820000
-1!
-1/
-18
-1@
-1?
-0>
-09
-06
-15
-14
-01
-12
-13
-1%
-1$
-0#
-#840000
-0!
-0/
-08
-#860000
-1!
-1/
-18
-0@
-19
-0:
-04
-03
-0%
-#880000
-0!
-0/
-08
-#900000
-1!
-1/
-18
-1@
-0?
-09
-05
-14
-02
-13
-1%
-0$
-#920000
-0!
-0/
-08
-#940000
-1!
-1/
-18
-0@
-19
-1:
-1;
-0<
-04
-03
-0%
-#960000
-0!
-0/
-08
-#980000
-1!
-1/
-18
-1@
-1?
-1>
-0=
-09
-07
-16
-15
-14
-00
-11
-12
-13
-1%
-1$
-1#
-0"
-#1000000
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.sft b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.vho b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.vho
deleted file mode 100644
index cb4a4cc..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.vho
+++ /dev/null
@@ -1,248 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/16/2023 16:48:05"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY ALTERA;
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY CounterDown4 IS
- PORT (
- clk : IN std_logic;
- count : OUT std_logic_vector(3 DOWNTO 0)
- );
-END CounterDown4;
-
-ARCHITECTURE structure OF CounterDown4 IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_clk : std_logic;
-SIGNAL ww_count : std_logic_vector(3 DOWNTO 0);
-SIGNAL \count[0]~output_o\ : std_logic;
-SIGNAL \count[1]~output_o\ : std_logic;
-SIGNAL \count[2]~output_o\ : std_logic;
-SIGNAL \count[3]~output_o\ : std_logic;
-SIGNAL \clk~input_o\ : std_logic;
-SIGNAL \s_count[0]~0_combout\ : std_logic;
-SIGNAL \Add0~0_combout\ : std_logic;
-SIGNAL \Add0~1_combout\ : std_logic;
-SIGNAL \Add0~2_combout\ : std_logic;
-SIGNAL s_count : std_logic_vector(3 DOWNTO 0);
-
-BEGIN
-
-ww_clk <= clk;
-count <= ww_count;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
-\count[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => s_count(0),
- devoe => ww_devoe,
- o => \count[0]~output_o\);
-
-\count[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => s_count(1),
- devoe => ww_devoe,
- o => \count[1]~output_o\);
-
-\count[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => s_count(2),
- devoe => ww_devoe,
- o => \count[2]~output_o\);
-
-\count[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => s_count(3),
- devoe => ww_devoe,
- o => \count[3]~output_o\);
-
-\clk~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_clk,
- o => \clk~input_o\);
-
-\s_count[0]~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \s_count[0]~0_combout\ = !s_count(0)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101010101010101",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => s_count(0),
- combout => \s_count[0]~0_combout\);
-
-\s_count[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \clk~input_o\,
- d => \s_count[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => s_count(0));
-
-\Add0~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Add0~0_combout\ = s_count(0) $ (!s_count(1))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111000000001111",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => s_count(0),
- datad => s_count(1),
- combout => \Add0~0_combout\);
-
-\s_count[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \clk~input_o\,
- d => \Add0~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => s_count(1));
-
-\Add0~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \Add0~1_combout\ = s_count(2) $ (((!s_count(0) & !s_count(1))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111110000000011",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => s_count(0),
- datac => s_count(1),
- datad => s_count(2),
- combout => \Add0~1_combout\);
-
-\s_count[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \clk~input_o\,
- d => \Add0~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => s_count(2));
-
-\Add0~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Add0~2_combout\ = s_count(3) $ (((!s_count(0) & (!s_count(1) & !s_count(2)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111000000001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => s_count(0),
- datab => s_count(1),
- datac => s_count(2),
- datad => s_count(3),
- combout => \Add0~2_combout\);
-
-\s_count[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \clk~input_o\,
- d => \Add0~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => s_count(3));
-
-ww_count(0) <= \count[0]~output_o\;
-
-ww_count(1) <= \count[1]~output_o\;
-
-ww_count(2) <= \count[2]~output_o\;
-
-ww_count(3) <= \count[3]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo_20230316164807.sim.vwf b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo_20230316164807.sim.vwf
deleted file mode 100644
index 16c7f20..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo_20230316164807.sim.vwf
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("clk")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("count")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 4;
- LSB_INDEX = 0;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("count[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "count";
-}
-
-SIGNAL("count[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "count";
-}
-
-SIGNAL("count[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "count";
-}
-
-SIGNAL("count[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "count";
-}
-
-TRANSITION_LIST("clk")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- }
- }
-}
-
-TRANSITION_LIST("count[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 320.0;
- LEVEL 0 FOR 320.0;
- LEVEL 1 FOR 320.0;
- LEVEL 0 FOR 20.0;
- }
- }
-}
-
-TRANSITION_LIST("count[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 160.0;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 160.0;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 160.0;
- LEVEL 1 FOR 20.0;
- }
- }
-}
-
-TRANSITION_LIST("count[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 20.0;
- }
- }
-}
-
-TRANSITION_LIST("count[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 20.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "clk";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "count";
- EXPAND_STATUS = EXPANDED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 0;
- CHILDREN = 2, 3, 4, 5;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "count[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 1;
- PARENT = 1;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "count[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 1;
- PARENT = 1;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "count[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 1;
- PARENT = 1;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "count[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 5;
- TREE_LEVEL = 1;
- PARENT = 1;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo_modelsim.xrf
deleted file mode 100644
index d90015e..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo_modelsim.xrf
+++ /dev/null
@@ -1,21 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cbx.xml
-design_name = CounterDown4
-instance = comp, \count[0]~output\, count[0]~output, CounterDown4, 1
-instance = comp, \count[1]~output\, count[1]~output, CounterDown4, 1
-instance = comp, \count[2]~output\, count[2]~output, CounterDown4, 1
-instance = comp, \count[3]~output\, count[3]~output, CounterDown4, 1
-instance = comp, \clk~input\, clk~input, CounterDown4, 1
-instance = comp, \s_count[0]~0\, s_count[0]~0, CounterDown4, 1
-instance = comp, \s_count[0]\, s_count[0], CounterDown4, 1
-instance = comp, \Add0~0\, Add0~0, CounterDown4, 1
-instance = comp, \s_count[1]\, s_count[1], CounterDown4, 1
-instance = comp, \Add0~1\, Add0~1, CounterDown4, 1
-instance = comp, \s_count[2]\, s_count[2], CounterDown4, 1
-instance = comp, \Add0~2\, Add0~2, CounterDown4, 1
-instance = comp, \s_count[3]\, s_count[3], CounterDown4, 1
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDown4.vwf.vht b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDown4.vwf.vht
deleted file mode 100644
index f6d0ffd..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDown4.vwf.vht
+++ /dev/null
@@ -1,64 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- *****************************************************************************
--- This file contains a Vhdl test bench with test vectors .The test vectors
--- are exported from a vector file in the Quartus Waveform Editor and apply to
--- the top level entity of the current Quartus project .The user can use this
--- testbench to simulate his design using a third-party simulation tool .
--- *****************************************************************************
--- Generated on "03/16/2023 16:48:04"
-
--- Vhdl Test Bench(with test vectors) for design : CounterDown4
---
--- Simulation tool : 3rd Party
---
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY CounterDown4_vhd_vec_tst IS
-END CounterDown4_vhd_vec_tst;
-ARCHITECTURE CounterDown4_arch OF CounterDown4_vhd_vec_tst IS
--- constants
--- signals
-SIGNAL clk : STD_LOGIC;
-SIGNAL count : STD_LOGIC_VECTOR(3 DOWNTO 0);
-COMPONENT CounterDown4
- PORT (
- clk : IN STD_LOGIC;
- count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
- );
-END COMPONENT;
-BEGIN
- i1 : CounterDown4
- PORT MAP (
--- list connections between master ports and signals
- clk => clk,
- count => count
- );
-
--- clk
-t_prcs_clk: PROCESS
-BEGIN
-LOOP
- clk <= '0';
- WAIT FOR 20000 ps;
- clk <= '1';
- WAIT FOR 20000 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_clk;
-END CounterDown4_arch;
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/transcript
deleted file mode 100644
index 13e27ae..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/transcript
+++ /dev/null
@@ -1,48 +0,0 @@
-# do CounterDemo.do
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 16:48:06 on Mar 16,2023
-# vcom -work work CounterDemo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package dffeas_pack
-# -- Loading package altera_primitives_components
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity CounterDown4
-# -- Compiling architecture structure of CounterDown4
-# End time: 16:48:06 on Mar 16,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 16:48:06 on Mar 16,2023
-# vcom -work work CounterDown4.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity CounterDown4_vhd_vec_tst
-# -- Compiling architecture CounterDown4_arch of CounterDown4_vhd_vec_tst
-# End time: 16:48:06 on Mar 16,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CounterDown4_vhd_vec_tst
-# Start time: 16:48:06 on Mar 16,2023
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading work.counterdown4_vhd_vec_tst(counterdown4_arch)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading altera.dffeas_pack
-# Loading altera.altera_primitives_components
-# Loading cycloneive.cycloneive_atom_pack(body)
-# Loading cycloneive.cycloneive_components
-# Loading work.counterdown4(structure)
-# Loading ieee.std_logic_arith(body)
-# Loading cycloneive.cycloneive_io_obuf(arch)
-# Loading cycloneive.cycloneive_io_ibuf(arch)
-# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# Loading altera.dffeas(vital_dffeas)
-# after#31
-# End time: 16:48:06 on Mar 16,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/vwf_sim_transcript
deleted file mode 100644
index 9b9f08f..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/vwf_sim_transcript
+++ /dev/null
@@ -1,73 +0,0 @@
-Determining the location of the ModelSim executable...
-
-Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
-
-To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
-Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
-
-**** Generating the ModelSim Testbench ****
-
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CounterDemo -c CounterDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDown4.vwf.vht"
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Thu Mar 16 16:48:04 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CounterDemo -c CounterDemo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDown4.vwf.vhtInfo (119006): Selected device EP4CE115F29C7 for design "CounterDemo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Completed successfully.
-
-**** Generating the functional simulation netlist ****
-
-quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/" CounterDemo -c CounterDemo
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Thu Mar 16 16:48:05 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/ CounterDemo -c CounterDemoInfo (119006): Selected device EP4CE115F29C7 for design "CounterDemo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file CounterDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 615 megabytes Info: Processing ended: Thu Mar 16 16:48:05 2023 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00
-Completed successfully.
-
-**** Generating the ModelSim .do script ****
-
-/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.do generated.
-
-Completed successfully.
-
-**** Running the ModelSim simulation ****
-
-/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do CounterDemo.do
-
-Reading pref.tcl
-# 2020.1
-# do CounterDemo.do
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 16:48:06 on Mar 16,2023# vcom -work work CounterDemo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package dffeas_pack# -- Loading package altera_primitives_components
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity CounterDown4
-# -- Compiling architecture structure of CounterDown4
-# End time: 16:48:06 on Mar 16,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 16:48:06 on Mar 16,2023# vcom -work work CounterDown4.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO# -- Loading package std_logic_1164
-# -- Compiling entity CounterDown4_vhd_vec_tst
-# -- Compiling architecture CounterDown4_arch of CounterDown4_vhd_vec_tst# End time: 16:48:06 on Mar 16,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CounterDown4_vhd_vec_tst # Start time: 16:48:06 on Mar 16,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.counterdown4_vhd_vec_tst(counterdown4_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading altera.dffeas_pack# Loading altera.altera_primitives_components# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.counterdown4(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)# Loading altera.dffeas(vital_dffeas)
-# after#31
-# End time: 16:48:06 on Mar 16,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-Completed successfully.
-
-**** Converting ModelSim VCD to vector waveform ****
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vwf...
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo.msim.vcd...
-
-Processing channel transitions...
-
-Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDemo_20230316164807.sim.vwf
-
-Finished VCD to VWF conversion.
-
-Completed successfully.
-
-All completed.
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_info
deleted file mode 100644
index 4655974..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_info
+++ /dev/null
@@ -1,105 +0,0 @@
-m255
-K4
-z2
-!s11e vcom 2020.1 2020.02, Feb 28 2020
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-Z0 d/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim
-Ecounterdown4
-Z1 w1678985285
-Z2 DPx10 cycloneive 20 cycloneive_atom_pack 0 22 WOh:M[al;oVzG5c`D0
-Z3 DPx10 cycloneive 21 cycloneive_components 0 22 zGMDhP>8e@2k@f0ekiXP8Q9dRClKfK1Zn7j1
-Z5 DPx6 altera 11 dffeas_pack 0 22 dc5N=DKXMMTVYdUQ@D3FA2
-Z6 DPx4 ieee 12 vital_timing 0 22 J>EBealN09f8GzldA[z2>3
-Z7 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
-Z8 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
-Z9 DPx6 altera 28 altera_primitives_components 0 22 ca:ehlQAg4;_gVV:^8MAg3
-!i122 0
-R0
-Z10 8CounterDemo.vho
-Z11 FCounterDemo.vho
-l0
-L37 1
-VYV9D_iQL>Id?MAGOM>nQz3
-!s100 `9Id?MAGOM>nQz3
-!i122 0
-l67
-L44 203
-V_zMY3
-!s100 XJjNR7SiMjK8:_9W0ch?42
-R12
-32
-R13
-!i10b 1
-R14
-R15
-R16
-!i113 1
-R17
-R18
-Ecounterdown4_vhd_vec_tst
-Z19 w1678985284
-R7
-R8
-!i122 1
-R0
-Z20 8CounterDown4.vwf.vht
-Z21 FCounterDown4.vwf.vht
-l0
-L32 1
-V;GC?2a[jnG6V5?CzHakgY0
-!s100 B?OO]3^Fh9CRc4R4aHA6H0
-R12
-32
-R13
-!i10b 1
-R14
-Z22 !s90 -work|work|CounterDown4.vwf.vht|
-!s107 CounterDown4.vwf.vht|
-!i113 1
-R17
-R18
-Acounterdown4_arch
-R7
-R8
-DEx4 work 24 counterdown4_vhd_vec_tst 0 22 ;GC?2a[jnG6V5?CzHakgY0
-!i122 1
-l45
-L34 31
-VjW5G@Mo`Sn8zX5R]D>d6G0
-!s100 ]5f=7Q4MbLK=biH1GQJfo2
-R12
-32
-R13
-!i10b 1
-R14
-R22
-Z23 !s107 CounterDown4.vwf.vht|
-!i113 1
-R17
-R18
diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_lib.qdb b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_lib.qdb
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_lib1_0.qdb b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_lib1_0.qdb
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_lib1_0.qpg b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_lib1_0.qpg
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_lib1_0.qtl b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_lib1_0.qtl
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_vmake b/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_vmake
deleted file mode 100644
index 37aa36a..0000000
--- a/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/work/_vmake
+++ /dev/null
@@ -1,4 +0,0 @@
-m255
-K4
-z0
-cModel Technology
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd.bak b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd.bak
deleted file mode 100644
index f83b36b..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd.bak
+++ /dev/null
@@ -1,21 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity FlipFlopD is
- port
- (
- clk : in std_logic;
- d : in std_logic;
- q : out std_logic;
- );
-end FlipFlopD;
-
-architecture Behav of FlipFlopD is
-begin
- process (clk)
- begin
- if (rising_edge(clk)) then
- q <= d;
- end if;
- end process;
-end Behav;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.qpf b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.qpf
deleted file mode 100644
index 31379c7..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 10:18:44 March 15, 2023
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "20.1"
-DATE = "10:18:44 March 15, 2023"
-
-# Revisions
-
-PROJECT_REVISION = "FlipFlopD_Demo"
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.qsf b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.qsf
deleted file mode 100644
index 4968362..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.qsf
+++ /dev/null
@@ -1,585 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 10:18:44 March 15, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# FlipFlopD_Demo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY FlipFlopD_Demo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:18:44 MARCH 15, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VHDL_FILE FlipFlopD_Demo.vhd
-set_global_assignment -name VHDL_FILE FlipFlopD.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE FlipFlopD.vwf
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.qsf.bak b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.qsf.bak
deleted file mode 100644
index fbd4315..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.qsf.bak
+++ /dev/null
@@ -1,66 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 10:18:44 March 15, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# FlipFlopD_Demo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY FlipFlopD_Demo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:18:44 MARCH 15, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VHDL_FILE FlipFlopD_Demo.vhd
-set_global_assignment -name VHDL_FILE FlipFlopD.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE FlipFlopD.vwf
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.qws b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.qws
deleted file mode 100644
index a7c1400..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.qws and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd.bak b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd.bak
deleted file mode 100644
index 86127d4..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd.bak
+++ /dev/null
@@ -1,22 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1664.all;
-
-entity FlipFlopD_Demo is
- port(
- SW : std_logic_vector(2 downto 0);
- KEY : std_logic_vector(0 downto 0);
- LEDR : std_logic_vector(0 downto 0)
- );
-end FlipFlopD_Demo
-
-architecture Shell of FlipFlopD_Demo is
-begin
- ff_d : work.FlipFlopD(Behav)
- port map(
- clk => KEY(0 downto 0),
- d => SW(0),
- set => SW(1),
- reset => SW(2),
- q => LEDR(0 downto 0),
- );
-end Shell;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(0).cnf.cdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(0).cnf.cdb
deleted file mode 100644
index 84b13e0..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(0).cnf.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(0).cnf.hdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(0).cnf.hdb
deleted file mode 100644
index c1a098e..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(0).cnf.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(1).cnf.cdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(1).cnf.cdb
deleted file mode 100644
index 5cfdcd7..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(1).cnf.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(1).cnf.hdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(1).cnf.hdb
deleted file mode 100644
index 306c6b3..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(1).cnf.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(2).cnf.cdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(2).cnf.cdb
deleted file mode 100644
index 5cc301f..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(2).cnf.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(2).cnf.hdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(2).cnf.hdb
deleted file mode 100644
index 0792066..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.(2).cnf.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.asm.qmsg b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.asm.qmsg
deleted file mode 100644
index c6154ab..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.asm.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678882359903 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678882359903 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 15 12:12:39 2023 " "Processing started: Wed Mar 15 12:12:39 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678882359903 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678882359903 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678882359904 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678882360385 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678882365189 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678882365383 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678882365926 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 15 12:12:45 2023 " "Processing ended: Wed Mar 15 12:12:45 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678882365926 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678882365926 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678882365926 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678882365926 ""}
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.asm.rdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.asm.rdb
deleted file mode 100644
index 3f2844f..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.asm_labs.ddb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.asm_labs.ddb
deleted file mode 100644
index ca0912a..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cbx.xml b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cbx.xml
deleted file mode 100644
index 8d1d1d1..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp.bpm b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp.bpm
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp.cdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp.cdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp.hdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp.hdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp.idb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp.idb
deleted file mode 100644
index dca46d2..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp.logdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp.logdb
deleted file mode 100644
index 00a0cdc..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp.logdb
+++ /dev/null
@@ -1,49 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;7;7;0;0;7;7;0;0;0;0;0;0;2;0;0;0;5;2;0;5;0;0;2;0;7;7;7;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,7;0;0;7;7;0;0;7;7;7;7;7;7;5;7;7;7;2;5;7;2;7;7;5;7;0;0;0;7;7,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,KEY[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp.rdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp.rdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp_merge.kpt b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cmp_merge.kpt
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index d9c61ce..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
deleted file mode 100644
index 41ec2ec..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.db_info b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.db_info
deleted file mode 100644
index 9c093be..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Wed Mar 15 10:46:55 2023
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.eda.qmsg b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.eda.qmsg
deleted file mode 100644
index ba29637..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678882371113 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678882371113 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 15 12:12:50 2023 " "Processing started: Wed Mar 15 12:12:50 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678882371113 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678882371113 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678882371113 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678882371552 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "FlipFlopD_Demo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/ simulation " "Generated file FlipFlopD_Demo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678882371624 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678882371652 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 15 12:12:51 2023 " "Processing ended: Wed Mar 15 12:12:51 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678882371652 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678882371652 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678882371652 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678882371652 ""}
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.fit.qmsg b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.fit.qmsg
deleted file mode 100644
index 29017c6..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.fit.qmsg
+++ /dev/null
@@ -1,46 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678882341769 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678882341769 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "FlipFlopD_Demo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"FlipFlopD_Demo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678882341774 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678882341906 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678882341906 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678882342565 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678882342572 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882342662 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882342662 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882342662 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882342662 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882342662 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882342662 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882342662 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882342662 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882342662 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678882342662 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/" { { 0 { 0 ""} 0 577 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678882342666 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/" { { 0 { 0 ""} 0 579 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678882342666 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/" { { 0 { 0 ""} 0 581 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678882342666 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/" { { 0 { 0 ""} 0 583 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678882342666 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/" { { 0 { 0 ""} 0 585 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678882342666 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678882342666 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678882342668 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "FlipFlopD_Demo.sdc " "Synopsys Design Constraints File file not found: 'FlipFlopD_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678882344075 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678882344075 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678882344078 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678882344078 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678882344078 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678882344398 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678882344398 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678882344399 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678882344399 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678882344400 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678882344400 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678882344400 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678882344400 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678882344406 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678882344406 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678882344406 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882344436 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678882344436 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678882344458 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678882344462 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678882348041 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678882348229 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678882348302 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678882348861 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678882348861 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678882349210 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y37 X115_Y48 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48"} { { 12 { 0 ""} 104 37 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678882355486 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678882355486 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678882355881 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678882355881 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678882355881 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678882355883 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.05 " "Total time spent on timing analysis during the Fitter is 0.05 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678882356096 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678882356107 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678882356547 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678882356547 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678882356945 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678882357579 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678882358021 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678882358115 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 518 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 518 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1146 " "Peak virtual memory: 1146 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678882358444 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 15 12:12:38 2023 " "Processing ended: Wed Mar 15 12:12:38 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678882358444 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678882358444 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678882358444 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678882358444 ""}
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.hier_info b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.hier_info
deleted file mode 100644
index d182fe8..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.hier_info
+++ /dev/null
@@ -1,18 +0,0 @@
-|FlipFlopD_Demo
-SW[0] => flipflopd:ff_d.d
-SW[1] => flipflopd:ff_d.set
-SW[2] => flipflopd:ff_d.rst
-KEY[0] => flipflopd:ff_d.clk
-KEY[1] => ~NO_FANOUT~
-LEDR[0] <= flipflopd:ff_d.q
-LEDR[1] <=
-
-
-|FlipFlopD_Demo|FlipFlopD:ff_d
-clk => q~reg0.CLK
-d => q.DATAA
-set => q.OUTPUTSELECT
-rst => q.OUTPUTSELECT
-q <= q~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.hif b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.hif
deleted file mode 100644
index 00a137a..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.hif and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.lpc.html b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.lpc.html
deleted file mode 100644
index 715c654..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.lpc.html
+++ /dev/null
@@ -1,34 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| ff_d |
-4 |
-0 |
-0 |
-0 |
-1 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.lpc.rdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.lpc.rdb
deleted file mode 100644
index 30986e0..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.lpc.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.lpc.txt b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.lpc.txt
deleted file mode 100644
index f7832a0..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.lpc.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; ff_d ; 4 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.ammdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.ammdb
deleted file mode 100644
index 790b913..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.bpm b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.bpm
deleted file mode 100644
index e41e3bd..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.bpm and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.cdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.cdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.hdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.hdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.kpt b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.kpt
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.logdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.qmsg b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.qmsg
deleted file mode 100644
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--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.qmsg
+++ /dev/null
@@ -1,16 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678882327474 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678882327475 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 15 12:12:07 2023 " "Processing started: Wed Mar 15 12:12:07 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678882327475 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882327475 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882327475 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678882327844 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678882327844 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FlipFlopD_Demo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FlipFlopD_Demo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FlipFlopD_Demo-Shell " "Found design unit 1: FlipFlopD_Demo-Shell" { } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882338356 ""} { "Info" "ISGN_ENTITY_NAME" "1 FlipFlopD_Demo " "Found entity 1: FlipFlopD_Demo" { } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882338356 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882338356 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FlipFlopD.vhd 3 1 " "Found 3 design units, including 1 entities, in source file FlipFlopD.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FlipFlopD-BehavS " "Found design unit 1: FlipFlopD-BehavS" { } { { "FlipFlopD.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882338357 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 FlipFlopD-BehavAs " "Found design unit 2: FlipFlopD-BehavAs" { } { { "FlipFlopD.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd" 31 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882338357 ""} { "Info" "ISGN_ENTITY_NAME" "1 FlipFlopD " "Found entity 1: FlipFlopD" { } { { "FlipFlopD.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882338357 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882338357 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "FlipFlopD_Demo " "Elaborating entity \"FlipFlopD_Demo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678882338433 ""}
-{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[1\] FlipFlopD_Demo.vhd(8) " "Using initial value X (don't care) for net \"LEDR\[1\]\" at FlipFlopD_Demo.vhd(8)" { } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 8 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882338435 "|FlipFlopD_Demo"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "FlipFlopD FlipFlopD:ff_d A:behavs " "Elaborating entity \"FlipFlopD\" using architecture \"A:behavs\" for hierarchy \"FlipFlopD:ff_d\"" { } { { "FlipFlopD_Demo.vhd" "ff_d" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 14 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678882338441 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[1\] GND " "Pin \"LEDR\[1\]\" is stuck at GND" { } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678882339208 "|FlipFlopD_Demo|LEDR[1]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1678882339208 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678882339364 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678882340198 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678882340198 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" { } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1678882340239 "|FlipFlopD_Demo|KEY[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1678882340239 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "8 " "Implemented 8 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678882340240 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678882340240 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678882340240 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678882340240 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "432 " "Peak virtual memory: 432 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678882340249 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 15 12:12:20 2023 " "Processing ended: Wed Mar 15 12:12:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678882340249 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678882340249 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:35 " "Total CPU time (on all processors): 00:00:35" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678882340249 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882340249 ""}
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.rdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map.rdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map_bb.cdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map_bb.cdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map_bb.hdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map_bb.hdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map_bb.logdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.npp.qmsg b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.npp.qmsg
deleted file mode 100644
index 9804e3e..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.npp.qmsg
+++ /dev/null
@@ -1,5 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678881098492 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678881098493 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 15 11:51:38 2023 " "Processing started: Wed Mar 15 11:51:38 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678881098493 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1678881098493 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp FlipFlopD_Demo -c FlipFlopD_Demo --netlist_type=sgate " "Command: quartus_npp FlipFlopD_Demo -c FlipFlopD_Demo --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1678881098493 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1678881098544 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1 Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "494 " "Peak virtual memory: 494 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678881098546 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 15 11:51:38 2023 " "Processing ended: Wed Mar 15 11:51:38 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678881098546 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678881098546 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678881098546 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1678881098546 ""}
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.pre_map.hdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.root_partition.map.reg_db.cdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.routing.rdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.rtlv.hdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.rtlv_sg.cdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.rtlv_sg.cdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.rtlv_sg_swap.cdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.rtlv_sg_swap.cdb
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sgate.nvd b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sgate.nvd
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sgate_sm.nvd b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sgate_sm.nvd
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sld_design_entry.sci b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.smart_action.txt b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.smart_action.txt
deleted file mode 100644
index c8e8a13..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sta.qmsg b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sta.qmsg
deleted file mode 100644
index bca7e65..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sta.qmsg
+++ /dev/null
@@ -1,44 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678882367187 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678882367187 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 15 12:12:46 2023 " "Processing started: Wed Mar 15 12:12:46 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678882367187 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678882367187 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta FlipFlopD_Demo -c FlipFlopD_Demo " "Command: quartus_sta FlipFlopD_Demo -c FlipFlopD_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678882367188 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678882367249 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678882367419 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678882367419 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678882367546 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678882367546 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "FlipFlopD_Demo.sdc " "Synopsys Design Constraints File file not found: 'FlipFlopD_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678882368401 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678882368401 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name KEY\[0\] KEY\[0\] " "create_clock -period 1.000 -name KEY\[0\] KEY\[0\]" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1678882368402 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1678882368402 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678882368403 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678882368403 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678882368404 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678882368412 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882368414 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882368418 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882368419 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882368420 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882368421 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1678882368421 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1678882368421 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882368422 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882368422 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -4.285 KEY\[0\] " " -3.000 -4.285 KEY\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882368422 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678882368422 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678882368441 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678882368477 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678882368915 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678882368948 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882368949 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882368951 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882368953 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882368954 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882368955 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1678882368956 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1678882368956 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882368957 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882368957 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -4.285 KEY\[0\] " " -3.000 -4.285 KEY\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882368957 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678882368957 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678882368980 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678882369094 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882369095 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882369096 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882369097 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882369098 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1678882369098 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1678882369098 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882369099 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882369099 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -4.129 KEY\[0\] " " -3.000 -4.129 KEY\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882369099 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678882369099 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678882369714 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678882369714 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "532 " "Peak virtual memory: 532 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678882369739 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 15 12:12:49 2023 " "Processing ended: Wed Mar 15 12:12:49 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678882369739 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678882369739 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678882369739 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678882369739 ""}
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sta.rdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sta.rdb
deleted file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.sta_cmp.7_slow_1200mv_85c.tdb
deleted file mode 100644
index 386a674..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.tis_db_list.ddb
deleted file mode 100644
index 73e5ec9..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index e6517ed..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index a6136fb..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index e01235a..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.tmw_info b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.tmw_info
deleted file mode 100644
index 7c97d30..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.tmw_info
+++ /dev/null
@@ -1,7 +0,0 @@
-start_full_compilation:s:00:00:45
-start_analysis_synthesis:s:00:00:14-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:18-start_full_compilation
-start_assembler:s:00:00:08-start_full_compilation
-start_timing_analyzer:s:00:00:03-start_full_compilation
-start_eda_netlist_writer:s:00:00:02-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.vpr.ammdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.vpr.ammdb
deleted file mode 100644
index b6606cf..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo_partition_pins.json b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo_partition_pins.json
deleted file mode 100644
index da2988f..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo_partition_pins.json
+++ /dev/null
@@ -1,29 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "LEDR[0]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- },
- {
- "name" : "SW[2]",
- "strict" : false
- },
- {
- "name" : "KEY[0]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/prev_cmp_FlipFlopD_Demo.qmsg b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/prev_cmp_FlipFlopD_Demo.qmsg
deleted file mode 100644
index c3cfcde..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/prev_cmp_FlipFlopD_Demo.qmsg
+++ /dev/null
@@ -1,127 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678882150604 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678882150609 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 15 12:09:10 2023 " "Processing started: Wed Mar 15 12:09:10 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678882150609 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882150609 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882150609 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678882150980 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678882150980 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FlipFlopD_Demo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FlipFlopD_Demo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FlipFlopD_Demo-Shell " "Found design unit 1: FlipFlopD_Demo-Shell" { } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882161426 ""} { "Info" "ISGN_ENTITY_NAME" "1 FlipFlopD_Demo " "Found entity 1: FlipFlopD_Demo" { } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882161426 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882161426 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FlipFlopD.vhd 3 1 " "Found 3 design units, including 1 entities, in source file FlipFlopD.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FlipFlopD-BehavS " "Found design unit 1: FlipFlopD-BehavS" { } { { "FlipFlopD.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882161427 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 FlipFlopD-BehavAs " "Found design unit 2: FlipFlopD-BehavAs" { } { { "FlipFlopD.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd" 31 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882161427 ""} { "Info" "ISGN_ENTITY_NAME" "1 FlipFlopD " "Found entity 1: FlipFlopD" { } { { "FlipFlopD.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882161427 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882161427 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "FlipFlopD_Demo " "Elaborating entity \"FlipFlopD_Demo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678882161503 ""}
-{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[1\] FlipFlopD_Demo.vhd(8) " "Using initial value X (don't care) for net \"LEDR\[1\]\" at FlipFlopD_Demo.vhd(8)" { } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 8 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882161504 "|FlipFlopD_Demo"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "FlipFlopD FlipFlopD:ff_d A:behavs " "Elaborating entity \"FlipFlopD\" using architecture \"A:behavs\" for hierarchy \"FlipFlopD:ff_d\"" { } { { "FlipFlopD_Demo.vhd" "ff_d" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 14 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678882161505 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[1\] GND " "Pin \"LEDR\[1\]\" is stuck at GND" { } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678882162260 "|FlipFlopD_Demo|LEDR[1]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1678882162260 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678882162408 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678882163244 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678882163244 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" { } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1678882163287 "|FlipFlopD_Demo|KEY[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1678882163287 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "8 " "Implemented 8 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678882163287 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678882163287 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678882163287 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678882163287 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "430 " "Peak virtual memory: 430 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678882163297 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 15 12:09:23 2023 " "Processing ended: Wed Mar 15 12:09:23 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678882163297 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678882163297 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:34 " "Total CPU time (on all processors): 00:00:34" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678882163297 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882163297 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1678882164638 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678882164639 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 15 12:09:24 2023 " "Processing started: Wed Mar 15 12:09:24 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678882164639 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1678882164639 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo " "Command: quartus_fit --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1678882164639 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1678882164696 ""}
-{ "Info" "0" "" "Project = FlipFlopD_Demo" { } { } 0 0 "Project = FlipFlopD_Demo" 0 0 "Fitter" 0 0 1678882164697 ""}
-{ "Info" "0" "" "Revision = FlipFlopD_Demo" { } { } 0 0 "Revision = FlipFlopD_Demo" 0 0 "Fitter" 0 0 1678882164698 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678882164793 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678882164793 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "FlipFlopD_Demo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"FlipFlopD_Demo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678882164798 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678882164938 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678882164938 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678882165588 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678882165595 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882165685 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882165685 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882165685 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882165685 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882165685 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882165685 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882165685 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882165685 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678882165685 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678882165685 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/" { { 0 { 0 ""} 0 577 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678882165689 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/" { { 0 { 0 ""} 0 579 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678882165689 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/" { { 0 { 0 ""} 0 581 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678882165689 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/" { { 0 { 0 ""} 0 583 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678882165689 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/" { { 0 { 0 ""} 0 585 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678882165689 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678882165689 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678882165691 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "FlipFlopD_Demo.sdc " "Synopsys Design Constraints File file not found: 'FlipFlopD_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678882167106 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678882167107 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678882167109 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678882167109 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678882167110 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678882167438 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678882167438 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678882167438 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678882167439 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678882167440 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678882167440 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678882167440 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678882167440 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678882167446 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678882167446 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678882167446 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678882167476 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678882167476 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678882167499 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678882167503 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678882171304 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678882171500 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678882171577 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678882172148 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678882172149 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678882172477 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y37 X115_Y48 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48"} { { 12 { 0 ""} 104 37 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678882178217 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678882178217 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678882178515 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678882178515 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678882178515 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678882178517 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678882178712 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678882178721 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678882179146 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678882179146 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678882179551 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678882180232 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678882180673 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678882180769 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 518 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 518 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1148 " "Peak virtual memory: 1148 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678882181100 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 15 12:09:41 2023 " "Processing ended: Wed Mar 15 12:09:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678882181100 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678882181100 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678882181100 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678882181100 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1678882182471 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678882182472 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 15 12:09:42 2023 " "Processing started: Wed Mar 15 12:09:42 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678882182472 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678882182472 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678882182472 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678882182836 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678882187054 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678882187240 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678882187801 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 15 12:09:47 2023 " "Processing ended: Wed Mar 15 12:09:47 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678882187801 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678882187801 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678882187801 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678882187801 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1678882187973 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1678882189103 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678882189104 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 15 12:09:48 2023 " "Processing started: Wed Mar 15 12:09:48 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678882189104 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678882189104 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta FlipFlopD_Demo -c FlipFlopD_Demo " "Command: quartus_sta FlipFlopD_Demo -c FlipFlopD_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678882189104 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678882189176 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678882189359 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678882189359 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678882189483 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678882189483 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "FlipFlopD_Demo.sdc " "Synopsys Design Constraints File file not found: 'FlipFlopD_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678882190403 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678882190404 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name KEY\[0\] KEY\[0\] " "create_clock -period 1.000 -name KEY\[0\] KEY\[0\]" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1678882190404 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1678882190404 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678882190405 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678882190405 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678882190406 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678882190414 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882190416 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882190420 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882190421 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882190422 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882190423 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1678882190424 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1678882190424 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882190425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882190425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -4.285 KEY\[0\] " " -3.000 -4.285 KEY\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882190425 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678882190425 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678882190442 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678882190480 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678882190922 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678882190954 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882190955 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882190957 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882190958 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882190959 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882190960 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1678882190960 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1678882190960 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882190961 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882190961 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -4.285 KEY\[0\] " " -3.000 -4.285 KEY\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882190961 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678882190961 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678882190978 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678882191084 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882191085 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882191087 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882191088 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678882191089 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1678882191089 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1678882191089 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882191090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882191090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -4.087 KEY\[0\] " " -3.000 -4.087 KEY\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678882191090 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678882191090 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678882191737 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678882191737 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "535 " "Peak virtual memory: 535 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678882191761 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 15 12:09:51 2023 " "Processing ended: Wed Mar 15 12:09:51 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678882191761 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678882191761 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678882191761 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678882191761 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1678882193093 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678882193094 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 15 12:09:52 2023 " "Processing started: Wed Mar 15 12:09:52 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678882193094 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678882193094 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678882193094 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678882193535 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "FlipFlopD_Demo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/ simulation " "Generated file FlipFlopD_Demo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678882193606 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678882193635 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 15 12:09:53 2023 " "Processing ended: Wed Mar 15 12:09:53 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678882193635 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678882193635 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678882193635 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678882193635 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 531 s " "Quartus Prime Full Compilation was successful. 0 errors, 531 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678882193800 ""}
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/README b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.db_info b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.db_info
deleted file mode 100644
index a868461..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Wed Mar 15 10:26:36 2023
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.ammdb
deleted file mode 100644
index da709ca..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.cdb
deleted file mode 100644
index 2a2ef11..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.dfp and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.hdb
deleted file mode 100644
index 716252d..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.rcfdb
deleted file mode 100644
index fe045f5..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.cmp.rcfdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.cdb
deleted file mode 100644
index 6ba2a78..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.dpi
deleted file mode 100644
index a959d5b..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.dpi and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hbdb.cdb
deleted file mode 100644
index 9492e3f..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hbdb.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hbdb.hdb
deleted file mode 100644
index 546621e..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hdb
deleted file mode 100644
index 0b47bb5..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.kpt
deleted file mode 100644
index 59bea11..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.root_partition.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.rrp.hdb b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.rrp.hdb
deleted file mode 100644
index b8ea6d9..0000000
Binary files a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/incremental_db/compiled_partitions/FlipFlopD_Demo.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.asm.rpt b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.asm.rpt
deleted file mode 100644
index 547496c..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for FlipFlopD_Demo
-Wed Mar 15 12:12:45 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: FlipFlopD_Demo.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Wed Mar 15 12:12:45 2023 ;
-; Revision Name ; FlipFlopD_Demo ;
-; Top-level Entity Name ; FlipFlopD_Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+--------------------------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+--------------------------------------------------------------------------------------------------------------+
-; File Name ;
-+--------------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.sof ;
-+--------------------------------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------+
-; Assembler Device Options: FlipFlopD_Demo.sof ;
-+----------------+-----------------------------+
-; Option ; Setting ;
-+----------------+-----------------------------+
-; JTAG usercode ; 0x00562EDB ;
-; Checksum ; 0x00562EDB ;
-+----------------+-----------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 15 12:12:39 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 367 megabytes
- Info: Processing ended: Wed Mar 15 12:12:45 2023
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:06
-
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.cdf b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.cdf
deleted file mode 100644
index a4fad9c..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.cdf
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition */
-JedecChain;
- FileRevision(JESD32A);
- DefaultMfr(6E);
-
- P ActionCode(Cfg)
- Device PartName(EP4CE115F29) Path("/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/") File("FlipFlopD_Demo.sof") MfrSpec(OpMask(1));
-
-ChainEnd;
-
-AlteraBegin;
- ChainType(JTAG);
-AlteraEnd;
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.done b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.done
deleted file mode 100644
index fe65517..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.done
+++ /dev/null
@@ -1 +0,0 @@
-Wed Mar 15 12:12:51 2023
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.eda.rpt b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.eda.rpt
deleted file mode 100644
index 52b71c1..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.eda.rpt
+++ /dev/null
@@ -1,94 +0,0 @@
-EDA Netlist Writer report for FlipFlopD_Demo
-Wed Mar 15 12:12:51 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Wed Mar 15 12:12:51 2023 ;
-; Revision Name ; FlipFlopD_Demo ;
-; Top-level Entity Name ; FlipFlopD_Demo ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+---------------------------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+---------------------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/FlipFlopD_Demo.vho ;
-+---------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 15 12:12:50 2023
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file FlipFlopD_Demo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 612 megabytes
- Info: Processing ended: Wed Mar 15 12:12:51 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.rpt b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.rpt
deleted file mode 100644
index 02dae7e..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.rpt
+++ /dev/null
@@ -1,2534 +0,0 @@
-Fitter report for FlipFlopD_Demo
-Wed Mar 15 12:12:38 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Control Signals
- 22. Routing Usage Summary
- 23. LAB Logic Elements
- 24. LAB-wide Signals
- 25. LAB Signals Sourced
- 26. LAB Signals Sourced Out
- 27. LAB Distinct Inputs
- 28. I/O Rules Summary
- 29. I/O Rules Details
- 30. I/O Rules Matrix
- 31. Fitter Device Options
- 32. Operating Settings and Conditions
- 33. Fitter Messages
- 34. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Wed Mar 15 12:12:38 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; FlipFlopD_Demo ;
-; Top-level Entity Name ; FlipFlopD_Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 2 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 1 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 1 / 114,480 ( < 1 % ) ;
-; Total registers ; 1 ;
-; Total pins ; 7 / 529 ( 1 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; CLOCK_50 ; PIN_Y2 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
-; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
-; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
-; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
-; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
-; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
-; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[0] ; PIN_E21 ; QSF Assignment ;
-; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
-; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
-; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[2] ; PIN_E19 ; QSF Assignment ;
-; Location ; ; ; LEDR[3] ; PIN_F21 ; QSF Assignment ;
-; Location ; ; ; LEDR[4] ; PIN_F18 ; QSF Assignment ;
-; Location ; ; ; LEDR[5] ; PIN_E18 ; QSF Assignment ;
-; Location ; ; ; LEDR[6] ; PIN_J19 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_H19 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; SW[10] ; PIN_AC24 ; QSF Assignment ;
-; Location ; ; ; SW[11] ; PIN_AB24 ; QSF Assignment ;
-; Location ; ; ; SW[12] ; PIN_AB23 ; QSF Assignment ;
-; Location ; ; ; SW[13] ; PIN_AA24 ; QSF Assignment ;
-; Location ; ; ; SW[14] ; PIN_AA23 ; QSF Assignment ;
-; Location ; ; ; SW[15] ; PIN_AA22 ; QSF Assignment ;
-; Location ; ; ; SW[16] ; PIN_Y24 ; QSF Assignment ;
-; Location ; ; ; SW[17] ; PIN_Y23 ; QSF Assignment ;
-; Location ; ; ; SW[3] ; PIN_AD27 ; QSF Assignment ;
-; Location ; ; ; SW[4] ; PIN_AB27 ; QSF Assignment ;
-; Location ; ; ; SW[5] ; PIN_AC26 ; QSF Assignment ;
-; Location ; ; ; SW[6] ; PIN_AD26 ; QSF Assignment ;
-; Location ; ; ; SW[7] ; PIN_AB26 ; QSF Assignment ;
-; Location ; ; ; SW[8] ; PIN_AC25 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AB25 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 27 ) ; 0.00 % ( 0 / 27 ) ; 0.00 % ( 0 / 27 ) ;
-; -- Achieved ; 0.00 % ( 0 / 27 ) ; 0.00 % ( 0 / 27 ) ; 0.00 % ( 0 / 27 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 17 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+-----------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-----------------------+
-; Total logic elements ; 2 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 1 ;
-; -- Register only ; 1 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 1 ;
-; -- <=2 input functions ; 0 ;
-; -- Register only ; 1 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers* ; 1 / 117,053 ( < 1 % ) ;
-; -- Dedicated logic registers ; 1 / 114,480 ( < 1 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 2 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 7 / 529 ( 1 % ) ;
-; -- Clock pins ; 0 / 7 ( 0 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ;
-; Maximum fan-out ; 1 ;
-; Highest non-global fan-out ; 1 ;
-; Total fan-out ; 18 ;
-; Average fan-out ; 0.69 ;
-+---------------------------------------------+-----------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 2 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 1 ; 0 ;
-; -- Register only ; 1 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 0 ; 0 ;
-; -- 3 input functions ; 1 ; 0 ;
-; -- <=2 input functions ; 0 ; 0 ;
-; -- Register only ; 1 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 1 ; 0 ;
-; -- arithmetic mode ; 0 ; 0 ;
-; ; ; ;
-; Total registers ; 1 ; 0 ;
-; -- Dedicated logic registers ; 1 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 2 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 7 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 13 ; 5 ;
-; -- Registered Connections ; 1 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 5 ; 0 ;
-; -- Output Ports ; 2 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; KEY[0] ; M23 ; 6 ; 115 ; 40 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; KEY[1] ; M21 ; 6 ; 115 ; 53 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+----------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+----------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+----------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 0 / 63 ( 0 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 3 / 65 ( 5 % ) ; 2.5V ; -- ;
-; 6 ; 3 / 58 ( 5 % ) ; 2.5V ; -- ;
-; 7 ; 2 / 72 ( 3 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+----------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA23 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA24 ; 279 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB24 ; 274 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB25 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB26 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB27 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC25 ; 272 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC26 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD27 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; KEY[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y24 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; KEY[1] ; Incomplete set of assignments ;
-; LEDR[0] ; Incomplete set of assignments ;
-; LEDR[1] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-; SW[1] ; Incomplete set of assignments ;
-; SW[2] ; Incomplete set of assignments ;
-; KEY[0] ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+----------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+----------------+--------------+
-; |FlipFlopD_Demo ; 2 (0) ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 1 (0) ; 1 (0) ; 0 (0) ; |FlipFlopD_Demo ; FlipFlopD_Demo ; work ;
-; |FlipFlopD:ff_d| ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 0 (0) ; |FlipFlopD_Demo|FlipFlopD:ff_d ; FlipFlopD ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+----------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-----------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; KEY[1] ; Input ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; KEY[0] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+---------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+---------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+---------------------------+-------------------+---------+
-; KEY[1] ; ; ;
-; SW[0] ; ; ;
-; - FlipFlopD:ff_d|q~0 ; 0 ; 6 ;
-; SW[1] ; ; ;
-; - FlipFlopD:ff_d|q~0 ; 0 ; 6 ;
-; SW[2] ; ; ;
-; - FlipFlopD:ff_d|q~0 ; 1 ; 6 ;
-; KEY[0] ; ; ;
-; - FlipFlopD:ff_d|q ; 0 ; 0 ;
-+---------------------------+-------------------+---------+
-
-
-+--------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+--------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+--------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
-; KEY[0] ; PIN_M23 ; 1 ; Clock ; no ; -- ; -- ; -- ;
-+--------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+-----------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+-----------------------+
-; Block interconnects ; 6 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 2 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 9 / 209,544 ( < 1 % ) ;
-; Direct links ; 0 / 342,891 ( 0 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 0 / 119,088 ( 0 % ) ;
-; R24 interconnects ; 2 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 2 / 289,782 ( < 1 % ) ;
-+-----------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 1.00) ; Number of LABs (Total = 2) ;
-+--------------------------------------------+-----------------------------+
-; 1 ; 2 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-+--------------------------------------------+-----------------------------+
-
-
-+------------------------------------------------------------------+
-; LAB-wide Signals ;
-+------------------------------------+-----------------------------+
-; LAB-wide Signals (Average = 0.50) ; Number of LABs (Total = 2) ;
-+------------------------------------+-----------------------------+
-; 1 Clock ; 1 ;
-+------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 1.00) ; Number of LABs (Total = 2) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 2 ;
-+---------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 2) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 2 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 2.50) ; Number of LABs (Total = 2) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 1 ;
-; 3 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 7 ; 7 ; 0 ; 0 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 5 ; 2 ; 0 ; 5 ; 0 ; 0 ; 2 ; 0 ; 7 ; 7 ; 7 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 7 ; 0 ; 0 ; 7 ; 7 ; 0 ; 0 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 5 ; 7 ; 7 ; 7 ; 2 ; 5 ; 7 ; 2 ; 7 ; 7 ; 5 ; 7 ; 0 ; 0 ; 0 ; 7 ; 7 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; KEY[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "FlipFlopD_Demo"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'FlipFlopD_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.05 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 518 warnings
- Info: Peak virtual memory: 1146 megabytes
- Info: Processing ended: Wed Mar 15 12:12:38 2023
- Info: Elapsed time: 00:00:17
- Info: Total CPU time (on all processors): 00:00:25
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.smsg b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.summary b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.summary
deleted file mode 100644
index 63e7d07..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Wed Mar 15 12:12:38 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : FlipFlopD_Demo
-Top-level Entity Name : FlipFlopD_Demo
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 2 / 114,480 ( < 1 % )
- Total combinational functions : 1 / 114,480 ( < 1 % )
- Dedicated logic registers : 1 / 114,480 ( < 1 % )
-Total registers : 1
-Total pins : 7 / 529 ( 1 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.flow.rpt b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.flow.rpt
deleted file mode 100644
index 91f23cc..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.flow.rpt
+++ /dev/null
@@ -1,136 +0,0 @@
-Flow report for FlipFlopD_Demo
-Wed Mar 15 12:12:51 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Wed Mar 15 12:12:51 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; FlipFlopD_Demo ;
-; Top-level Entity Name ; FlipFlopD_Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 2 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 1 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 1 / 114,480 ( < 1 % ) ;
-; Total registers ; 1 ;
-; Total pins ; 7 / 529 ( 1 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/15/2023 12:12:07 ;
-; Main task ; Compilation ;
-; Revision Name ; FlipFlopD_Demo ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 198516037997543.167888232715660 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:13 ; 1.0 ; 432 MB ; 00:00:34 ;
-; Fitter ; 00:00:17 ; 1.0 ; 1146 MB ; 00:00:25 ;
-; Assembler ; 00:00:06 ; 1.0 ; 367 MB ; 00:00:06 ;
-; Timing Analyzer ; 00:00:03 ; 1.0 ; 532 MB ; 00:00:03 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 612 MB ; 00:00:01 ;
-; Total ; 00:00:40 ; -- ; -- ; 00:01:09 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo
-quartus_fit --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo
-quartus_asm --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo
-quartus_sta FlipFlopD_Demo -c FlipFlopD_Demo
-quartus_eda --read_settings_files=off --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo
-
-
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.jdi b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.jdi
deleted file mode 100644
index 4a00cb7..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.map.rpt b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.map.rpt
deleted file mode 100644
index 78dc4ea..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.map.rpt
+++ /dev/null
@@ -1,297 +0,0 @@
-Analysis & Synthesis report for FlipFlopD_Demo
-Wed Mar 15 12:12:20 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Post-Synthesis Netlist Statistics for Top Partition
- 10. Elapsed Time Per Partition
- 11. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Wed Mar 15 12:12:20 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; FlipFlopD_Demo ;
-; Top-level Entity Name ; FlipFlopD_Demo ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 1 ;
-; Total combinational functions ; 1 ;
-; Dedicated logic registers ; 1 ;
-; Total registers ; 1 ;
-; Total pins ; 7 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; FlipFlopD_Demo ; FlipFlopD_Demo ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------------------------------+---------+
-; FlipFlopD_Demo.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd ; ;
-; FlipFlopD.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd ; ;
-+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------------------------------+---------+
-
-
-+----------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+------------------+
-; Resource ; Usage ;
-+---------------------------------------------+------------------+
-; Estimated Total logic elements ; 1 ;
-; ; ;
-; Total combinational functions ; 1 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 1 ;
-; -- <=2 input functions ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers ; 1 ;
-; -- Dedicated logic registers ; 1 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 7 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; FlipFlopD:ff_d|q ;
-; Maximum fan-out ; 1 ;
-; Total fan-out ; 13 ;
-; Average fan-out ; 0.81 ;
-+---------------------------------------------+------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+----------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+----------------+--------------+
-; |FlipFlopD_Demo ; 1 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; |FlipFlopD_Demo ; FlipFlopD_Demo ; work ;
-; |FlipFlopD:ff_d| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FlipFlopD_Demo|FlipFlopD:ff_d ; FlipFlopD ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+----------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 1 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 7 ;
-; cycloneiii_ff ; 1 ;
-; plain ; 1 ;
-; cycloneiii_lcell_comb ; 2 ;
-; normal ; 2 ;
-; 0 data inputs ; 1 ;
-; 3 data inputs ; 1 ;
-; ; ;
-; Max LUT depth ; 1.00 ;
-; Average LUT depth ; 0.57 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:01 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 15 12:12:07 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 2 design units, including 1 entities, in source file FlipFlopD_Demo.vhd
- Info (12022): Found design unit 1: FlipFlopD_Demo-Shell File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd Line: 12
- Info (12023): Found entity 1: FlipFlopD_Demo File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd Line: 4
-Info (12021): Found 3 design units, including 1 entities, in source file FlipFlopD.vhd
- Info (12022): Found design unit 1: FlipFlopD-BehavS File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd Line: 15
- Info (12022): Found design unit 2: FlipFlopD-BehavAs File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd Line: 31
- Info (12023): Found entity 1: FlipFlopD File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd Line: 4
-Info (12127): Elaborating entity "FlipFlopD_Demo" for the top level hierarchy
-Warning (10873): Using initial value X (don't care) for net "LEDR[1]" at FlipFlopD_Demo.vhd(8) File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd Line: 8
-Info (12129): Elaborating entity "FlipFlopD" using architecture "A:behavs" for hierarchy "FlipFlopD:ff_d" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd Line: 14
-Warning (13024): Output pins are stuck at VCC or GND
- Warning (13410): Pin "LEDR[1]" is stuck at GND File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd Line: 8
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 1 input pin(s) that do not drive logic
- Warning (15610): No output dependent on input pin "KEY[1]" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd Line: 7
-Info (21057): Implemented 8 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 5 input pins
- Info (21059): Implemented 2 output pins
- Info (21061): Implemented 1 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 6 warnings
- Info: Peak virtual memory: 432 megabytes
- Info: Processing ended: Wed Mar 15 12:12:20 2023
- Info: Elapsed time: 00:00:13
- Info: Total CPU time (on all processors): 00:00:35
-
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.map.summary b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.map.summary
deleted file mode 100644
index 73d77dd..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Wed Mar 15 12:12:20 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : FlipFlopD_Demo
-Top-level Entity Name : FlipFlopD_Demo
-Family : Cyclone IV E
-Total logic elements : 1
- Total combinational functions : 1
- Dedicated logic registers : 1
-Total registers : 1
-Total pins : 7
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.pin b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.pin
deleted file mode 100644
index ac71e23..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "FlipFlopD_Demo" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5 :
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC26 : : : : 5 :
-SW[2] : AC27 : input : 2.5 V : : 5 : Y
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7 :
-VCCIO7 : E20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
-VCCIO7 : E23 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7 :
-LEDR[1] : F19 : output : 2.5 V : : 7 : Y
-GND : F20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
-LEDR[0] : G19 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
-VCCIO7 : H18 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7 :
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-KEY[1] : M21 : input : 2.5 V : : 6 : Y
-MSEL2 : M22 : : : : 6 :
-KEY[0] : M23 : input : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-GND+ : Y2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.sld b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.sta.rpt b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.sta.rpt
deleted file mode 100644
index 00783c1..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.sta.rpt
+++ /dev/null
@@ -1,472 +0,0 @@
-Timing Analyzer report for FlipFlopD_Demo
-Wed Mar 15 12:12:49 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Clock Status Summary
- 37. Unconstrained Input Ports
- 38. Unconstrained Output Ports
- 39. Unconstrained Input Ports
- 40. Unconstrained Output Ports
- 41. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; FlipFlopD_Demo ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.1% ;
-+----------------------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------+
-; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------+
-; KEY[0] ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { KEY[0] } ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------+
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
-+--------+--------+---------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+--------+--------+---------------------------------+
-; KEY[0] ; -3.000 ; -4.285 ;
-+--------+--------+---------------------------------+
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------+
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-+--------+--------+--------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+--------+--------+--------------------------------+
-; KEY[0] ; -3.000 ; -4.285 ;
-+--------+--------+--------------------------------+
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------+
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-+--------+--------+--------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+--------+--------+--------------------------------+
-; KEY[0] ; -3.000 ; -4.129 ;
-+--------+--------+--------------------------------+
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; -3.000 ;
-; KEY[0] ; N/A ; N/A ; N/A ; N/A ; -3.000 ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; -4.285 ;
-; KEY[0] ; N/A ; N/A ; N/A ; N/A ; -4.285 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 3 ; 3 ;
-; Unconstrained Input Port Paths ; 3 ; 3 ;
-; Unconstrained Output Ports ; 1 ; 1 ;
-; Unconstrained Output Port Paths ; 1 ; 1 ;
-+---------------------------------+-------+------+
-
-
-+--------------------------------------+
-; Clock Status Summary ;
-+--------+--------+------+-------------+
-; Target ; Clock ; Type ; Status ;
-+--------+--------+------+-------------+
-; KEY[0] ; KEY[0] ; Base ; Constrained ;
-+--------+--------+------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 15 12:12:46 2023
-Info: Command: quartus_sta FlipFlopD_Demo -c FlipFlopD_Demo
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'FlipFlopD_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
- Info (332105): create_clock -period 1.000 -name KEY[0] KEY[0]
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -4.285 KEY[0]
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -4.285 KEY[0]
-Info: Analyzing Fast 1200mV 0C Model
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -4.129 KEY[0]
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 532 megabytes
- Info: Processing ended: Wed Mar 15 12:12:49 2023
- Info: Elapsed time: 00:00:03
- Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.sta.summary b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.sta.summary
deleted file mode 100644
index 5a6e4d2..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.sta.summary
+++ /dev/null
@@ -1,17 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-Type : Slow 1200mV 85C Model Minimum Pulse Width 'KEY[0]'
-Slack : -3.000
-TNS : -4.285
-
-Type : Slow 1200mV 0C Model Minimum Pulse Width 'KEY[0]'
-Slack : -3.000
-TNS : -4.285
-
-Type : Fast 1200mV 0C Model Minimum Pulse Width 'KEY[0]'
-Slack : -3.000
-TNS : -4.129
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/FlipFlopD_Demo.sft b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/FlipFlopD_Demo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/FlipFlopD_Demo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/FlipFlopD_Demo.vho b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/FlipFlopD_Demo.vho
deleted file mode 100644
index 3251724..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/FlipFlopD_Demo.vho
+++ /dev/null
@@ -1,259 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/15/2023 12:12:51"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY ALTERA;
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY FlipFlopD_Demo IS
- PORT (
- SW : IN std_logic_vector(2 DOWNTO 0);
- KEY : IN std_logic_vector(1 DOWNTO 0);
- LEDR : OUT std_logic_vector(1 DOWNTO 0)
- );
-END FlipFlopD_Demo;
-
--- Design Ports Information
--- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF FlipFlopD_Demo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_SW : std_logic_vector(2 DOWNTO 0);
-SIGNAL ww_KEY : std_logic_vector(1 DOWNTO 0);
-SIGNAL ww_LEDR : std_logic_vector(1 DOWNTO 0);
-SIGNAL \KEY[1]~input_o\ : std_logic;
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \LEDR[1]~output_o\ : std_logic;
-SIGNAL \KEY[0]~input_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[2]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \ff_d|q~0_combout\ : std_logic;
-SIGNAL \ff_d|q~q\ : std_logic;
-SIGNAL \ALT_INV_KEY[0]~input_o\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-ww_SW <= SW;
-ww_KEY <= KEY;
-LEDR <= ww_LEDR;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\ALT_INV_KEY[0]~input_o\ <= NOT \KEY[0]~input_o\;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X69_Y73_N16
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \ff_d|q~q\,
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N2
-\LEDR[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => GND,
- devoe => ww_devoe,
- o => \LEDR[1]~output_o\);
-
--- Location: IOIBUF_X115_Y40_N8
-\KEY[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY(0),
- o => \KEY[0]~input_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N8
-\SW[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(2),
- o => \SW[2]~input_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: LCCOMB_X114_Y17_N8
-\ff_d|q~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \ff_d|q~0_combout\ = (!\SW[2]~input_o\ & ((\SW[1]~input_o\) # (\SW[0]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000111100001010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[1]~input_o\,
- datac => \SW[2]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \ff_d|q~0_combout\);
-
--- Location: FF_X114_Y40_N17
-\ff_d|q\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \ALT_INV_KEY[0]~input_o\,
- asdata => \ff_d|q~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \ff_d|q~q\);
-
--- Location: IOIBUF_X115_Y53_N15
-\KEY[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY(1),
- o => \KEY[1]~input_o\);
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-
-ww_LEDR(1) <= \LEDR[1]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/FlipFlopD_Demo_modelsim.xrf b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/FlipFlopD_Demo_modelsim.xrf
deleted file mode 100644
index 1c2b065..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/modelsim/FlipFlopD_Demo_modelsim.xrf
+++ /dev/null
@@ -1,20 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vwf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cbx.xml
-design_name = hard_block
-design_name = FlipFlopD_Demo
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, FlipFlopD_Demo, 1
-instance = comp, \LEDR[1]~output\, LEDR[1]~output, FlipFlopD_Demo, 1
-instance = comp, \KEY[0]~input\, KEY[0]~input, FlipFlopD_Demo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, FlipFlopD_Demo, 1
-instance = comp, \SW[2]~input\, SW[2]~input, FlipFlopD_Demo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, FlipFlopD_Demo, 1
-instance = comp, \ff_d|q~0\, ff_d|q~0, FlipFlopD_Demo, 1
-instance = comp, \ff_d|q\, ff_d|q, FlipFlopD_Demo, 1
-instance = comp, \KEY[1]~input\, KEY[1]~input, FlipFlopD_Demo, 1
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD.vwf.vht b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD.vwf.vht
deleted file mode 100644
index 547041b..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD.vwf.vht
+++ /dev/null
@@ -1,326 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- *****************************************************************************
--- This file contains a Vhdl test bench with test vectors .The test vectors
--- are exported from a vector file in the Quartus Waveform Editor and apply to
--- the top level entity of the current Quartus project .The user can use this
--- testbench to simulate his design using a third-party simulation tool .
--- *****************************************************************************
--- Generated on "03/15/2023 10:57:35"
-
--- Vhdl Test Bench(with test vectors) for design : FlipFlopD
---
--- Simulation tool : 3rd Party
---
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY FlipFlopD_vhd_vec_tst IS
-END FlipFlopD_vhd_vec_tst;
-ARCHITECTURE FlipFlopD_arch OF FlipFlopD_vhd_vec_tst IS
--- constants
--- signals
-SIGNAL clk : STD_LOGIC;
-SIGNAL d : STD_LOGIC;
-SIGNAL q : STD_LOGIC;
-SIGNAL rst : STD_LOGIC;
-SIGNAL set : STD_LOGIC;
-COMPONENT FlipFlopD
- PORT (
- clk : IN STD_LOGIC;
- d : IN STD_LOGIC;
- q : OUT STD_LOGIC;
- rst : IN STD_LOGIC;
- set : IN STD_LOGIC
- );
-END COMPONENT;
-BEGIN
- i1 : FlipFlopD
- PORT MAP (
--- list connections between master ports and signals
- clk => clk,
- d => d,
- q => q,
- rst => rst,
- set => set
- );
-
--- clk
-t_prcs_clk: PROCESS
-BEGIN
-LOOP
- clk <= '0';
- WAIT FOR 20000 ps;
- clk <= '1';
- WAIT FOR 20000 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_clk;
-
--- rst
-t_prcs_rst: PROCESS
-BEGIN
- rst <= '0';
- WAIT FOR 50000 ps;
- rst <= '1';
- WAIT FOR 70000 ps;
- rst <= '0';
- WAIT FOR 310000 ps;
- rst <= '1';
- WAIT FOR 120000 ps;
- rst <= '0';
-WAIT;
-END PROCESS t_prcs_rst;
-
--- set
-t_prcs_set: PROCESS
-BEGIN
- set <= '0';
- WAIT FOR 200000 ps;
- set <= '1';
- WAIT FOR 90000 ps;
- set <= '0';
- WAIT FOR 140000 ps;
- set <= '1';
- WAIT FOR 120000 ps;
- set <= '0';
-WAIT;
-END PROCESS t_prcs_set;
-
--- d
-t_prcs_d: PROCESS
-BEGIN
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 10000 ps;
- d <= '1';
- WAIT FOR 20000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 15000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 20000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 15000 ps;
- d <= '1';
- WAIT FOR 15000 ps;
- d <= '0';
- WAIT FOR 10000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 10000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 15000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 15000 ps;
- d <= '1';
- WAIT FOR 15000 ps;
- d <= '0';
- WAIT FOR 20000 ps;
- d <= '1';
- WAIT FOR 20000 ps;
- d <= '0';
- WAIT FOR 30000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 10000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 10000 ps;
- d <= '1';
- WAIT FOR 20000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 10000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 15000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 15000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 20000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 10000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 10000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 10000 ps;
- d <= '1';
- WAIT FOR 20000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 25000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 15000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 20000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 20000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 10000 ps;
- d <= '1';
- WAIT FOR 15000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 10000 ps;
- d <= '0';
- WAIT FOR 20000 ps;
- d <= '1';
- WAIT FOR 15000 ps;
- d <= '0';
- WAIT FOR 5000 ps;
- d <= '1';
- WAIT FOR 5000 ps;
- d <= '0';
- WAIT FOR 10000 ps;
- d <= '1';
- WAIT FOR 20000 ps;
- d <= '0';
-WAIT;
-END PROCESS t_prcs_d;
-END FlipFlopD_arch;
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.do b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.do
deleted file mode 100644
index 30142ac..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.do
+++ /dev/null
@@ -1,18 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vcom -work work FlipFlopD_Demo.vho
-vcom -work work FlipFlopD.vwf.vht
-vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.FlipFlopD_vhd_vec_tst
-vcd file -direction FlipFlopD_Demo.msim.vcd
-vcd add -internal FlipFlopD_vhd_vec_tst/*
-vcd add -internal FlipFlopD_vhd_vec_tst/i1/*
-proc simTimestamp {} {
- echo "Simulation time: $::now ps"
- if { [string equal running [runStatus]] } {
- after 2500 simTimestamp
- }
-}
-after 2500 simTimestamp
-run -all
-quit -f
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.msim.vcd b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.msim.vcd
deleted file mode 100644
index 969d32e..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.msim.vcd
+++ /dev/null
@@ -1,815 +0,0 @@
-$comment
- File created using the following command:
- vcd file FlipFlopD_Demo.msim.vcd -direction
-$end
-$date
- Wed Mar 15 10:57:36 2023
-$end
-$version
- ModelSim Version 2020.1
-$end
-$timescale
- 1ps
-$end
-
-$scope module flipflopd_vhd_vec_tst $end
-$var wire 1 ! clk $end
-$var wire 1 " d $end
-$var wire 1 # q $end
-$var wire 1 $ rst $end
-$var wire 1 % set $end
-
-$scope module i1 $end
-$var wire 1 & gnd $end
-$var wire 1 ' vcc $end
-$var wire 1 ( unknown $end
-$var wire 1 ) devoe $end
-$var wire 1 * devclrn $end
-$var wire 1 + devpor $end
-$var wire 1 , ww_devoe $end
-$var wire 1 - ww_devclrn $end
-$var wire 1 . ww_devpor $end
-$var wire 1 / ww_clk $end
-$var wire 1 0 ww_d $end
-$var wire 1 1 ww_set $end
-$var wire 1 2 ww_rst $end
-$var wire 1 3 ww_q $end
-$var wire 1 4 \q~output_o\ $end
-$var wire 1 5 \clk~input_o\ $end
-$var wire 1 6 \d~input_o\ $end
-$var wire 1 7 \set~input_o\ $end
-$var wire 1 8 \rst~input_o\ $end
-$var wire 1 9 \q~0_combout\ $end
-$var wire 1 : \q~reg0_q\ $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0!
-0"
-0#
-0$
-0%
-0&
-1'
-x(
-1)
-1*
-1+
-1,
-1-
-1.
-0/
-00
-01
-02
-03
-04
-05
-06
-07
-08
-09
-0:
-$end
-#5000
-1"
-10
-16
-19
-#15000
-0"
-00
-06
-09
-#20000
-1"
-1!
-10
-1/
-15
-16
-19
-#25000
-0"
-00
-06
-09
-#35000
-1"
-10
-16
-19
-#40000
-0!
-0/
-05
-#50000
-1$
-12
-18
-09
-#55000
-0"
-00
-06
-#60000
-1"
-1!
-10
-1/
-15
-16
-#70000
-0"
-00
-06
-#75000
-1"
-10
-16
-#80000
-0"
-0!
-00
-0/
-05
-06
-#85000
-1"
-10
-16
-#90000
-0"
-00
-06
-#100000
-1!
-1/
-15
-#105000
-1"
-10
-16
-#115000
-0"
-00
-06
-#120000
-1"
-0!
-0$
-10
-0/
-02
-08
-05
-16
-19
-#130000
-0"
-00
-06
-09
-#140000
-1!
-1/
-15
-#150000
-1"
-10
-16
-19
-#155000
-0"
-00
-06
-09
-#160000
-0!
-0/
-05
-#170000
-1"
-10
-16
-19
-#180000
-1!
-1/
-15
-1:
-14
-13
-1#
-#185000
-0"
-00
-06
-09
-#195000
-1"
-10
-16
-19
-#200000
-0!
-1%
-0/
-11
-17
-05
-#205000
-0"
-00
-06
-#210000
-1"
-10
-16
-#215000
-0"
-00
-06
-#220000
-1!
-1/
-15
-#225000
-1"
-10
-16
-#230000
-0"
-00
-06
-#235000
-1"
-10
-16
-#240000
-0!
-0/
-05
-#250000
-0"
-00
-06
-#255000
-1"
-10
-16
-#260000
-0"
-1!
-00
-1/
-15
-06
-#275000
-1"
-10
-16
-#280000
-0!
-0/
-05
-#290000
-0"
-0%
-00
-01
-07
-06
-09
-#300000
-1!
-1/
-15
-0:
-04
-03
-0#
-#310000
-1"
-10
-16
-19
-#320000
-0!
-0/
-05
-#330000
-0"
-00
-06
-09
-#340000
-1!
-1/
-15
-#360000
-0!
-1"
-0/
-10
-16
-05
-19
-#365000
-0"
-00
-06
-09
-#375000
-1"
-10
-16
-19
-#380000
-1!
-1/
-15
-1:
-14
-13
-1#
-#385000
-0"
-00
-06
-09
-#390000
-1"
-10
-16
-19
-#400000
-0"
-0!
-00
-0/
-05
-06
-09
-#405000
-1"
-10
-16
-19
-#410000
-0"
-00
-06
-09
-#420000
-1"
-1!
-10
-1/
-15
-16
-19
-0:
-04
-03
-0#
-#430000
-1%
-1$
-11
-12
-18
-17
-09
-#440000
-0"
-0!
-00
-0/
-05
-06
-#445000
-1"
-10
-16
-#455000
-0"
-00
-06
-#460000
-1"
-1!
-10
-1/
-15
-16
-#465000
-0"
-00
-06
-#475000
-1"
-10
-16
-#480000
-0"
-0!
-00
-0/
-05
-06
-#485000
-1"
-10
-16
-#490000
-0"
-00
-06
-#495000
-1"
-10
-16
-#500000
-1!
-1/
-15
-#510000
-0"
-00
-06
-#515000
-1"
-10
-16
-#520000
-0"
-0!
-00
-0/
-05
-06
-#525000
-1"
-10
-16
-#530000
-0"
-00
-06
-#535000
-1"
-10
-16
-#540000
-0"
-1!
-00
-1/
-15
-06
-#550000
-0%
-0$
-01
-02
-08
-07
-#555000
-1"
-10
-16
-19
-#560000
-0!
-0/
-05
-#565000
-0"
-00
-06
-09
-#570000
-1"
-10
-16
-19
-#580000
-0"
-1!
-00
-1/
-15
-06
-09
-1:
-14
-13
-1#
-#585000
-1"
-10
-16
-19
-#590000
-0"
-00
-06
-09
-#595000
-1"
-10
-16
-19
-#600000
-0!
-0/
-05
-#605000
-0"
-00
-06
-09
-#610000
-1"
-10
-16
-19
-#615000
-0"
-00
-06
-09
-#620000
-1"
-1!
-10
-1/
-15
-16
-19
-0:
-04
-03
-0#
-#625000
-0"
-00
-06
-09
-#640000
-0!
-0/
-05
-#645000
-1"
-10
-16
-19
-#650000
-0"
-00
-06
-09
-#660000
-1"
-1!
-10
-1/
-15
-16
-19
-#665000
-0"
-00
-06
-09
-#670000
-1"
-10
-16
-19
-#680000
-0"
-0!
-00
-0/
-05
-06
-09
-#690000
-1"
-10
-16
-19
-#695000
-0"
-00
-06
-09
-#700000
-1!
-1/
-15
-#705000
-1"
-10
-16
-19
-#720000
-0!
-0/
-05
-#725000
-0"
-00
-06
-09
-#730000
-1"
-10
-16
-19
-#735000
-0"
-00
-06
-09
-#740000
-1"
-1!
-10
-1/
-15
-16
-19
-#750000
-0"
-00
-06
-09
-#760000
-0!
-0/
-05
-#775000
-1"
-10
-16
-19
-#780000
-1!
-1/
-15
-1:
-14
-13
-1#
-#785000
-0"
-00
-06
-09
-#790000
-1"
-10
-16
-19
-#800000
-0"
-0!
-00
-0/
-05
-06
-09
-#815000
-1"
-10
-16
-19
-#820000
-0"
-1!
-00
-1/
-15
-06
-09
-#840000
-1"
-0!
-10
-0/
-05
-16
-19
-#845000
-0"
-00
-06
-09
-#860000
-1!
-1/
-15
-0:
-04
-03
-0#
-#865000
-1"
-10
-16
-19
-#870000
-0"
-00
-06
-09
-#880000
-1"
-0!
-10
-0/
-05
-16
-19
-#895000
-0"
-00
-06
-09
-#900000
-1"
-1!
-10
-1/
-15
-16
-19
-#905000
-0"
-00
-06
-09
-#910000
-1"
-10
-16
-19
-#920000
-0"
-0!
-00
-0/
-05
-06
-09
-#940000
-1"
-1!
-10
-1/
-15
-16
-19
-#955000
-0"
-00
-06
-09
-#960000
-1"
-0!
-10
-0/
-05
-16
-19
-#965000
-0"
-00
-06
-09
-#975000
-1"
-10
-16
-19
-#980000
-1!
-1/
-15
-1:
-14
-13
-1#
-#995000
-0"
-00
-06
-09
-#1000000
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.sft b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.vho b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.vho
deleted file mode 100644
index 904899a..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.vho
+++ /dev/null
@@ -1,163 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/15/2023 10:57:36"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY ALTERA;
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY FlipFlopD IS
- PORT (
- clk : IN std_logic;
- d : IN std_logic;
- set : IN std_logic;
- rst : IN std_logic;
- q : OUT std_logic
- );
-END FlipFlopD;
-
-ARCHITECTURE structure OF FlipFlopD IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_clk : std_logic;
-SIGNAL ww_d : std_logic;
-SIGNAL ww_set : std_logic;
-SIGNAL ww_rst : std_logic;
-SIGNAL ww_q : std_logic;
-SIGNAL \q~output_o\ : std_logic;
-SIGNAL \clk~input_o\ : std_logic;
-SIGNAL \d~input_o\ : std_logic;
-SIGNAL \set~input_o\ : std_logic;
-SIGNAL \rst~input_o\ : std_logic;
-SIGNAL \q~0_combout\ : std_logic;
-SIGNAL \q~reg0_q\ : std_logic;
-
-BEGIN
-
-ww_clk <= clk;
-ww_d <= d;
-ww_set <= set;
-ww_rst <= rst;
-q <= ww_q;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
-\q~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \q~reg0_q\,
- devoe => ww_devoe,
- o => \q~output_o\);
-
-\clk~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_clk,
- o => \clk~input_o\);
-
-\d~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_d,
- o => \d~input_o\);
-
-\set~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_set,
- o => \set~input_o\);
-
-\rst~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_rst,
- o => \rst~input_o\);
-
-\q~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \q~0_combout\ = (!\rst~input_o\ & ((\d~input_o\) # (\set~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000011101110",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \d~input_o\,
- datab => \set~input_o\,
- datad => \rst~input_o\,
- combout => \q~0_combout\);
-
-\q~reg0\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \clk~input_o\,
- d => \q~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \q~reg0_q\);
-
-ww_q <= \q~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo_20230315103947.sim.vwf b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo_20230315103947.sim.vwf
deleted file mode 100644
index ab17047..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo_20230315103947.sim.vwf
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("clk")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("d")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("q")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-TRANSITION_LIST("clk")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- }
- }
-}
-
-TRANSITION_LIST("d")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 30.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 25.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 35.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 30.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- }
- }
-}
-
-TRANSITION_LIST("q")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 220.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "clk";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "d";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "q";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo_20230315105737.sim.vwf b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo_20230315105737.sim.vwf
deleted file mode 100644
index b7e3385..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo_20230315105737.sim.vwf
+++ /dev/null
@@ -1,375 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("clk")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("d")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("q")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("rst")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("set")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-TRANSITION_LIST("clk")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- }
- }
-}
-
-TRANSITION_LIST("d")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 30.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 25.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 15.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 10.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 15.0;
- LEVEL 0 FOR 5.0;
- LEVEL 1 FOR 5.0;
- LEVEL 0 FOR 10.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 5.0;
- }
- }
-}
-
-TRANSITION_LIST("q")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 180.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 160.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 160.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 20.0;
- }
- }
-}
-
-TRANSITION_LIST("rst")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 50.0;
- LEVEL 1 FOR 70.0;
- LEVEL 0 FOR 310.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 450.0;
- }
- }
-}
-
-TRANSITION_LIST("set")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 90.0;
- LEVEL 0 FOR 140.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 450.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "clk";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "rst";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "set";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "d";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "q";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo_modelsim.xrf b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo_modelsim.xrf
deleted file mode 100644
index ae4693b..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo_modelsim.xrf
+++ /dev/null
@@ -1,16 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vwf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/db/FlipFlopD_Demo.cbx.xml
-design_name = FlipFlopD
-instance = comp, \q~output\, q~output, FlipFlopD, 1
-instance = comp, \clk~input\, clk~input, FlipFlopD, 1
-instance = comp, \d~input\, d~input, FlipFlopD, 1
-instance = comp, \set~input\, set~input, FlipFlopD, 1
-instance = comp, \rst~input\, rst~input, FlipFlopD, 1
-instance = comp, \q~0\, q~0, FlipFlopD, 1
-instance = comp, \q~reg0\, q~reg0, FlipFlopD, 1
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/transcript
deleted file mode 100644
index 593649d..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/transcript
+++ /dev/null
@@ -1,49 +0,0 @@
-# do FlipFlopD_Demo.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 10:57:36 on Mar 15,2023
-# vcom -work work FlipFlopD_Demo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package dffeas_pack
-# -- Loading package altera_primitives_components
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity FlipFlopD
-# -- Compiling architecture structure of FlipFlopD
-# End time: 10:57:36 on Mar 15,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 10:57:36 on Mar 15,2023
-# vcom -work work FlipFlopD.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity FlipFlopD_vhd_vec_tst
-# -- Compiling architecture FlipFlopD_arch of FlipFlopD_vhd_vec_tst
-# End time: 10:57:36 on Mar 15,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.FlipFlopD_vhd_vec_tst
-# Start time: 10:57:36 on Mar 15,2023
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading work.flipflopd_vhd_vec_tst(flipflopd_arch)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading altera.dffeas_pack
-# Loading altera.altera_primitives_components
-# Loading cycloneive.cycloneive_atom_pack(body)
-# Loading cycloneive.cycloneive_components
-# Loading work.flipflopd(structure)
-# Loading ieee.std_logic_arith(body)
-# Loading cycloneive.cycloneive_io_obuf(arch)
-# Loading cycloneive.cycloneive_io_ibuf(arch)
-# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
-# Loading altera.dffeas(vital_dffeas)
-# after#33
-# End time: 10:57:36 on Mar 15,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/vwf_sim_transcript
deleted file mode 100644
index 3c16bf1..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/vwf_sim_transcript
+++ /dev/null
@@ -1,70 +0,0 @@
-Determining the location of the ModelSim executable...
-
-Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
-
-To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
-Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
-
-**** Generating the ModelSim Testbench ****
-
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD.vwf.vht"
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Mar 15 10:57:35 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD.vwf.vhtInfo (119006): Selected device EP4CE115F29C7 for design "FlipFlopD_Demo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Completed successfully.
-
-**** Generating the functional simulation netlist ****
-
-quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/" FlipFlopD_Demo -c FlipFlopD_Demo
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Mar 15 10:57:35 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/ FlipFlopD_Demo -c FlipFlopD_DemoInfo (119006): Selected device EP4CE115F29C7 for design "FlipFlopD_Demo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file FlipFlopD_Demo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 615 megabytes Info: Processing ended: Wed Mar 15 10:57:36 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00
-Completed successfully.
-
-**** Generating the ModelSim .do script ****
-
-/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.do generated.
-
-Completed successfully.
-
-**** Running the ModelSim simulation ****
-
-/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do FlipFlopD_Demo.do
-
-Reading pref.tcl
-# 2020.1
-# do FlipFlopD_Demo.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 10:57:36 on Mar 15,2023# vcom -work work FlipFlopD_Demo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164# -- Loading package VITAL_Timing# -- Loading package VITAL_Primitives
-# -- Loading package dffeas_pack# -- Loading package altera_primitives_components# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components# -- Compiling entity FlipFlopD# -- Compiling architecture structure of FlipFlopD
-# End time: 10:57:36 on Mar 15,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 10:57:36 on Mar 15,2023# vcom -work work FlipFlopD.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO# -- Loading package std_logic_1164
-# -- Compiling entity FlipFlopD_vhd_vec_tst# -- Compiling architecture FlipFlopD_arch of FlipFlopD_vhd_vec_tst
-# End time: 10:57:36 on Mar 15,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.FlipFlopD_vhd_vec_tst # Start time: 10:57:36 on Mar 15,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.flipflopd_vhd_vec_tst(flipflopd_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading altera.dffeas_pack# Loading altera.altera_primitives_components# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.flipflopd(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)# Loading altera.dffeas(vital_dffeas)
-# after#33
-# End time: 10:57:36 on Mar 15,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-Completed successfully.
-
-**** Converting ModelSim VCD to vector waveform ****
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vwf...
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo.msim.vcd...
-
-Processing channel transitions...
-
-Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD_Demo_20230315105737.sim.vwf
-
-Finished VCD to VWF conversion.
-
-Completed successfully.
-
-All completed.
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/work/_info
deleted file mode 100644
index 0978bc0..0000000
--- a/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/work/_info
+++ /dev/null
@@ -1,105 +0,0 @@
-m255
-K4
-z2
-!s11e vcom 2020.1 2020.02, Feb 28 2020
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-Z0 d/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim
-Eflipflopd
-Z1 w1678877856
-Z2 DPx10 cycloneive 20 cycloneive_atom_pack 0 22 WOh:M[al;oVzG5c`D0
-Z3 DPx10 cycloneive 21 cycloneive_components 0 22 zGMDhP>8e@2k@f0ekiXP8Q9dRClKfK1Zn7j1
-Z5 DPx6 altera 11 dffeas_pack 0 22 dc5N=DKXMMTVYdUQ@D3FA2
-Z6 DPx4 ieee 12 vital_timing 0 22 J>EBealN09f8GzldA[z2>3
-Z7 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
-Z8 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
-Z9 DPx6 altera 28 altera_primitives_components 0 22 ca:ehlQAg4;_gVV:^8MAg3
-!i122 2
-R0
-Z10 8FlipFlopD_Demo.vho
-Z11 FFlipFlopD_Demo.vho
-l0
-L37 1
-VkkcY3P9OPh3I83BRHl[2M1
-!s100 kEc3FdTQ5]2f8MI59l7Y90
-Z12 OV;C;2020.1;71
-32
-Z13 !s110 1678877856
-!i10b 1
-Z14 !s108 1678877856.000000
-Z15 !s90 -work|work|FlipFlopD_Demo.vho|
-Z16 !s107 FlipFlopD_Demo.vho|
-!i113 1
-Z17 o-work work
-Z18 tExplicit 1 CvgOpt 0
-Astructure
-R2
-R3
-R4
-R5
-R6
-R7
-R8
-R9
-DEx4 work 9 flipflopd 0 22 kkcY3P9OPh3I83BRHl[2M1
-!i122 2
-l70
-L47 115
-VIQol9GK[oSAg]]mPHj=kg2
-!s100 bDVb;33^QGS6e1ffBbA7:3
-R12
-32
-R13
-!i10b 1
-R14
-R15
-R16
-!i113 1
-R17
-R18
-Eflipflopd_vhd_vec_tst
-Z19 w1678877855
-R7
-R8
-!i122 3
-R0
-Z20 8FlipFlopD.vwf.vht
-Z21 FFlipFlopD.vwf.vht
-l0
-L32 1
-V_hf]K[JUEnmKOT8_MlE`31
-!s100 B0D]Y`jPC@nc2_
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.bpm b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.bpm
deleted file mode 100644
index b79a790..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.cdb
deleted file mode 100644
index c326152..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.hdb
deleted file mode 100644
index 5be2cf6..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.idb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.idb
deleted file mode 100644
index 93056c6..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.idb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.logdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.logdb
deleted file mode 100644
index 40b57b0..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.logdb
+++ /dev/null
@@ -1,60 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;18;18;0;0;18;18;0;0;0;0;0;0;8;0;0;0;10;8;0;10;0;0;8;0;18;18;18;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,18;0;0;18;18;0;0;18;18;18;18;18;18;10;18;18;18;8;10;18;8;18;18;10;18;0;0;0;18;18,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,LEDR[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.rdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.rdb
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.db_info b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.db_info
deleted file mode 100644
index 7094f3b..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Wed Mar 22 10:17:38 2023
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.eda.qmsg b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.eda.qmsg
deleted file mode 100644
index fbd9692..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679476809390 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679476809391 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 09:20:09 2023 " "Processing started: Wed Mar 22 09:20:09 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679476809391 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679476809391 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679476809391 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1679476809824 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "RegisterDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/ simulation " "Generated file RegisterDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1679476809899 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679476809929 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 09:20:09 2023 " "Processing ended: Wed Mar 22 09:20:09 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679476809929 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679476809929 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679476809929 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1679476809929 ""}
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.fit.qmsg b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.fit.qmsg
deleted file mode 100644
index 01b8ce2..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.fit.qmsg
+++ /dev/null
@@ -1,46 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1679476780815 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1679476780815 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "RegisterDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"RegisterDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1679476780820 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679476780960 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679476780960 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1679476781655 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1679476781665 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1679476781923 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/" { { 0 { 0 ""} 0 594 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679476781929 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/" { { 0 { 0 ""} 0 596 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679476781929 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/" { { 0 { 0 ""} 0 598 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679476781929 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/" { { 0 { 0 ""} 0 600 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679476781929 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/" { { 0 { 0 ""} 0 602 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679476781929 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1679476781929 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1679476781939 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RegisterDemo.sdc " "Synopsys Design Constraints File file not found: 'RegisterDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1679476783502 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1679476783503 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1679476783512 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1679476783512 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1679476783513 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1679476783864 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679476783864 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679476783865 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1679476783866 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1679476783866 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1679476783867 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1679476783867 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1679476783867 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1679476783876 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1679476783876 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1679476783876 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1679476783924 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679476783945 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1679476783953 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1679476787519 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679476787725 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1679476787806 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1679476788347 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679476788347 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1679476788799 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y37 X115_Y48 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48"} { { 12 { 0 ""} 104 37 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1679476794390 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1679476794390 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1679476794649 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1679476794649 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1679476794649 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679476794651 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1679476794847 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1679476794857 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1679476795309 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1679476795309 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1679476795724 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679476796365 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1679476796816 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1679476796921 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 507 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 507 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1151 " "Peak virtual memory: 1151 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679476797269 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 09:19:57 2023 " "Processing ended: Wed Mar 22 09:19:57 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679476797269 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679476797269 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679476797269 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1679476797269 ""}
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.hier_info b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.hier_info
deleted file mode 100644
index ce19507..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.hier_info
+++ /dev/null
@@ -1,56 +0,0 @@
-|RegisterDemo
-LEDR[0] <= Register8:inst.dataOut[0]
-LEDR[1] <= Register8:inst.dataOut[1]
-LEDR[2] <= Register8:inst.dataOut[2]
-LEDR[3] <= Register8:inst.dataOut[3]
-LEDR[4] <= Register8:inst.dataOut[4]
-LEDR[5] <= Register8:inst.dataOut[5]
-LEDR[6] <= Register8:inst.dataOut[6]
-LEDR[7] <= Register8:inst.dataOut[7]
-KEY[0] => Register8:inst.clk
-SW[0] => Register8:inst.dataIn[0]
-SW[1] => Register8:inst.dataIn[1]
-SW[2] => Register8:inst.dataIn[2]
-SW[3] => Register8:inst.dataIn[3]
-SW[4] => Register8:inst.dataIn[4]
-SW[5] => Register8:inst.dataIn[5]
-SW[6] => Register8:inst.dataIn[6]
-SW[7] => Register8:inst.dataIn[7]
-SW[8] => Register8:inst.wrEn
-
-
-|RegisterDemo|Register8:inst
-dataIn[0] => dataOut[0]~reg0.DATAIN
-dataIn[1] => dataOut[1]~reg0.DATAIN
-dataIn[2] => dataOut[2]~reg0.DATAIN
-dataIn[3] => dataOut[3]~reg0.DATAIN
-dataIn[4] => dataOut[4]~reg0.DATAIN
-dataIn[5] => dataOut[5]~reg0.DATAIN
-dataIn[6] => dataOut[6]~reg0.DATAIN
-dataIn[7] => dataOut[7]~reg0.DATAIN
-clk => dataOut[0]~reg0.CLK
-clk => dataOut[1]~reg0.CLK
-clk => dataOut[2]~reg0.CLK
-clk => dataOut[3]~reg0.CLK
-clk => dataOut[4]~reg0.CLK
-clk => dataOut[5]~reg0.CLK
-clk => dataOut[6]~reg0.CLK
-clk => dataOut[7]~reg0.CLK
-wrEn => dataOut[0]~reg0.ENA
-wrEn => dataOut[1]~reg0.ENA
-wrEn => dataOut[2]~reg0.ENA
-wrEn => dataOut[3]~reg0.ENA
-wrEn => dataOut[4]~reg0.ENA
-wrEn => dataOut[5]~reg0.ENA
-wrEn => dataOut[6]~reg0.ENA
-wrEn => dataOut[7]~reg0.ENA
-dataOut[0] <= dataOut[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[1] <= dataOut[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[2] <= dataOut[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[3] <= dataOut[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[4] <= dataOut[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[5] <= dataOut[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[6] <= dataOut[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[7] <= dataOut[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.hif b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.hif
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.html b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.html
deleted file mode 100644
index d666a97..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.html
+++ /dev/null
@@ -1,34 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| inst |
-10 |
-0 |
-0 |
-0 |
-8 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.rdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.rdb
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index 9a2dd17..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.txt b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.txt
deleted file mode 100644
index dfec3a3..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; inst ; 10 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.ammdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.ammdb
deleted file mode 100644
index 790b913..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.bpm b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.bpm
deleted file mode 100644
index 852de38..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.cdb
deleted file mode 100644
index 3210da8..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.hdb
deleted file mode 100644
index 6e29a54..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.kpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.kpt
deleted file mode 100644
index e7a7f67..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.logdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.qmsg b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.qmsg
deleted file mode 100644
index 8864fa9..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.qmsg
+++ /dev/null
@@ -1,13 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679476766975 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679476766976 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 09:19:26 2023 " "Processing started: Wed Mar 22 09:19:26 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679476766976 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679476766976 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RegisterDemo -c RegisterDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off RegisterDemo -c RegisterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679476766976 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679476767318 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679476767318 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Register8.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Register8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Register8-Behavioral " "Found design unit 1: Register8-Behavioral" { } { { "Register8.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679476777398 ""} { "Info" "ISGN_ENTITY_NAME" "1 Register8 " "Found entity 1: Register8" { } { { "Register8.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679476777398 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679476777398 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RegisterDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file RegisterDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 RegisterDemo " "Found entity 1: RegisterDemo" { } { { "RegisterDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679476777404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679476777404 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "RegisterDemo " "Elaborating entity \"RegisterDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679476777479 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Register8 Register8:inst " "Elaborating entity \"Register8\" for hierarchy \"Register8:inst\"" { } { { "RegisterDemo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.bdf" { { 184 408 600 296 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679476777485 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1679476778374 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1679476779182 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679476779182 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "26 " "Implemented 26 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1679476779225 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1679476779225 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1679476779225 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1679476779225 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "429 " "Peak virtual memory: 429 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679476779234 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 09:19:39 2023 " "Processing ended: Wed Mar 22 09:19:39 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679476779234 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679476779234 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679476779234 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679476779234 ""}
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.rdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.rdb
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.cdb
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.hdb
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.logdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.pre_map.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.pre_map.hdb
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index 79a73bf..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.root_partition.map.reg_db.cdb
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.routing.rdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv_sg.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv_sg.cdb
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv_sg_swap.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv_sg_swap.cdb
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sld_design_entry.sci b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sld_design_entry.sci
deleted file mode 100644
index 7d39add..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.smart_action.txt b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.smart_action.txt
deleted file mode 100644
index c8e8a13..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta.qmsg b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta.qmsg
deleted file mode 100644
index ec0a272..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta.qmsg
+++ /dev/null
@@ -1,44 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679476805482 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679476805483 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 09:20:05 2023 " "Processing started: Wed Mar 22 09:20:05 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679476805483 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1679476805483 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RegisterDemo -c RegisterDemo " "Command: quartus_sta RegisterDemo -c RegisterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1679476805483 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1679476805547 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1679476805713 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1679476805713 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679476805835 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679476805835 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RegisterDemo.sdc " "Synopsys Design Constraints File file not found: 'RegisterDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1679476806667 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1679476806667 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name KEY\[0\] KEY\[0\] " "create_clock -period 1.000 -name KEY\[0\] KEY\[0\]" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1679476806668 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679476806668 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1679476806669 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1679476806669 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1679476806670 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1679476806679 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476806680 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476806686 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476806687 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476806688 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476806689 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679476806689 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679476806689 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476806690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476806690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -13.280 KEY\[0\] " " -3.000 -13.280 KEY\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476806690 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679476806690 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679476806708 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1679476806747 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1679476807280 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1679476807315 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807316 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807317 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807319 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807320 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807321 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679476807321 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679476807321 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476807322 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476807322 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -13.280 KEY\[0\] " " -3.000 -13.280 KEY\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476807322 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679476807322 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679476807338 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1679476807441 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807442 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807444 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807445 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807446 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679476807446 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679476807446 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476807447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476807447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -11.696 KEY\[0\] " " -3.000 -11.696 KEY\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476807447 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679476807447 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679476808049 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679476808050 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "534 " "Peak virtual memory: 534 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679476808076 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 09:20:08 2023 " "Processing ended: Wed Mar 22 09:20:08 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679476808076 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679476808076 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679476808076 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1679476808076 ""}
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta.rdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta.rdb
deleted file mode 100644
index a866f1f..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta_cmp.7_slow_1200mv_85c.tdb
deleted file mode 100644
index 0d13df0..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tis_db_list.ddb
deleted file mode 100644
index 73e5ec9..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index f6380d2..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index 8de7c5e..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.slow_1200mv_0c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index 1f52d4f..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tmw_info b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tmw_info
deleted file mode 100644
index 1bd50f7..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tmw_info
+++ /dev/null
@@ -1,4 +0,0 @@
-start_full_compilation:s
-start_assembler:s-start_full_compilation
-start_timing_analyzer:s-start_full_compilation
-start_eda_netlist_writer:s-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.vpr.ammdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.vpr.ammdb
deleted file mode 100644
index 9e79825..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo_partition_pins.json b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo_partition_pins.json
deleted file mode 100644
index 0e70d74..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo_partition_pins.json
+++ /dev/null
@@ -1,81 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "LEDR[7]",
- "strict" : false
- },
- {
- "name" : "LEDR[6]",
- "strict" : false
- },
- {
- "name" : "LEDR[5]",
- "strict" : false
- },
- {
- "name" : "LEDR[4]",
- "strict" : false
- },
- {
- "name" : "LEDR[3]",
- "strict" : false
- },
- {
- "name" : "LEDR[2]",
- "strict" : false
- },
- {
- "name" : "LEDR[1]",
- "strict" : false
- },
- {
- "name" : "LEDR[0]",
- "strict" : false
- },
- {
- "name" : "SW[7]",
- "strict" : false
- },
- {
- "name" : "KEY[0]",
- "strict" : false
- },
- {
- "name" : "SW[8]",
- "strict" : false
- },
- {
- "name" : "SW[6]",
- "strict" : false
- },
- {
- "name" : "SW[5]",
- "strict" : false
- },
- {
- "name" : "SW[4]",
- "strict" : false
- },
- {
- "name" : "SW[3]",
- "strict" : false
- },
- {
- "name" : "SW[2]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/prev_cmp_RegisterDemo.qmsg b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/prev_cmp_RegisterDemo.qmsg
deleted file mode 100644
index 10e047c..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/prev_cmp_RegisterDemo.qmsg
+++ /dev/null
@@ -1,4 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679476600097 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus Prime " "Running Quartus Prime Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679476600098 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 09:16:39 2023 " "Processing started: Wed Mar 22 09:16:39 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679476600098 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1679476600098 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RegisterDemo -c RegisterDemo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd " "Command: quartus_map --read_settings_files=on --write_settings_files=off RegisterDemo -c RegisterDemo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1679476600098 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus Prime " "Quartus Prime Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "695 " "Peak virtual memory: 695 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679476601028 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 09:16:41 2023 " "Processing ended: Wed Mar 22 09:16:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679476601028 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679476601028 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679476601028 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1679476601028 ""}
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/README b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.db_info b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.db_info
deleted file mode 100644
index f364095..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Wed Mar 22 09:13:23 2023
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.ammdb
deleted file mode 100644
index b912250..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.cdb
deleted file mode 100644
index 450f748..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.hdb
deleted file mode 100644
index e43a9b2..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.rcfdb
deleted file mode 100644
index cb0c02b..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.cdb
deleted file mode 100644
index cc89887..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.dpi
deleted file mode 100644
index ef4ffbe..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.dpi and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.cdb
deleted file mode 100644
index cf03cfb..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.hdb
deleted file mode 100644
index e515c3b..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hdb
deleted file mode 100644
index 41ae750..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.kpt
deleted file mode 100644
index c5a15bd..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.rrp.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.rrp.hdb
deleted file mode 100644
index 107377a..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.asm.rpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.asm.rpt
deleted file mode 100644
index f18555d..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for RegisterDemo
-Wed Mar 22 09:20:04 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: RegisterDemo.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Wed Mar 22 09:20:04 2023 ;
-; Revision Name ; RegisterDemo ;
-; Top-level Entity Name ; RegisterDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+----------------------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+----------------------------------------------------------------------------------------------------------+
-; File Name ;
-+----------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sof ;
-+----------------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------+
-; Assembler Device Options: RegisterDemo.sof ;
-+----------------+---------------------------+
-; Option ; Setting ;
-+----------------+---------------------------+
-; JTAG usercode ; 0x00564A1F ;
-; Checksum ; 0x00564A1F ;
-+----------------+---------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 22 09:19:58 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 364 megabytes
- Info: Processing ended: Wed Mar 22 09:20:04 2023
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:05
-
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.done b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.done
deleted file mode 100644
index 515e6e3..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.done
+++ /dev/null
@@ -1 +0,0 @@
-Wed Mar 22 09:20:10 2023
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.eda.rpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.eda.rpt
deleted file mode 100644
index bd2eead..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.eda.rpt
+++ /dev/null
@@ -1,94 +0,0 @@
-EDA Netlist Writer report for RegisterDemo
-Wed Mar 22 09:20:09 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Wed Mar 22 09:20:09 2023 ;
-; Revision Name ; RegisterDemo ;
-; Top-level Entity Name ; RegisterDemo ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+-----------------------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+-----------------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.vho ;
-+-----------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 22 09:20:09 2023
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file RegisterDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 612 megabytes
- Info: Processing ended: Wed Mar 22 09:20:09 2023
- Info: Elapsed time: 00:00:00
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.rpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.rpt
deleted file mode 100644
index a13caba..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.rpt
+++ /dev/null
@@ -1,2606 +0,0 @@
-Fitter report for RegisterDemo
-Wed Mar 22 09:19:56 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Control Signals
- 22. Routing Usage Summary
- 23. LAB Logic Elements
- 24. LAB-wide Signals
- 25. LAB Signals Sourced
- 26. LAB Signals Sourced Out
- 27. LAB Distinct Inputs
- 28. I/O Rules Summary
- 29. I/O Rules Details
- 30. I/O Rules Matrix
- 31. Fitter Device Options
- 32. Operating Settings and Conditions
- 33. Fitter Messages
- 34. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Wed Mar 22 09:19:56 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; RegisterDemo ;
-; Top-level Entity Name ; RegisterDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 8 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 0 / 114,480 ( 0 % ) ;
-; Dedicated logic registers ; 8 / 114,480 ( < 1 % ) ;
-; Total registers ; 8 ;
-; Total pins ; 18 / 529 ( 3 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.1% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; CLOCK_50 ; PIN_Y2 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
-; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
-; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
-; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
-; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
-; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
-; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[1] ; PIN_M21 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[0] ; PIN_E21 ; QSF Assignment ;
-; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
-; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
-; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; SW[10] ; PIN_AC24 ; QSF Assignment ;
-; Location ; ; ; SW[11] ; PIN_AB24 ; QSF Assignment ;
-; Location ; ; ; SW[12] ; PIN_AB23 ; QSF Assignment ;
-; Location ; ; ; SW[13] ; PIN_AA24 ; QSF Assignment ;
-; Location ; ; ; SW[14] ; PIN_AA23 ; QSF Assignment ;
-; Location ; ; ; SW[15] ; PIN_AA22 ; QSF Assignment ;
-; Location ; ; ; SW[16] ; PIN_Y24 ; QSF Assignment ;
-; Location ; ; ; SW[17] ; PIN_Y23 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AB25 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 55 ) ; 0.00 % ( 0 / 55 ) ; 0.00 % ( 0 / 55 ) ;
-; -- Achieved ; 0.00 % ( 0 / 55 ) ; 0.00 % ( 0 / 55 ) ; 0.00 % ( 0 / 55 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 45 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+-----------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-----------------------+
-; Total logic elements ; 8 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 0 ;
-; -- Register only ; 8 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 0 ;
-; -- <=2 input functions ; 0 ;
-; -- Register only ; 8 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 0 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers* ; 8 / 117,053 ( < 1 % ) ;
-; -- Dedicated logic registers ; 8 / 114,480 ( < 1 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 1 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 18 / 529 ( 3 % ) ;
-; -- Clock pins ; 0 / 7 ( 0 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ;
-; Peak interconnect usage (total/H/V) ; 0.5% / 0.4% / 0.8% ;
-; Maximum fan-out ; 8 ;
-; Highest non-global fan-out ; 8 ;
-; Total fan-out ; 57 ;
-; Average fan-out ; 1.02 ;
-+---------------------------------------------+-----------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 8 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 0 ; 0 ;
-; -- Register only ; 8 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 0 ; 0 ;
-; -- 3 input functions ; 0 ; 0 ;
-; -- <=2 input functions ; 0 ; 0 ;
-; -- Register only ; 8 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 0 ; 0 ;
-; -- arithmetic mode ; 0 ; 0 ;
-; ; ; ;
-; Total registers ; 8 ; 0 ;
-; -- Dedicated logic registers ; 8 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 1 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 18 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 52 ; 5 ;
-; -- Registered Connections ; 8 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 10 ; 0 ;
-; -- Output Ports ; 8 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; KEY[0] ; M23 ; 6 ; 115 ; 40 ; 7 ; 8 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[3] ; AD27 ; 5 ; 115 ; 13 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[4] ; AB27 ; 5 ; 115 ; 18 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[5] ; AC26 ; 5 ; 115 ; 11 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[6] ; AD26 ; 5 ; 115 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[7] ; AB26 ; 5 ; 115 ; 15 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[8] ; AC25 ; 5 ; 115 ; 4 ; 21 ; 8 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[2] ; E19 ; 7 ; 94 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[3] ; F21 ; 7 ; 107 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[4] ; F18 ; 7 ; 87 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[5] ; E18 ; 7 ; 87 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[6] ; J19 ; 7 ; 72 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[7] ; H19 ; 7 ; 72 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+-----------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+-----------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+-----------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 0 / 63 ( 0 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 9 / 65 ( 14 % ) ; 2.5V ; -- ;
-; 6 ; 2 / 58 ( 3 % ) ; 2.5V ; -- ;
-; 7 ; 8 / 72 ( 11 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+-----------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA23 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA24 ; 279 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB24 ; 274 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB25 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB26 ; 291 ; 5 ; SW[7] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB27 ; 296 ; 5 ; SW[4] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC25 ; 272 ; 5 ; SW[8] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC26 ; 282 ; 5 ; SW[5] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; SW[6] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD27 ; 286 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 427 ; 7 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E19 ; 421 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; LEDR[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y24 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; LEDR[7] ; Incomplete set of assignments ;
-; LEDR[6] ; Incomplete set of assignments ;
-; LEDR[5] ; Incomplete set of assignments ;
-; LEDR[4] ; Incomplete set of assignments ;
-; LEDR[3] ; Incomplete set of assignments ;
-; LEDR[2] ; Incomplete set of assignments ;
-; LEDR[1] ; Incomplete set of assignments ;
-; LEDR[0] ; Incomplete set of assignments ;
-; SW[7] ; Incomplete set of assignments ;
-; KEY[0] ; Incomplete set of assignments ;
-; SW[8] ; Incomplete set of assignments ;
-; SW[6] ; Incomplete set of assignments ;
-; SW[5] ; Incomplete set of assignments ;
-; SW[4] ; Incomplete set of assignments ;
-; SW[3] ; Incomplete set of assignments ;
-; SW[2] ; Incomplete set of assignments ;
-; SW[1] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------+--------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------+--------------+--------------+
-; |RegisterDemo ; 8 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; 0 (0) ; 8 (0) ; 0 (0) ; |RegisterDemo ; RegisterDemo ; work ;
-; |Register8:inst| ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 8 (8) ; 0 (0) ; |RegisterDemo|Register8:inst ; Register8 ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------+--------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-----------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; KEY[0] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
-; SW[8] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[5] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[4] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+-----------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+-----------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+-----------------------------------------+-------------------+---------+
-; SW[7] ; ; ;
-; - Register8:inst|dataOut[7]~feeder ; 0 ; 6 ;
-; KEY[0] ; ; ;
-; - Register8:inst|dataOut[0] ; 0 ; 0 ;
-; - Register8:inst|dataOut[1] ; 0 ; 0 ;
-; - Register8:inst|dataOut[2] ; 0 ; 0 ;
-; - Register8:inst|dataOut[3] ; 0 ; 0 ;
-; - Register8:inst|dataOut[4] ; 0 ; 0 ;
-; - Register8:inst|dataOut[5] ; 0 ; 0 ;
-; - Register8:inst|dataOut[6] ; 0 ; 0 ;
-; - Register8:inst|dataOut[7] ; 0 ; 0 ;
-; SW[8] ; ; ;
-; - Register8:inst|dataOut[0] ; 1 ; 6 ;
-; - Register8:inst|dataOut[1] ; 1 ; 6 ;
-; - Register8:inst|dataOut[2] ; 1 ; 6 ;
-; - Register8:inst|dataOut[3] ; 1 ; 6 ;
-; - Register8:inst|dataOut[4] ; 1 ; 6 ;
-; - Register8:inst|dataOut[5] ; 1 ; 6 ;
-; - Register8:inst|dataOut[6] ; 1 ; 6 ;
-; - Register8:inst|dataOut[7] ; 1 ; 6 ;
-; SW[6] ; ; ;
-; - Register8:inst|dataOut[6] ; 0 ; 6 ;
-; SW[5] ; ; ;
-; - Register8:inst|dataOut[5]~feeder ; 1 ; 6 ;
-; SW[4] ; ; ;
-; - Register8:inst|dataOut[4] ; 1 ; 6 ;
-; SW[3] ; ; ;
-; - Register8:inst|dataOut[3] ; 1 ; 6 ;
-; SW[2] ; ; ;
-; - Register8:inst|dataOut[2] ; 1 ; 6 ;
-; SW[1] ; ; ;
-; - Register8:inst|dataOut[1] ; 0 ; 6 ;
-; SW[0] ; ; ;
-; - Register8:inst|dataOut[0] ; 0 ; 6 ;
-+-----------------------------------------+-------------------+---------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
-; KEY[0] ; PIN_M23 ; 8 ; Clock ; no ; -- ; -- ; -- ;
-; SW[8] ; PIN_AC25 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-+--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
-
-
-+------------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+------------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+------------------------+
-; Block interconnects ; 18 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 25 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 45 / 209,544 ( < 1 % ) ;
-; Direct links ; 0 / 342,891 ( 0 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 0 / 119,088 ( 0 % ) ;
-; R24 interconnects ; 16 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 29 / 289,782 ( < 1 % ) ;
-+-----------------------+------------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 1) ;
-+--------------------------------------------+-----------------------------+
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-+--------------------------------------------+-----------------------------+
-
-
-+------------------------------------------------------------------+
-; LAB-wide Signals ;
-+------------------------------------+-----------------------------+
-; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 1) ;
-+------------------------------------+-----------------------------+
-; 1 Clock ; 1 ;
-; 1 Clock enable ; 1 ;
-+------------------------------------+-----------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+----------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 10.00) ; Number of LABs (Total = 1) ;
-+----------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 1 ;
-+----------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 1) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+----------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 10.00) ; Number of LABs (Total = 1) ;
-+----------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 1 ;
-+----------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 18 ; 18 ; 0 ; 0 ; 18 ; 18 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 10 ; 8 ; 0 ; 10 ; 0 ; 0 ; 8 ; 0 ; 18 ; 18 ; 18 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 18 ; 0 ; 0 ; 18 ; 18 ; 0 ; 0 ; 18 ; 18 ; 18 ; 18 ; 18 ; 18 ; 10 ; 18 ; 18 ; 18 ; 8 ; 10 ; 18 ; 8 ; 18 ; 18 ; 10 ; 18 ; 0 ; 0 ; 0 ; 18 ; 18 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; LEDR[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "RegisterDemo"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'RegisterDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 507 warnings
- Info: Peak virtual memory: 1151 megabytes
- Info: Processing ended: Wed Mar 22 09:19:57 2023
- Info: Elapsed time: 00:00:17
- Info: Total CPU time (on all processors): 00:00:24
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.summary b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.summary
deleted file mode 100644
index 90909a4..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Wed Mar 22 09:19:56 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : RegisterDemo
-Top-level Entity Name : RegisterDemo
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 8 / 114,480 ( < 1 % )
- Total combinational functions : 0 / 114,480 ( 0 % )
- Dedicated logic registers : 8 / 114,480 ( < 1 % )
-Total registers : 8
-Total pins : 18 / 529 ( 3 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.flow.rpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.flow.rpt
deleted file mode 100644
index 40fc3f4..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.flow.rpt
+++ /dev/null
@@ -1,136 +0,0 @@
-Flow report for RegisterDemo
-Wed Mar 22 09:20:09 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Wed Mar 22 09:20:09 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; RegisterDemo ;
-; Top-level Entity Name ; RegisterDemo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 8 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 0 / 114,480 ( 0 % ) ;
-; Dedicated logic registers ; 8 / 114,480 ( < 1 % ) ;
-; Total registers ; 8 ;
-; Total pins ; 18 / 529 ( 3 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/22/2023 09:19:27 ;
-; Main task ; Compilation ;
-; Revision Name ; RegisterDemo ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 198516037997543.167947676707173 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 429 MB ; 00:00:32 ;
-; Fitter ; 00:00:16 ; 1.0 ; 1151 MB ; 00:00:24 ;
-; Assembler ; 00:00:06 ; 1.0 ; 364 MB ; 00:00:05 ;
-; Timing Analyzer ; 00:00:03 ; 1.0 ; 534 MB ; 00:00:03 ;
-; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 612 MB ; 00:00:01 ;
-; Total ; 00:00:37 ; -- ; -- ; 00:01:05 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off RegisterDemo -c RegisterDemo
-quartus_fit --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo
-quartus_asm --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo
-quartus_sta RegisterDemo -c RegisterDemo
-quartus_eda --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo
-
-
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.jdi b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.jdi
deleted file mode 100644
index bca186f..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.map.rpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.map.rpt
deleted file mode 100644
index b78f94c..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.map.rpt
+++ /dev/null
@@ -1,286 +0,0 @@
-Analysis & Synthesis report for RegisterDemo
-Wed Mar 22 09:19:39 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Post-Synthesis Netlist Statistics for Top Partition
- 10. Elapsed Time Per Partition
- 11. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Wed Mar 22 09:19:39 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; RegisterDemo ;
-; Top-level Entity Name ; RegisterDemo ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 8 ;
-; Total combinational functions ; 0 ;
-; Dedicated logic registers ; 8 ;
-; Total registers ; 8 ;
-; Total pins ; 18 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; RegisterDemo ; RegisterDemo ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------+---------+
-; Register8.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd ; ;
-; RegisterDemo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.bdf ; ;
-+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------+---------+
-
-
-+------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+--------------+
-; Resource ; Usage ;
-+---------------------------------------------+--------------+
-; Estimated Total logic elements ; 8 ;
-; ; ;
-; Total combinational functions ; 0 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 0 ;
-; -- 3 input functions ; 0 ;
-; -- <=2 input functions ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 0 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers ; 8 ;
-; -- Dedicated logic registers ; 8 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 18 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; KEY[0]~input ;
-; Maximum fan-out ; 8 ;
-; Total fan-out ; 50 ;
-; Average fan-out ; 1.14 ;
-+---------------------------------------------+--------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+--------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+--------------+--------------+
-; |RegisterDemo ; 0 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; |RegisterDemo ; RegisterDemo ; work ;
-; |Register8:inst| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |RegisterDemo|Register8:inst ; Register8 ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+--------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 8 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 8 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-------------------+---------------------------------+
-; Type ; Count ;
-+-------------------+---------------------------------+
-; boundary_port ; 18 ;
-; cycloneiii_ff ; 8 ;
-; ENA ; 8 ;
-; ; ;
-; Max LUT depth ; 0.00 ;
-; Average LUT depth ; 0.00 ;
-+-------------------+---------------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:01 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 22 09:19:26 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RegisterDemo -c RegisterDemo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 2 design units, including 1 entities, in source file Register8.vhd
- Info (12022): Found design unit 1: Register8-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd Line: 14
- Info (12023): Found entity 1: Register8 File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd Line: 4
-Info (12021): Found 1 design units, including 1 entities, in source file RegisterDemo.bdf
- Info (12023): Found entity 1: RegisterDemo
-Info (12127): Elaborating entity "RegisterDemo" for the top level hierarchy
-Info (12128): Elaborating entity "Register8" for hierarchy "Register8:inst"
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 26 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 10 input pins
- Info (21059): Implemented 8 output pins
- Info (21061): Implemented 8 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 429 megabytes
- Info: Processing ended: Wed Mar 22 09:19:39 2023
- Info: Elapsed time: 00:00:13
- Info: Total CPU time (on all processors): 00:00:32
-
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.map.summary b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.map.summary
deleted file mode 100644
index 4744268..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Wed Mar 22 09:19:39 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : RegisterDemo
-Top-level Entity Name : RegisterDemo
-Family : Cyclone IV E
-Total logic elements : 8
- Total combinational functions : 0
- Dedicated logic registers : 8
-Total registers : 8
-Total pins : 18
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.pin b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.pin
deleted file mode 100644
index bb54ae1..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "RegisterDemo" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5 :
-SW[7] : AB26 : input : 2.5 V : : 5 : Y
-SW[4] : AB27 : input : 2.5 V : : 5 : Y
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5 :
-SW[8] : AC25 : input : 2.5 V : : 5 : Y
-SW[5] : AC26 : input : 2.5 V : : 5 : Y
-SW[2] : AC27 : input : 2.5 V : : 5 : Y
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-SW[6] : AD26 : input : 2.5 V : : 5 : Y
-SW[3] : AD27 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
-LEDR[5] : E18 : output : 2.5 V : : 7 : Y
-LEDR[2] : E19 : output : 2.5 V : : 7 : Y
-VCCIO7 : E20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
-VCCIO7 : E23 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-LEDR[4] : F18 : output : 2.5 V : : 7 : Y
-LEDR[1] : F19 : output : 2.5 V : : 7 : Y
-GND : F20 : gnd : : : :
-LEDR[3] : F21 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
-LEDR[0] : G19 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
-VCCIO7 : H18 : power : : 2.5V : 7 :
-LEDR[7] : H19 : output : 2.5 V : : 7 : Y
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
-GND : J18 : gnd : : : :
-LEDR[6] : J19 : output : 2.5 V : : 7 : Y
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6 :
-MSEL2 : M22 : : : : 6 :
-KEY[0] : M23 : input : 2.5 V : : 6 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-GND+ : Y2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sld b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sta.rpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sta.rpt
deleted file mode 100644
index 4634ce2..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sta.rpt
+++ /dev/null
@@ -1,527 +0,0 @@
-Timing Analyzer report for RegisterDemo
-Wed Mar 22 09:20:08 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Clock Status Summary
- 37. Unconstrained Input Ports
- 38. Unconstrained Output Ports
- 39. Unconstrained Input Ports
- 40. Unconstrained Output Ports
- 41. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; RegisterDemo ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.2% ;
-+----------------------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------+
-; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------+
-; KEY[0] ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { KEY[0] } ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------+
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
-+--------+--------+---------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+--------+--------+---------------------------------+
-; KEY[0] ; -3.000 ; -13.280 ;
-+--------+--------+---------------------------------+
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------+
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-+--------+--------+--------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+--------+--------+--------------------------------+
-; KEY[0] ; -3.000 ; -13.280 ;
-+--------+--------+--------------------------------+
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------+
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-+--------+--------+--------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+--------+--------+--------------------------------+
-; KEY[0] ; -3.000 ; -11.696 ;
-+--------+--------+--------------------------------+
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; -3.000 ;
-; KEY[0] ; N/A ; N/A ; N/A ; N/A ; -3.000 ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; -13.28 ;
-; KEY[0] ; N/A ; N/A ; N/A ; N/A ; -13.280 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 9 ; 9 ;
-; Unconstrained Input Port Paths ; 16 ; 16 ;
-; Unconstrained Output Ports ; 8 ; 8 ;
-; Unconstrained Output Port Paths ; 8 ; 8 ;
-+---------------------------------+-------+------+
-
-
-+--------------------------------------+
-; Clock Status Summary ;
-+--------+--------+------+-------------+
-; Target ; Clock ; Type ; Status ;
-+--------+--------+------+-------------+
-; KEY[0] ; KEY[0] ; Base ; Constrained ;
-+--------+--------+------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 22 09:20:05 2023
-Info: Command: quartus_sta RegisterDemo -c RegisterDemo
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'RegisterDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
- Info (332105): create_clock -period 1.000 -name KEY[0] KEY[0]
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -13.280 KEY[0]
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -13.280 KEY[0]
-Info: Analyzing Fast 1200mV 0C Model
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -11.696 KEY[0]
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 534 megabytes
- Info: Processing ended: Wed Mar 22 09:20:08 2023
- Info: Elapsed time: 00:00:03
- Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sta.summary b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sta.summary
deleted file mode 100644
index 364aeea..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sta.summary
+++ /dev/null
@@ -1,17 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-Type : Slow 1200mV 85C Model Minimum Pulse Width 'KEY[0]'
-Slack : -3.000
-TNS : -13.280
-
-Type : Slow 1200mV 0C Model Minimum Pulse Width 'KEY[0]'
-Slack : -3.000
-TNS : -13.280
-
-Type : Fast 1200mV 0C Model Minimum Pulse Width 'KEY[0]'
-Slack : -3.000
-TNS : -11.696
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.sft b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.vho b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.vho
deleted file mode 100644
index d29e86e..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.vho
+++ /dev/null
@@ -1,542 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/22/2023 09:20:09"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY ALTERA;
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY RegisterDemo IS
- PORT (
- LEDR : OUT std_logic_vector(7 DOWNTO 0);
- KEY : IN std_logic_vector(0 DOWNTO 0);
- SW : IN std_logic_vector(8 DOWNTO 0)
- );
-END RegisterDemo;
-
--- Design Ports Information
--- LEDR[7] => Location: PIN_H19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[6] => Location: PIN_J19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[5] => Location: PIN_E18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[4] => Location: PIN_F18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default
--- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF RegisterDemo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDR : std_logic_vector(7 DOWNTO 0);
-SIGNAL ww_KEY : std_logic_vector(0 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(8 DOWNTO 0);
-SIGNAL \LEDR[7]~output_o\ : std_logic;
-SIGNAL \LEDR[6]~output_o\ : std_logic;
-SIGNAL \LEDR[5]~output_o\ : std_logic;
-SIGNAL \LEDR[4]~output_o\ : std_logic;
-SIGNAL \LEDR[3]~output_o\ : std_logic;
-SIGNAL \LEDR[2]~output_o\ : std_logic;
-SIGNAL \LEDR[1]~output_o\ : std_logic;
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \KEY[0]~input_o\ : std_logic;
-SIGNAL \SW[7]~input_o\ : std_logic;
-SIGNAL \inst|dataOut[7]~feeder_combout\ : std_logic;
-SIGNAL \SW[8]~input_o\ : std_logic;
-SIGNAL \SW[6]~input_o\ : std_logic;
-SIGNAL \SW[5]~input_o\ : std_logic;
-SIGNAL \inst|dataOut[5]~feeder_combout\ : std_logic;
-SIGNAL \SW[4]~input_o\ : std_logic;
-SIGNAL \SW[3]~input_o\ : std_logic;
-SIGNAL \SW[2]~input_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \inst|dataOut\ : std_logic_vector(7 DOWNTO 0);
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-LEDR <= ww_LEDR;
-ww_KEY <= KEY;
-ww_SW <= SW;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X72_Y73_N2
-\LEDR[7]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|dataOut\(7),
- devoe => ww_devoe,
- o => \LEDR[7]~output_o\);
-
--- Location: IOOBUF_X72_Y73_N9
-\LEDR[6]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|dataOut\(6),
- devoe => ww_devoe,
- o => \LEDR[6]~output_o\);
-
--- Location: IOOBUF_X87_Y73_N9
-\LEDR[5]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|dataOut\(5),
- devoe => ww_devoe,
- o => \LEDR[5]~output_o\);
-
--- Location: IOOBUF_X87_Y73_N16
-\LEDR[4]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|dataOut\(4),
- devoe => ww_devoe,
- o => \LEDR[4]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N16
-\LEDR[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|dataOut\(3),
- devoe => ww_devoe,
- o => \LEDR[3]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N9
-\LEDR[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|dataOut\(2),
- devoe => ww_devoe,
- o => \LEDR[2]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N2
-\LEDR[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|dataOut\(1),
- devoe => ww_devoe,
- o => \LEDR[1]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N16
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|dataOut\(0),
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
--- Location: IOIBUF_X115_Y40_N8
-\KEY[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY(0),
- o => \KEY[0]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N1
-\SW[7]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(7),
- o => \SW[7]~input_o\);
-
--- Location: LCCOMB_X114_Y40_N24
-\inst|dataOut[7]~feeder\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|dataOut[7]~feeder_combout\ = \SW[7]~input_o\
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datad => \SW[7]~input_o\,
- combout => \inst|dataOut[7]~feeder_combout\);
-
--- Location: IOIBUF_X115_Y4_N22
-\SW[8]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(8),
- o => \SW[8]~input_o\);
-
--- Location: FF_X114_Y40_N25
-\inst|dataOut[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \KEY[0]~input_o\,
- d => \inst|dataOut[7]~feeder_combout\,
- ena => \SW[8]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|dataOut\(7));
-
--- Location: IOIBUF_X115_Y10_N1
-\SW[6]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(6),
- o => \SW[6]~input_o\);
-
--- Location: FF_X114_Y40_N27
-\inst|dataOut[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \KEY[0]~input_o\,
- asdata => \SW[6]~input_o\,
- sload => VCC,
- ena => \SW[8]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|dataOut\(6));
-
--- Location: IOIBUF_X115_Y11_N8
-\SW[5]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(5),
- o => \SW[5]~input_o\);
-
--- Location: LCCOMB_X114_Y40_N4
-\inst|dataOut[5]~feeder\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|dataOut[5]~feeder_combout\ = \SW[5]~input_o\
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111111100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datad => \SW[5]~input_o\,
- combout => \inst|dataOut[5]~feeder_combout\);
-
--- Location: FF_X114_Y40_N5
-\inst|dataOut[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \KEY[0]~input_o\,
- d => \inst|dataOut[5]~feeder_combout\,
- ena => \SW[8]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|dataOut\(5));
-
--- Location: IOIBUF_X115_Y18_N8
-\SW[4]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(4),
- o => \SW[4]~input_o\);
-
--- Location: FF_X114_Y40_N23
-\inst|dataOut[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \KEY[0]~input_o\,
- asdata => \SW[4]~input_o\,
- sload => VCC,
- ena => \SW[8]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|dataOut\(4));
-
--- Location: IOIBUF_X115_Y13_N8
-\SW[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(3),
- o => \SW[3]~input_o\);
-
--- Location: FF_X114_Y40_N1
-\inst|dataOut[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \KEY[0]~input_o\,
- asdata => \SW[3]~input_o\,
- sload => VCC,
- ena => \SW[8]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|dataOut\(3));
-
--- Location: IOIBUF_X115_Y15_N8
-\SW[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(2),
- o => \SW[2]~input_o\);
-
--- Location: FF_X114_Y40_N19
-\inst|dataOut[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \KEY[0]~input_o\,
- asdata => \SW[2]~input_o\,
- sload => VCC,
- ena => \SW[8]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|dataOut\(2));
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: FF_X114_Y40_N13
-\inst|dataOut[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \KEY[0]~input_o\,
- asdata => \SW[1]~input_o\,
- sload => VCC,
- ena => \SW[8]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|dataOut\(1));
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: FF_X114_Y40_N7
-\inst|dataOut[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \KEY[0]~input_o\,
- asdata => \SW[0]~input_o\,
- sload => VCC,
- ena => \SW[8]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|dataOut\(0));
-
-ww_LEDR(7) <= \LEDR[7]~output_o\;
-
-ww_LEDR(6) <= \LEDR[6]~output_o\;
-
-ww_LEDR(5) <= \LEDR[5]~output_o\;
-
-ww_LEDR(4) <= \LEDR[4]~output_o\;
-
-ww_LEDR(3) <= \LEDR[3]~output_o\;
-
-ww_LEDR(2) <= \LEDR[2]~output_o\;
-
-ww_LEDR(1) <= \LEDR[1]~output_o\;
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo_modelsim.xrf
deleted file mode 100644
index c7027af..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo_modelsim.xrf
+++ /dev/null
@@ -1,39 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.bdf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cbx.xml
-design_name = hard_block
-design_name = RegisterDemo
-instance = comp, \LEDR[7]~output\, LEDR[7]~output, RegisterDemo, 1
-instance = comp, \LEDR[6]~output\, LEDR[6]~output, RegisterDemo, 1
-instance = comp, \LEDR[5]~output\, LEDR[5]~output, RegisterDemo, 1
-instance = comp, \LEDR[4]~output\, LEDR[4]~output, RegisterDemo, 1
-instance = comp, \LEDR[3]~output\, LEDR[3]~output, RegisterDemo, 1
-instance = comp, \LEDR[2]~output\, LEDR[2]~output, RegisterDemo, 1
-instance = comp, \LEDR[1]~output\, LEDR[1]~output, RegisterDemo, 1
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, RegisterDemo, 1
-instance = comp, \KEY[0]~input\, KEY[0]~input, RegisterDemo, 1
-instance = comp, \SW[7]~input\, SW[7]~input, RegisterDemo, 1
-instance = comp, \inst|dataOut[7]~feeder\, inst|dataOut[7]~feeder, RegisterDemo, 1
-instance = comp, \SW[8]~input\, SW[8]~input, RegisterDemo, 1
-instance = comp, \inst|dataOut[7]\, inst|dataOut[7], RegisterDemo, 1
-instance = comp, \SW[6]~input\, SW[6]~input, RegisterDemo, 1
-instance = comp, \inst|dataOut[6]\, inst|dataOut[6], RegisterDemo, 1
-instance = comp, \SW[5]~input\, SW[5]~input, RegisterDemo, 1
-instance = comp, \inst|dataOut[5]~feeder\, inst|dataOut[5]~feeder, RegisterDemo, 1
-instance = comp, \inst|dataOut[5]\, inst|dataOut[5], RegisterDemo, 1
-instance = comp, \SW[4]~input\, SW[4]~input, RegisterDemo, 1
-instance = comp, \inst|dataOut[4]\, inst|dataOut[4], RegisterDemo, 1
-instance = comp, \SW[3]~input\, SW[3]~input, RegisterDemo, 1
-instance = comp, \inst|dataOut[3]\, inst|dataOut[3], RegisterDemo, 1
-instance = comp, \SW[2]~input\, SW[2]~input, RegisterDemo, 1
-instance = comp, \inst|dataOut[2]\, inst|dataOut[2], RegisterDemo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, RegisterDemo, 1
-instance = comp, \inst|dataOut[1]\, inst|dataOut[1], RegisterDemo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, RegisterDemo, 1
-instance = comp, \inst|dataOut[0]\, inst|dataOut[0], RegisterDemo, 1
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vht b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vht
deleted file mode 100644
index d6d8948..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vht
+++ /dev/null
@@ -1,339 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- *****************************************************************************
--- This file contains a Vhdl test bench with test vectors .The test vectors
--- are exported from a vector file in the Quartus Waveform Editor and apply to
--- the top level entity of the current Quartus project .The user can use this
--- testbench to simulate his design using a third-party simulation tool .
--- *****************************************************************************
--- Generated on "03/22/2023 09:15:28"
-
--- Vhdl Test Bench(with test vectors) for design : Register8
---
--- Simulation tool : 3rd Party
---
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY Register8_vhd_vec_tst IS
-END Register8_vhd_vec_tst;
-ARCHITECTURE Register8_arch OF Register8_vhd_vec_tst IS
--- constants
--- signals
-SIGNAL clk : STD_LOGIC;
-SIGNAL dataIn : STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL dataOut : STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL wrEn : STD_LOGIC;
-COMPONENT Register8
- PORT (
- clk : IN STD_LOGIC;
- dataIn : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- dataOut : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
- wrEn : IN STD_LOGIC
- );
-END COMPONENT;
-BEGIN
- i1 : Register8
- PORT MAP (
--- list connections between master ports and signals
- clk => clk,
- dataIn => dataIn,
- dataOut => dataOut,
- wrEn => wrEn
- );
-
--- wrEn
-t_prcs_wrEn: PROCESS
-BEGIN
- wrEn <= '0';
- WAIT FOR 400000 ps;
- wrEn <= '1';
- WAIT FOR 400000 ps;
- wrEn <= '0';
-WAIT;
-END PROCESS t_prcs_wrEn;
-
--- clk
-t_prcs_clk: PROCESS
-BEGIN
-LOOP
- clk <= '0';
- WAIT FOR 20000 ps;
- clk <= '1';
- WAIT FOR 20000 ps;
- IF (NOW >= 1000000 ps) THEN WAIT; END IF;
-END LOOP;
-END PROCESS t_prcs_clk;
--- dataIn[7]
-t_prcs_dataIn_7: PROCESS
-BEGIN
- dataIn(7) <= '1';
- WAIT FOR 200000 ps;
- dataIn(7) <= '0';
- WAIT FOR 40000 ps;
- dataIn(7) <= '1';
- WAIT FOR 120000 ps;
- dataIn(7) <= '0';
- WAIT FOR 40000 ps;
- dataIn(7) <= '1';
- WAIT FOR 40000 ps;
- dataIn(7) <= '0';
- WAIT FOR 120000 ps;
- dataIn(7) <= '1';
- WAIT FOR 40000 ps;
- dataIn(7) <= '0';
- WAIT FOR 40000 ps;
- dataIn(7) <= '1';
- WAIT FOR 40000 ps;
- dataIn(7) <= '0';
- WAIT FOR 40000 ps;
- dataIn(7) <= '1';
- WAIT FOR 40000 ps;
- dataIn(7) <= '0';
- WAIT FOR 40000 ps;
- dataIn(7) <= '1';
- WAIT FOR 40000 ps;
- dataIn(7) <= '0';
- WAIT FOR 120000 ps;
- dataIn(7) <= '1';
-WAIT;
-END PROCESS t_prcs_dataIn_7;
--- dataIn[6]
-t_prcs_dataIn_6: PROCESS
-BEGIN
- dataIn(6) <= '0';
- WAIT FOR 80000 ps;
- dataIn(6) <= '1';
- WAIT FOR 80000 ps;
- dataIn(6) <= '0';
- WAIT FOR 40000 ps;
- dataIn(6) <= '1';
- WAIT FOR 40000 ps;
- dataIn(6) <= '0';
- WAIT FOR 40000 ps;
- dataIn(6) <= '1';
- WAIT FOR 40000 ps;
- dataIn(6) <= '0';
- WAIT FOR 120000 ps;
- dataIn(6) <= '1';
- WAIT FOR 120000 ps;
- dataIn(6) <= '0';
- WAIT FOR 40000 ps;
- dataIn(6) <= '1';
- WAIT FOR 80000 ps;
- dataIn(6) <= '0';
- WAIT FOR 120000 ps;
- dataIn(6) <= '1';
- WAIT FOR 40000 ps;
- dataIn(6) <= '0';
- WAIT FOR 120000 ps;
- dataIn(6) <= '1';
-WAIT;
-END PROCESS t_prcs_dataIn_6;
--- dataIn[5]
-t_prcs_dataIn_5: PROCESS
-BEGIN
- dataIn(5) <= '0';
- WAIT FOR 80000 ps;
- dataIn(5) <= '1';
- WAIT FOR 40000 ps;
- dataIn(5) <= '0';
- WAIT FOR 120000 ps;
- dataIn(5) <= '1';
- WAIT FOR 40000 ps;
- dataIn(5) <= '0';
- WAIT FOR 80000 ps;
- dataIn(5) <= '1';
- WAIT FOR 40000 ps;
- dataIn(5) <= '0';
- WAIT FOR 80000 ps;
- dataIn(5) <= '1';
- WAIT FOR 80000 ps;
- dataIn(5) <= '0';
- WAIT FOR 120000 ps;
- dataIn(5) <= '1';
- WAIT FOR 40000 ps;
- dataIn(5) <= '0';
- WAIT FOR 40000 ps;
- dataIn(5) <= '1';
- WAIT FOR 80000 ps;
- dataIn(5) <= '0';
- WAIT FOR 40000 ps;
- dataIn(5) <= '1';
- WAIT FOR 40000 ps;
- dataIn(5) <= '0';
- WAIT FOR 40000 ps;
- dataIn(5) <= '1';
-WAIT;
-END PROCESS t_prcs_dataIn_5;
--- dataIn[4]
-t_prcs_dataIn_4: PROCESS
-BEGIN
- dataIn(4) <= '0';
- WAIT FOR 200000 ps;
- dataIn(4) <= '1';
- WAIT FOR 160000 ps;
- dataIn(4) <= '0';
- WAIT FOR 40000 ps;
- dataIn(4) <= '1';
- WAIT FOR 320000 ps;
- dataIn(4) <= '0';
- WAIT FOR 160000 ps;
- dataIn(4) <= '1';
- WAIT FOR 40000 ps;
- dataIn(4) <= '0';
-WAIT;
-END PROCESS t_prcs_dataIn_4;
--- dataIn[3]
-t_prcs_dataIn_3: PROCESS
-BEGIN
- dataIn(3) <= '1';
- WAIT FOR 160000 ps;
- dataIn(3) <= '0';
- WAIT FOR 40000 ps;
- dataIn(3) <= '1';
- WAIT FOR 120000 ps;
- dataIn(3) <= '0';
- WAIT FOR 40000 ps;
- dataIn(3) <= '1';
- WAIT FOR 80000 ps;
- dataIn(3) <= '0';
- WAIT FOR 80000 ps;
- dataIn(3) <= '1';
- WAIT FOR 40000 ps;
- dataIn(3) <= '0';
- WAIT FOR 40000 ps;
- dataIn(3) <= '1';
- WAIT FOR 160000 ps;
- dataIn(3) <= '0';
- WAIT FOR 40000 ps;
- dataIn(3) <= '1';
- WAIT FOR 120000 ps;
- dataIn(3) <= '0';
-WAIT;
-END PROCESS t_prcs_dataIn_3;
--- dataIn[2]
-t_prcs_dataIn_2: PROCESS
-BEGIN
- dataIn(2) <= '0';
- WAIT FOR 80000 ps;
- dataIn(2) <= '1';
- WAIT FOR 40000 ps;
- dataIn(2) <= '0';
- WAIT FOR 120000 ps;
- dataIn(2) <= '1';
- WAIT FOR 40000 ps;
- dataIn(2) <= '0';
- WAIT FOR 40000 ps;
- dataIn(2) <= '1';
- WAIT FOR 40000 ps;
- dataIn(2) <= '0';
- WAIT FOR 120000 ps;
- dataIn(2) <= '1';
- WAIT FOR 40000 ps;
- dataIn(2) <= '0';
- WAIT FOR 40000 ps;
- dataIn(2) <= '1';
- WAIT FOR 80000 ps;
- dataIn(2) <= '0';
- WAIT FOR 40000 ps;
- dataIn(2) <= '1';
- WAIT FOR 40000 ps;
- dataIn(2) <= '0';
- WAIT FOR 40000 ps;
- dataIn(2) <= '1';
- WAIT FOR 80000 ps;
- dataIn(2) <= '0';
- WAIT FOR 80000 ps;
- dataIn(2) <= '1';
-WAIT;
-END PROCESS t_prcs_dataIn_2;
--- dataIn[1]
-t_prcs_dataIn_1: PROCESS
-BEGIN
- dataIn(1) <= '1';
- WAIT FOR 80000 ps;
- dataIn(1) <= '0';
- WAIT FOR 80000 ps;
- dataIn(1) <= '1';
- WAIT FOR 80000 ps;
- dataIn(1) <= '0';
- WAIT FOR 80000 ps;
- dataIn(1) <= '1';
- WAIT FOR 40000 ps;
- dataIn(1) <= '0';
- WAIT FOR 40000 ps;
- dataIn(1) <= '1';
- WAIT FOR 40000 ps;
- dataIn(1) <= '0';
- WAIT FOR 80000 ps;
- dataIn(1) <= '1';
- WAIT FOR 40000 ps;
- dataIn(1) <= '0';
- WAIT FOR 120000 ps;
- dataIn(1) <= '1';
- WAIT FOR 40000 ps;
- dataIn(1) <= '0';
- WAIT FOR 40000 ps;
- dataIn(1) <= '1';
- WAIT FOR 40000 ps;
- dataIn(1) <= '0';
- WAIT FOR 40000 ps;
- dataIn(1) <= '1';
- WAIT FOR 40000 ps;
- dataIn(1) <= '0';
- WAIT FOR 40000 ps;
- dataIn(1) <= '1';
- WAIT FOR 40000 ps;
- dataIn(1) <= '0';
-WAIT;
-END PROCESS t_prcs_dataIn_1;
--- dataIn[0]
-t_prcs_dataIn_0: PROCESS
-BEGIN
- dataIn(0) <= '1';
- WAIT FOR 160000 ps;
- dataIn(0) <= '0';
- WAIT FOR 40000 ps;
- dataIn(0) <= '1';
- WAIT FOR 120000 ps;
- dataIn(0) <= '0';
- WAIT FOR 40000 ps;
- dataIn(0) <= '1';
- WAIT FOR 40000 ps;
- dataIn(0) <= '0';
- WAIT FOR 40000 ps;
- dataIn(0) <= '1';
- WAIT FOR 40000 ps;
- dataIn(0) <= '0';
- WAIT FOR 40000 ps;
- dataIn(0) <= '1';
- WAIT FOR 40000 ps;
- dataIn(0) <= '0';
- WAIT FOR 160000 ps;
- dataIn(0) <= '1';
- WAIT FOR 40000 ps;
- dataIn(0) <= '0';
- WAIT FOR 80000 ps;
- dataIn(0) <= '1';
- WAIT FOR 80000 ps;
- dataIn(0) <= '0';
- WAIT FOR 40000 ps;
- dataIn(0) <= '1';
-WAIT;
-END PROCESS t_prcs_dataIn_0;
-END Register8_arch;
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.do b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.do
deleted file mode 100644
index cc16917..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.do
+++ /dev/null
@@ -1,17 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vcom -work work RegisterDemo.vho
-vcom -work work Register8.vwf.vht
-vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Register8_vhd_vec_tst
-vcd file -direction RegisterDemo.msim.vcd
-vcd add -internal Register8_vhd_vec_tst/*
-vcd add -internal Register8_vhd_vec_tst/i1/*
-proc simTimestamp {} {
- echo "Simulation time: $::now ps"
- if { [string equal running [runStatus]] } {
- after 2500 simTimestamp
- }
-}
-after 2500 simTimestamp
-run -all
-quit -f
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.msim.vcd b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.msim.vcd
deleted file mode 100644
index 78a0e20..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.msim.vcd
+++ /dev/null
@@ -1,863 +0,0 @@
-$comment
- File created using the following command:
- vcd file RegisterDemo.msim.vcd -direction
-$end
-$date
- Wed Mar 22 09:15:32 2023
-$end
-$version
- ModelSim Version 2020.1
-$end
-$timescale
- 1ps
-$end
-
-$scope module register8_vhd_vec_tst $end
-$var wire 1 ! clk $end
-$var wire 1 " dataIn [7] $end
-$var wire 1 # dataIn [6] $end
-$var wire 1 $ dataIn [5] $end
-$var wire 1 % dataIn [4] $end
-$var wire 1 & dataIn [3] $end
-$var wire 1 ' dataIn [2] $end
-$var wire 1 ( dataIn [1] $end
-$var wire 1 ) dataIn [0] $end
-$var wire 1 * dataOut [7] $end
-$var wire 1 + dataOut [6] $end
-$var wire 1 , dataOut [5] $end
-$var wire 1 - dataOut [4] $end
-$var wire 1 . dataOut [3] $end
-$var wire 1 / dataOut [2] $end
-$var wire 1 0 dataOut [1] $end
-$var wire 1 1 dataOut [0] $end
-$var wire 1 2 wrEn $end
-
-$scope module i1 $end
-$var wire 1 3 gnd $end
-$var wire 1 4 vcc $end
-$var wire 1 5 unknown $end
-$var wire 1 6 devoe $end
-$var wire 1 7 devclrn $end
-$var wire 1 8 devpor $end
-$var wire 1 9 ww_devoe $end
-$var wire 1 : ww_devclrn $end
-$var wire 1 ; ww_devpor $end
-$var wire 1 < ww_dataIn [7] $end
-$var wire 1 = ww_dataIn [6] $end
-$var wire 1 > ww_dataIn [5] $end
-$var wire 1 ? ww_dataIn [4] $end
-$var wire 1 @ ww_dataIn [3] $end
-$var wire 1 A ww_dataIn [2] $end
-$var wire 1 B ww_dataIn [1] $end
-$var wire 1 C ww_dataIn [0] $end
-$var wire 1 D ww_clk $end
-$var wire 1 E ww_wrEn $end
-$var wire 1 F ww_dataOut [7] $end
-$var wire 1 G ww_dataOut [6] $end
-$var wire 1 H ww_dataOut [5] $end
-$var wire 1 I ww_dataOut [4] $end
-$var wire 1 J ww_dataOut [3] $end
-$var wire 1 K ww_dataOut [2] $end
-$var wire 1 L ww_dataOut [1] $end
-$var wire 1 M ww_dataOut [0] $end
-$var wire 1 N \dataOut[0]~output_o\ $end
-$var wire 1 O \dataOut[1]~output_o\ $end
-$var wire 1 P \dataOut[2]~output_o\ $end
-$var wire 1 Q \dataOut[3]~output_o\ $end
-$var wire 1 R \dataOut[4]~output_o\ $end
-$var wire 1 S \dataOut[5]~output_o\ $end
-$var wire 1 T \dataOut[6]~output_o\ $end
-$var wire 1 U \dataOut[7]~output_o\ $end
-$var wire 1 V \clk~input_o\ $end
-$var wire 1 W \dataIn[0]~input_o\ $end
-$var wire 1 X \wrEn~input_o\ $end
-$var wire 1 Y \dataOut[0]~reg0_q\ $end
-$var wire 1 Z \dataIn[1]~input_o\ $end
-$var wire 1 [ \dataOut[1]~reg0_q\ $end
-$var wire 1 \ \dataIn[2]~input_o\ $end
-$var wire 1 ] \dataOut[2]~reg0_q\ $end
-$var wire 1 ^ \dataIn[3]~input_o\ $end
-$var wire 1 _ \dataOut[3]~reg0_q\ $end
-$var wire 1 ` \dataIn[4]~input_o\ $end
-$var wire 1 a \dataOut[4]~reg0_q\ $end
-$var wire 1 b \dataIn[5]~input_o\ $end
-$var wire 1 c \dataOut[5]~reg0_q\ $end
-$var wire 1 d \dataIn[6]~input_o\ $end
-$var wire 1 e \dataOut[6]~reg0_q\ $end
-$var wire 1 f \dataIn[7]~input_o\ $end
-$var wire 1 g \dataOut[7]~reg0_q\ $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0!
-02
-03
-14
-x5
-16
-17
-18
-19
-1:
-1;
-0D
-0E
-0N
-0O
-0P
-0Q
-0R
-0S
-0T
-0U
-0V
-1W
-0X
-0Y
-1Z
-0[
-0\
-0]
-1^
-0_
-0`
-0a
-0b
-0c
-0d
-0e
-1f
-0g
-1"
-0#
-0$
-0%
-1&
-0'
-1(
-1)
-1<
-0=
-0>
-0?
-1@
-0A
-1B
-1C
-0F
-0G
-0H
-0I
-0J
-0K
-0L
-0M
-0*
-0+
-0,
-0-
-0.
-0/
-00
-01
-$end
-#20000
-1!
-1D
-1V
-#40000
-0!
-0D
-0V
-#60000
-1!
-1D
-1V
-#80000
-0!
-1#
-1$
-1'
-0(
-0D
-0B
-1A
-1>
-1=
-1d
-1b
-1\
-0Z
-0V
-#100000
-1!
-1D
-1V
-#120000
-0!
-0$
-0'
-0D
-0A
-0>
-0b
-0\
-0V
-#140000
-1!
-1D
-1V
-#160000
-0!
-0#
-1(
-0&
-0)
-0D
-0C
-1B
-0@
-0=
-0d
-0^
-1Z
-0W
-0V
-#180000
-1!
-1D
-1V
-#200000
-0!
-1#
-1&
-1)
-0"
-1%
-0D
-1C
-1@
-1?
-1=
-0<
-0f
-1d
-1`
-1^
-1W
-0V
-#220000
-1!
-1D
-1V
-#240000
-0!
-0#
-1"
-0(
-1$
-1'
-0D
-0B
-1A
-1>
-0=
-1<
-1f
-0d
-1b
-1\
-0Z
-0V
-#260000
-1!
-1D
-1V
-#280000
-0!
-1#
-0$
-0'
-0D
-0A
-0>
-1=
-1d
-0b
-0\
-0V
-#300000
-1!
-1D
-1V
-#320000
-0!
-0#
-1'
-1(
-0&
-0)
-0D
-0C
-1B
-1A
-0@
-0=
-0d
-0^
-1\
-1Z
-0W
-0V
-#340000
-1!
-1D
-1V
-#360000
-0!
-0'
-0(
-1&
-1)
-1$
-0"
-0%
-0D
-1C
-0B
-0A
-1@
-0?
-1>
-0<
-0f
-1b
-0`
-1^
-0\
-0Z
-1W
-0V
-#380000
-1!
-1D
-1V
-#400000
-0!
-1(
-0)
-0$
-1"
-1%
-12
-0D
-0C
-1B
-1?
-0>
-1<
-1E
-1X
-1f
-0b
-1`
-1Z
-0W
-0V
-#420000
-1!
-1D
-1V
-1[
-1_
-1a
-1g
-1U
-1R
-1Q
-1O
-1F
-1I
-1J
-1L
-10
-1.
-1-
-1*
-#440000
-0!
-0(
-1)
-0"
-0&
-1#
-0D
-1C
-0B
-0@
-1=
-0<
-0f
-1d
-0^
-0Z
-1W
-0V
-#460000
-1!
-1D
-1V
-1Y
-0[
-0_
-1e
-0g
-0U
-1T
-0Q
-0O
-1N
-0F
-1G
-0J
-0L
-1M
-11
-00
-0.
-1+
-0*
-#480000
-0!
-0)
-1$
-1'
-0D
-0C
-1A
-1>
-1b
-1\
-0W
-0V
-#500000
-1!
-1D
-1V
-0Y
-1]
-1c
-1S
-1P
-0N
-1H
-1K
-0M
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-#520000
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-1]
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-1g
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-0T
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-0Q
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-0N
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-1K
-0L
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-01
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-0.
-0,
-0+
-1*
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-0!
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-1!
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-1L
-0M
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-10
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.sft b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.vho b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.vho
deleted file mode 100644
index 671d429..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.vho
+++ /dev/null
@@ -1,414 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/22/2023 09:15:30"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY ALTERA;
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY Register8 IS
- PORT (
- dataIn : IN std_logic_vector(7 DOWNTO 0);
- clk : IN std_logic;
- wrEn : IN std_logic;
- dataOut : OUT std_logic_vector(7 DOWNTO 0)
- );
-END Register8;
-
-ARCHITECTURE structure OF Register8 IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_dataIn : std_logic_vector(7 DOWNTO 0);
-SIGNAL ww_clk : std_logic;
-SIGNAL ww_wrEn : std_logic;
-SIGNAL ww_dataOut : std_logic_vector(7 DOWNTO 0);
-SIGNAL \dataOut[0]~output_o\ : std_logic;
-SIGNAL \dataOut[1]~output_o\ : std_logic;
-SIGNAL \dataOut[2]~output_o\ : std_logic;
-SIGNAL \dataOut[3]~output_o\ : std_logic;
-SIGNAL \dataOut[4]~output_o\ : std_logic;
-SIGNAL \dataOut[5]~output_o\ : std_logic;
-SIGNAL \dataOut[6]~output_o\ : std_logic;
-SIGNAL \dataOut[7]~output_o\ : std_logic;
-SIGNAL \clk~input_o\ : std_logic;
-SIGNAL \dataIn[0]~input_o\ : std_logic;
-SIGNAL \wrEn~input_o\ : std_logic;
-SIGNAL \dataOut[0]~reg0_q\ : std_logic;
-SIGNAL \dataIn[1]~input_o\ : std_logic;
-SIGNAL \dataOut[1]~reg0_q\ : std_logic;
-SIGNAL \dataIn[2]~input_o\ : std_logic;
-SIGNAL \dataOut[2]~reg0_q\ : std_logic;
-SIGNAL \dataIn[3]~input_o\ : std_logic;
-SIGNAL \dataOut[3]~reg0_q\ : std_logic;
-SIGNAL \dataIn[4]~input_o\ : std_logic;
-SIGNAL \dataOut[4]~reg0_q\ : std_logic;
-SIGNAL \dataIn[5]~input_o\ : std_logic;
-SIGNAL \dataOut[5]~reg0_q\ : std_logic;
-SIGNAL \dataIn[6]~input_o\ : std_logic;
-SIGNAL \dataOut[6]~reg0_q\ : std_logic;
-SIGNAL \dataIn[7]~input_o\ : std_logic;
-SIGNAL \dataOut[7]~reg0_q\ : std_logic;
-
-BEGIN
-
-ww_dataIn <= dataIn;
-ww_clk <= clk;
-ww_wrEn <= wrEn;
-dataOut <= ww_dataOut;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
-\dataOut[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \dataOut[0]~reg0_q\,
- devoe => ww_devoe,
- o => \dataOut[0]~output_o\);
-
-\dataOut[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \dataOut[1]~reg0_q\,
- devoe => ww_devoe,
- o => \dataOut[1]~output_o\);
-
-\dataOut[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \dataOut[2]~reg0_q\,
- devoe => ww_devoe,
- o => \dataOut[2]~output_o\);
-
-\dataOut[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \dataOut[3]~reg0_q\,
- devoe => ww_devoe,
- o => \dataOut[3]~output_o\);
-
-\dataOut[4]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \dataOut[4]~reg0_q\,
- devoe => ww_devoe,
- o => \dataOut[4]~output_o\);
-
-\dataOut[5]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \dataOut[5]~reg0_q\,
- devoe => ww_devoe,
- o => \dataOut[5]~output_o\);
-
-\dataOut[6]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \dataOut[6]~reg0_q\,
- devoe => ww_devoe,
- o => \dataOut[6]~output_o\);
-
-\dataOut[7]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \dataOut[7]~reg0_q\,
- devoe => ww_devoe,
- o => \dataOut[7]~output_o\);
-
-\clk~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_clk,
- o => \clk~input_o\);
-
-\dataIn[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_dataIn(0),
- o => \dataIn[0]~input_o\);
-
-\wrEn~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_wrEn,
- o => \wrEn~input_o\);
-
-\dataOut[0]~reg0\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \clk~input_o\,
- d => \dataIn[0]~input_o\,
- ena => \wrEn~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \dataOut[0]~reg0_q\);
-
-\dataIn[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_dataIn(1),
- o => \dataIn[1]~input_o\);
-
-\dataOut[1]~reg0\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \clk~input_o\,
- d => \dataIn[1]~input_o\,
- ena => \wrEn~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \dataOut[1]~reg0_q\);
-
-\dataIn[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_dataIn(2),
- o => \dataIn[2]~input_o\);
-
-\dataOut[2]~reg0\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \clk~input_o\,
- d => \dataIn[2]~input_o\,
- ena => \wrEn~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \dataOut[2]~reg0_q\);
-
-\dataIn[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_dataIn(3),
- o => \dataIn[3]~input_o\);
-
-\dataOut[3]~reg0\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \clk~input_o\,
- d => \dataIn[3]~input_o\,
- ena => \wrEn~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \dataOut[3]~reg0_q\);
-
-\dataIn[4]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_dataIn(4),
- o => \dataIn[4]~input_o\);
-
-\dataOut[4]~reg0\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \clk~input_o\,
- d => \dataIn[4]~input_o\,
- ena => \wrEn~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \dataOut[4]~reg0_q\);
-
-\dataIn[5]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_dataIn(5),
- o => \dataIn[5]~input_o\);
-
-\dataOut[5]~reg0\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \clk~input_o\,
- d => \dataIn[5]~input_o\,
- ena => \wrEn~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \dataOut[5]~reg0_q\);
-
-\dataIn[6]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_dataIn(6),
- o => \dataIn[6]~input_o\);
-
-\dataOut[6]~reg0\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \clk~input_o\,
- d => \dataIn[6]~input_o\,
- ena => \wrEn~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \dataOut[6]~reg0_q\);
-
-\dataIn[7]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_dataIn(7),
- o => \dataIn[7]~input_o\);
-
-\dataOut[7]~reg0\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \clk~input_o\,
- d => \dataIn[7]~input_o\,
- ena => \wrEn~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \dataOut[7]~reg0_q\);
-
-ww_dataOut(0) <= \dataOut[0]~output_o\;
-
-ww_dataOut(1) <= \dataOut[1]~output_o\;
-
-ww_dataOut(2) <= \dataOut[2]~output_o\;
-
-ww_dataOut(3) <= \dataOut[3]~output_o\;
-
-ww_dataOut(4) <= \dataOut[4]~output_o\;
-
-ww_dataOut(5) <= \dataOut[5]~output_o\;
-
-ww_dataOut(6) <= \dataOut[6]~output_o\;
-
-ww_dataOut(7) <= \dataOut[7]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_20230322091532.sim.vwf b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_20230322091532.sim.vwf
deleted file mode 100644
index 20e9aaf..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_20230322091532.sim.vwf
+++ /dev/null
@@ -1,874 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-
-HEADER
-{
- VERSION = 1;
- TIME_UNIT = ns;
- DATA_OFFSET = 0.0;
- DATA_DURATION = 1000.0;
- SIMULATION_TIME = 0.0;
- GRID_PHASE = 0.0;
- GRID_PERIOD = 10.0;
- GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("clk")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("dataIn")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 8;
- LSB_INDEX = 0;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-SIGNAL("dataIn[7]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "dataIn";
-}
-
-SIGNAL("dataIn[6]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "dataIn";
-}
-
-SIGNAL("dataIn[5]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "dataIn";
-}
-
-SIGNAL("dataIn[4]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "dataIn";
-}
-
-SIGNAL("dataIn[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "dataIn";
-}
-
-SIGNAL("dataIn[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "dataIn";
-}
-
-SIGNAL("dataIn[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "dataIn";
-}
-
-SIGNAL("dataIn[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "dataIn";
-}
-
-SIGNAL("dataOut")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = BUS;
- WIDTH = 8;
- LSB_INDEX = 0;
- DIRECTION = OUTPUT;
- PARENT = "";
-}
-
-SIGNAL("dataOut[7]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "dataOut";
-}
-
-SIGNAL("dataOut[6]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "dataOut";
-}
-
-SIGNAL("dataOut[5]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "dataOut";
-}
-
-SIGNAL("dataOut[4]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "dataOut";
-}
-
-SIGNAL("dataOut[3]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "dataOut";
-}
-
-SIGNAL("dataOut[2]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "dataOut";
-}
-
-SIGNAL("dataOut[1]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "dataOut";
-}
-
-SIGNAL("dataOut[0]")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = OUTPUT;
- PARENT = "dataOut";
-}
-
-SIGNAL("wrEn")
-{
- VALUE_TYPE = NINE_LEVEL_BIT;
- SIGNAL_TYPE = SINGLE_BIT;
- WIDTH = 1;
- LSB_INDEX = -1;
- DIRECTION = INPUT;
- PARENT = "";
-}
-
-TRANSITION_LIST("clk")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- LEVEL 0 FOR 20.0;
- LEVEL 1 FOR 20.0;
- }
- }
-}
-
-TRANSITION_LIST("dataIn[7]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 200.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("dataIn[6]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("dataIn[5]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("dataIn[4]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 200.0;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 320.0;
- LEVEL 0 FOR 160.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 80.0;
- }
- }
-}
-
-TRANSITION_LIST("dataIn[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 80.0;
- }
- }
-}
-
-TRANSITION_LIST("dataIn[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- }
- }
-}
-
-TRANSITION_LIST("dataIn[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("dataIn[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 160.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- }
- }
-}
-
-TRANSITION_LIST("dataOut[7]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 420.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 220.0;
- }
- }
-}
-
-TRANSITION_LIST("dataOut[6]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 460.0;
- LEVEL 1 FOR 120.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 300.0;
- }
- }
-}
-
-TRANSITION_LIST("dataOut[5]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 500.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 220.0;
- }
- }
-}
-
-TRANSITION_LIST("dataOut[4]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 420.0;
- LEVEL 1 FOR 320.0;
- LEVEL 0 FOR 260.0;
- }
- }
-}
-
-TRANSITION_LIST("dataOut[3]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 420.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 160.0;
- LEVEL 0 FOR 220.0;
- }
- }
-}
-
-TRANSITION_LIST("dataOut[2]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 500.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 80.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 220.0;
- }
- }
-}
-
-TRANSITION_LIST("dataOut[1]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 420.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 80.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 120.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 220.0;
- }
- }
-}
-
-TRANSITION_LIST("dataOut[0]")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 460.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 40.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 160.0;
- LEVEL 1 FOR 40.0;
- LEVEL 0 FOR 220.0;
- }
- }
-}
-
-TRANSITION_LIST("wrEn")
-{
- NODE
- {
- REPEAT = 1;
- NODE
- {
- REPEAT = 1;
- LEVEL 0 FOR 400.0;
- LEVEL 1 FOR 400.0;
- LEVEL 0 FOR 200.0;
- }
- }
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "wrEn";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 0;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "clk";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 1;
- TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 2;
- TREE_LEVEL = 0;
- CHILDREN = 3, 4, 5, 6, 7, 8, 9, 10;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn[7]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 3;
- TREE_LEVEL = 1;
- PARENT = 2;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn[6]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 4;
- TREE_LEVEL = 1;
- PARENT = 2;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn[5]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 5;
- TREE_LEVEL = 1;
- PARENT = 2;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn[4]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 6;
- TREE_LEVEL = 1;
- PARENT = 2;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 7;
- TREE_LEVEL = 1;
- PARENT = 2;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 8;
- TREE_LEVEL = 1;
- PARENT = 2;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 9;
- TREE_LEVEL = 1;
- PARENT = 2;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataIn[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 10;
- TREE_LEVEL = 1;
- PARENT = 2;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataOut";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 11;
- TREE_LEVEL = 0;
- CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataOut[7]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 12;
- TREE_LEVEL = 1;
- PARENT = 11;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataOut[6]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 13;
- TREE_LEVEL = 1;
- PARENT = 11;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataOut[5]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 14;
- TREE_LEVEL = 1;
- PARENT = 11;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataOut[4]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 15;
- TREE_LEVEL = 1;
- PARENT = 11;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataOut[3]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 16;
- TREE_LEVEL = 1;
- PARENT = 11;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataOut[2]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 17;
- TREE_LEVEL = 1;
- PARENT = 11;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataOut[1]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 18;
- TREE_LEVEL = 1;
- PARENT = 11;
-}
-
-DISPLAY_LINE
-{
- CHANNEL = "dataOut[0]";
- EXPAND_STATUS = COLLAPSED;
- RADIX = Binary;
- TREE_INDEX = 19;
- TREE_LEVEL = 1;
- PARENT = 11;
-}
-
-TIME_BAR
-{
- TIME = 0;
- MASTER = TRUE;
-}
-;
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_modelsim.xrf
deleted file mode 100644
index 71f73e4..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_modelsim.xrf
+++ /dev/null
@@ -1,34 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cbx.xml
-design_name = Register8
-instance = comp, \dataOut[0]~output\, dataOut[0]~output, Register8, 1
-instance = comp, \dataOut[1]~output\, dataOut[1]~output, Register8, 1
-instance = comp, \dataOut[2]~output\, dataOut[2]~output, Register8, 1
-instance = comp, \dataOut[3]~output\, dataOut[3]~output, Register8, 1
-instance = comp, \dataOut[4]~output\, dataOut[4]~output, Register8, 1
-instance = comp, \dataOut[5]~output\, dataOut[5]~output, Register8, 1
-instance = comp, \dataOut[6]~output\, dataOut[6]~output, Register8, 1
-instance = comp, \dataOut[7]~output\, dataOut[7]~output, Register8, 1
-instance = comp, \clk~input\, clk~input, Register8, 1
-instance = comp, \dataIn[0]~input\, dataIn[0]~input, Register8, 1
-instance = comp, \wrEn~input\, wrEn~input, Register8, 1
-instance = comp, \dataOut[0]~reg0\, dataOut[0]~reg0, Register8, 1
-instance = comp, \dataIn[1]~input\, dataIn[1]~input, Register8, 1
-instance = comp, \dataOut[1]~reg0\, dataOut[1]~reg0, Register8, 1
-instance = comp, \dataIn[2]~input\, dataIn[2]~input, Register8, 1
-instance = comp, \dataOut[2]~reg0\, dataOut[2]~reg0, Register8, 1
-instance = comp, \dataIn[3]~input\, dataIn[3]~input, Register8, 1
-instance = comp, \dataOut[3]~reg0\, dataOut[3]~reg0, Register8, 1
-instance = comp, \dataIn[4]~input\, dataIn[4]~input, Register8, 1
-instance = comp, \dataOut[4]~reg0\, dataOut[4]~reg0, Register8, 1
-instance = comp, \dataIn[5]~input\, dataIn[5]~input, Register8, 1
-instance = comp, \dataOut[5]~reg0\, dataOut[5]~reg0, Register8, 1
-instance = comp, \dataIn[6]~input\, dataIn[6]~input, Register8, 1
-instance = comp, \dataOut[6]~reg0\, dataOut[6]~reg0, Register8, 1
-instance = comp, \dataIn[7]~input\, dataIn[7]~input, Register8, 1
-instance = comp, \dataOut[7]~reg0\, dataOut[7]~reg0, Register8, 1
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/transcript
deleted file mode 100644
index 0b7a78d..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/transcript
+++ /dev/null
@@ -1,47 +0,0 @@
-# do RegisterDemo.do
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 09:15:31 on Mar 22,2023
-# vcom -work work RegisterDemo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package dffeas_pack
-# -- Loading package altera_primitives_components
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity Register8
-# -- Compiling architecture structure of Register8
-# End time: 09:15:32 on Mar 22,2023, Elapsed time: 0:00:01
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 09:15:32 on Mar 22,2023
-# vcom -work work Register8.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity Register8_vhd_vec_tst
-# -- Compiling architecture Register8_arch of Register8_vhd_vec_tst
-# End time: 09:15:32 on Mar 22,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Register8_vhd_vec_tst
-# Start time: 09:15:32 on Mar 22,2023
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading work.register8_vhd_vec_tst(register8_arch)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading altera.dffeas_pack
-# Loading altera.altera_primitives_components
-# Loading cycloneive.cycloneive_atom_pack(body)
-# Loading cycloneive.cycloneive_components
-# Loading work.register8(structure)
-# Loading ieee.std_logic_arith(body)
-# Loading cycloneive.cycloneive_io_obuf(arch)
-# Loading cycloneive.cycloneive_io_ibuf(arch)
-# Loading altera.dffeas(vital_dffeas)
-# after#31
-# End time: 09:15:32 on Mar 22,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/vwf_sim_transcript
deleted file mode 100644
index 87f116b..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/vwf_sim_transcript
+++ /dev/null
@@ -1,76 +0,0 @@
-Determining the location of the ModelSim executable...
-
-Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
-
-To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
-Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
-
-**** Generating the ModelSim Testbench ****
-
-quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off RegisterDemo -c RegisterDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vht"
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Mar 22 09:15:27 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off RegisterDemo -c RegisterDemo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vhtInfo (119006): Selected device EP4CE115F29C7 for design "RegisterDemo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Completed successfully.
-
-**** Generating the functional simulation netlist ****
-
-quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/" RegisterDemo -c RegisterDemo
-
-Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Mar 22 09:15:29 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/ RegisterDemo -c RegisterDemoInfo (119006): Selected device EP4CE115F29C7 for design "RegisterDemo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file RegisterDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 615 megabytes Info: Processing ended: Wed Mar 22 09:15:30 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01
-Completed successfully.
-
-**** Generating the ModelSim .do script ****
-
-/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.do generated.
-
-Completed successfully.
-
-**** Running the ModelSim simulation ****
-
-/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do RegisterDemo.do
-
-Reading pref.tcl
-# 2020.1
-# do RegisterDemo.do
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 09:15:31 on Mar 22,2023# vcom -work work RegisterDemo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package dffeas_pack# -- Loading package altera_primitives_components
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity Register8
-# -- Compiling architecture structure of Register8
-# End time: 09:15:32 on Mar 22,2023, Elapsed time: 0:00:01
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 09:15:32 on Mar 22,2023# vcom -work work Register8.vwf.vht
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling entity Register8_vhd_vec_tst# -- Compiling architecture Register8_arch of Register8_vhd_vec_tst
-# End time: 09:15:32 on Mar 22,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Register8_vhd_vec_tst # Start time: 09:15:32 on Mar 22,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.register8_vhd_vec_tst(register8_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading altera.dffeas_pack# Loading altera.altera_primitives_components# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.register8(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading altera.dffeas(vital_dffeas)
-# after#31
-# End time: 09:15:32 on Mar 22,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
-Completed successfully.
-
-**** Converting ModelSim VCD to vector waveform ****
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf...
-
-Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.msim.vcd...
-
-Processing channel transitions...
-
-Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_20230322091532.sim.vwf
-
-Finished VCD to VWF conversion.
-
-Completed successfully.
-
-All completed.
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_info
deleted file mode 100644
index e49f4d7..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_info
+++ /dev/null
@@ -1,105 +0,0 @@
-m255
-K4
-z2
-!s11e vcom 2020.1 2020.02, Feb 28 2020
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-Z0 d/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim
-Eregister8
-Z1 w1679476530
-Z2 DPx10 cycloneive 20 cycloneive_atom_pack 0 22 WOh:M[al;oVzG5c`D0
-Z3 DPx10 cycloneive 21 cycloneive_components 0 22 zGMDhP>8e@2k@f0ekiXP8Q9dRClKfK1Zn7j1
-Z5 DPx6 altera 11 dffeas_pack 0 22 dc5N=DKXMMTVYdUQ@D3FA2
-Z6 DPx4 ieee 12 vital_timing 0 22 J>EBealN09f8GzldA[z2>3
-Z7 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
-Z8 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
-Z9 DPx6 altera 28 altera_primitives_components 0 22 ca:ehlQAg4;_gVV:^8MAg3
-!i122 0
-R0
-Z10 8RegisterDemo.vho
-Z11 FRegisterDemo.vho
-l0
-L37 1
-VVlE;3DEQD1QSeZ6g`]h7X1
-!s100 X5eG7YZL=f1^zzaD4`;H@>giSDZn1
-!s100 Mok?CPQT5i3K>i?OWHQid0
-R12
-32
-R13
-!i10b 1
-R14
-R15
-R16
-!i113 1
-R17
-R18
-Eregister8_vhd_vec_tst
-Z19 w1679476528
-R7
-R8
-!i122 1
-R0
-Z20 8Register8.vwf.vht
-Z21 FRegister8.vwf.vht
-l0
-L32 1
-V<0FH[1`=PTlGok:DD5J_[0
-!s100 J69iBXek>Ja25:B71kB2f0
-R12
-32
-R13
-!i10b 1
-Z22 !s108 1679476532.000000
-Z23 !s90 -work|work|Register8.vwf.vht|
-!s107 Register8.vwf.vht|
-!i113 1
-R17
-R18
-Aregister8_arch
-R7
-R8
-DEx4 work 21 register8_vhd_vec_tst 0 22 <0FH[1`=PTlGok:DD5J_[0
-!i122 1
-l49
-L34 306
-VR@mihK9Xh^8H5TR]YX@^Z0
-!s100 X=LZSzM>;2
-R12
-32
-R13
-!i10b 1
-R22
-R23
-Z24 !s107 Register8.vwf.vht|
-!i113 1
-R17
-R18
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_lib.qdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_lib.qdb
deleted file mode 100644
index 921c800..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_lib.qdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_lib1_0.qdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_lib1_0.qdb
deleted file mode 100644
index 1174d87..0000000
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_lib1_0.qpg b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_lib1_0.qpg
deleted file mode 100644
index cd20dcb..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_lib1_0.qpg and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_lib1_0.qtl b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_lib1_0.qtl
deleted file mode 100644
index f10815b..0000000
Binary files a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_lib1_0.qtl and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_vmake b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_vmake
deleted file mode 100644
index 37aa36a..0000000
--- a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_vmake
+++ /dev/null
@@ -1,4 +0,0 @@
-m255
-K4
-z0
-cModel Technology
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd.bak b/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd.bak
deleted file mode 100644
index 9604b53..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd.bak
+++ /dev/null
@@ -1,2 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf b/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf
index 21278a1..57d988f 100644
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf
+++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf
@@ -182,7 +182,7 @@ https://fpgasoftware.intel.com/eula.
(symbol
(rect 304 288 448 368)
(text "FreqDivider" (rect 5 0 64 11)(font "Arial" ))
- (text "inst2" (rect 8 64 32 77)(font "Intel Clear" ))
+ (text "inst4" (rect 8 64 33 77)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
@@ -231,11 +231,11 @@ https://fpgasoftware.intel.com/eula.
(pt 480 296)
(pt 480 320)
)
-(connector
- (pt 448 320)
- (pt 480 320)
-)
(connector
(pt 296 320)
(pt 304 320)
)
+(connector
+ (pt 448 320)
+ (pt 480 320)
+)
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.qpf b/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.qpf
deleted file mode 100644
index ec1e53f..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 10:48:27 March 22, 2023
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "20.1"
-DATE = "10:48:27 March 22, 2023"
-
-# Revisions
-
-PROJECT_REVISION = "AccN_Demo"
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.qsf b/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.qsf
deleted file mode 100644
index 6073a27..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.qsf
+++ /dev/null
@@ -1,587 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 10:48:27 March 22, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# AccN_Demo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY AccN_Demo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:48:27 MARCH 22, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VHDL_FILE FreqDivider.vhd
-set_global_assignment -name BDF_FILE AccN_Demo.bdf
-set_global_assignment -name VHDL_FILE AccN.vhd
-set_global_assignment -name VHDL_FILE RegN.vhd
-set_global_assignment -name VHDL_FILE AdderN.vhd
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.qsf.bak b/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.qsf.bak
deleted file mode 100644
index 6073a27..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.qsf.bak
+++ /dev/null
@@ -1,587 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 10:48:27 March 22, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# AccN_Demo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY AccN_Demo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:48:27 MARCH 22, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VHDL_FILE FreqDivider.vhd
-set_global_assignment -name BDF_FILE AccN_Demo.bdf
-set_global_assignment -name VHDL_FILE AccN.vhd
-set_global_assignment -name VHDL_FILE RegN.vhd
-set_global_assignment -name VHDL_FILE AdderN.vhd
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd.bak b/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd.bak
deleted file mode 100644
index 780634e..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd.bak
+++ /dev/null
@@ -1,17 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity AdderN is
- generic ( N : positive )
- port
- (
- operand1, operand2 : in std_logic_vector((N-1) downto 0 );
- result : out std_logic_vector( N downto 0 )
- );
-end AdderN;
-
-architecture Behavioral of AdderN is
-begin
- result <= operand1 + operand2;
-end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd b/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd
index 74d55de..1673a6f 100644
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd
+++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd
@@ -13,12 +13,12 @@ architecture Behavioral of FreqDivider is
signal s_halfWay : unsigned(31 downto 0);
signal k : std_logic_vector(31 downto 0);
begin
- k <= x"02AD7840";
- s_halfWay <= unsigned(k);
-
+ k <= x"008D7840";
+ s_halfWay <= unsigned(k);
+
process(clkIn)
- begin
- if (rising_edge(clkIn)) then
+ begin
+ if (rising_edge(clkIn)) then
if (s_counter = s_halfWay - 1) then
clkOut <= '0';
s_counter <= (others => '0');
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd.bak b/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd.bak
deleted file mode 100644
index 9eb9d16..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd.bak
+++ /dev/null
@@ -1,33 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-
-entity FreqDivider is
- port (clkIn : in std_logic;
- clkOut : out std_logic
- );
-end FreqDivider;
-
-architecture Behavioral of FreqDivider is
- signal s_counter : unsigned(31 downto 0);
- signal s_halfWay : unsigned(31 downto 0);
- signal k : std_logic_vector(31 downto 0);
-begin
- k <= x"017D7840";
- s_halfWay <= unsigned(k);
-
- process(clkIn)
- begin
- if (rising_edge(clkIn)) then
- if (s_counter = s_halfWay - 1) then
- clkOut <= '0';
- s_counter <= (others => '0');
- else
- if (s_counter = s_halfWay/2 - 1) then
- clkOut <= '1';
- end if;
- s_counter <= s_counter + 1;
- end if;
- end if;
- end process;
-end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd.bak b/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd.bak
deleted file mode 100644
index c61efca..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd.bak
+++ /dev/null
@@ -1,10 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity RegN is
- generic ( N : positive := 8);
- port
- (
-
- );
-end RegN;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(0).cnf.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(0).cnf.cdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(5).cnf.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(5).cnf.cdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(6).cnf.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(6).cnf.cdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(6).cnf.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(6).cnf.hdb
deleted file mode 100644
index d244140..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.qmsg b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.qmsg
deleted file mode 100644
index 584d4fe..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680013329122 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680013329122 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 15:22:09 2023 " "Processing started: Tue Mar 28 15:22:09 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680013329122 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1680013329122 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1680013329122 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1680013329245 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1680013330690 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1680013330760 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680013330941 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 15:22:10 2023 " "Processing ended: Tue Mar 28 15:22:10 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680013330941 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680013330941 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680013330941 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1680013330941 ""}
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.rdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.rdb
deleted file mode 100644
index 89034e9..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm_labs.ddb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm_labs.ddb
deleted file mode 100644
index 316fa44..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm_labs.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cbx.xml b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cbx.xml
deleted file mode 100644
index 42e8b07..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.bpm b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.bpm
deleted file mode 100644
index 31adcc4..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.bpm and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.cdb
deleted file mode 100644
index 3143b68..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.hdb
deleted file mode 100644
index 95ab5f2..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.idb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.idb
deleted file mode 100644
index af2ff91..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.idb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.logdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.logdb
deleted file mode 100644
index 37ebf4d..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.logdb
+++ /dev/null
@@ -1,79 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;37;37;0;0;37;37;0;0;0;0;0;0;17;0;0;0;20;17;0;20;0;0;17;0;37;37;37;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,37;0;0;37;37;0;0;37;37;37;37;37;37;20;37;37;37;17;20;37;17;37;37;20;37;0;0;0;37;37,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,LEDR[16],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[15],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[14],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[13],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[12],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[11],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[10],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[16],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[15],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[14],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[13],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[12],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[11],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[10],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SW[17],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CLOCK_50,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.rdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.rdb
deleted file mode 100644
index ca80e8a..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp_merge.kpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp_merge.kpt
deleted file mode 100644
index ef704dd..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index d9c61ce..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
deleted file mode 100644
index 218eca7..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
deleted file mode 100644
index 41ec2ec..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.db_info b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.db_info
deleted file mode 100644
index d051e94..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Tue Mar 28 15:21:18 2023
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.eda.qmsg b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.eda.qmsg
deleted file mode 100644
index ff64f95..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680013333031 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680013333031 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 15:22:12 2023 " "Processing started: Tue Mar 28 15:22:12 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680013333031 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1680013333031 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1680013333031 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1680013333182 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "AccN_Demo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/ simulation " "Generated file AccN_Demo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1680013333223 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680013333233 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 15:22:13 2023 " "Processing ended: Tue Mar 28 15:22:13 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680013333233 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680013333233 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680013333233 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1680013333233 ""}
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.fit.qmsg b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.fit.qmsg
deleted file mode 100644
index 7c83203..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.fit.qmsg
+++ /dev/null
@@ -1,48 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1680013320041 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1680013320041 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "AccN_Demo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"AccN_Demo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1680013320044 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1680013320084 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1680013320084 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1680013320315 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1680013320319 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1680013320377 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 785 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1680013320381 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 787 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1680013320381 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 789 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1680013320381 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 791 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1680013320381 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 793 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1680013320381 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1680013320381 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1680013320383 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AccN_Demo.sdc " "Synopsys Design Constraints File file not found: 'AccN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1680013320917 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1680013320917 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1680013320919 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1680013320919 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1680013320920 ""}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1680013320929 ""} } { { "AccN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { { 312 128 296 328 "CLOCK_50" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 780 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1680013320929 ""}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "FreqDivider:inst2\|clkOut " "Automatically promoted node FreqDivider:inst2\|clkOut " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1680013320929 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "FreqDivider:inst2\|clkOut~4 " "Destination node FreqDivider:inst2\|clkOut~4" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 7 -1 0 } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 668 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1680013320929 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1680013320929 ""} } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 7 -1 0 } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1680013320929 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1680013321052 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1680013321052 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1680013321053 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1680013321053 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1680013321053 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1680013321054 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1680013321054 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1680013321054 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1680013321055 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1680013321055 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1680013321055 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1680013321087 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680013321094 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1680013321099 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1680013322456 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680013322532 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1680013322566 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1680013325163 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680013325164 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1680013325288 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X104_Y37 X115_Y48 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48"} { { 12 { 0 ""} 104 37 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1680013327218 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1680013327218 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1680013327645 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1680013327645 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680013327646 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.07 " "Total time spent on timing analysis during the Fitter is 0.07 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1680013327723 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1680013327729 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1680013327885 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1680013327885 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1680013328010 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680013328248 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1680013328423 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1680013328462 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 488 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 488 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1160 " "Peak virtual memory: 1160 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680013328595 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 15:22:08 2023 " "Processing ended: Tue Mar 28 15:22:08 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680013328595 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680013328595 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680013328595 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1680013328595 ""}
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.hier_info b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.hier_info
deleted file mode 100644
index 4d1cedc..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.hier_info
+++ /dev/null
@@ -1,259 +0,0 @@
-|AccN_Demo
-LEDR[0] <= AccN:inst.dataOut[0]
-LEDR[1] <= AccN:inst.dataOut[1]
-LEDR[2] <= AccN:inst.dataOut[2]
-LEDR[3] <= AccN:inst.dataOut[3]
-LEDR[4] <= AccN:inst.dataOut[4]
-LEDR[5] <= AccN:inst.dataOut[5]
-LEDR[6] <= AccN:inst.dataOut[6]
-LEDR[7] <= AccN:inst.dataOut[7]
-LEDR[8] <= AccN:inst.dataOut[8]
-LEDR[9] <= AccN:inst.dataOut[9]
-LEDR[10] <= AccN:inst.dataOut[10]
-LEDR[11] <= AccN:inst.dataOut[11]
-LEDR[12] <= AccN:inst.dataOut[12]
-LEDR[13] <= AccN:inst.dataOut[13]
-LEDR[14] <= AccN:inst.dataOut[14]
-LEDR[15] <= AccN:inst.dataOut[15]
-LEDR[16] <= AccN:inst.dataOut[16]
-KEY[1] => inst1.IN0
-SW[0] => AccN:inst.dataIn[0]
-SW[1] => AccN:inst.dataIn[1]
-SW[2] => AccN:inst.dataIn[2]
-SW[3] => AccN:inst.dataIn[3]
-SW[4] => AccN:inst.dataIn[4]
-SW[5] => AccN:inst.dataIn[5]
-SW[6] => AccN:inst.dataIn[6]
-SW[7] => AccN:inst.dataIn[7]
-SW[8] => AccN:inst.dataIn[8]
-SW[9] => AccN:inst.dataIn[9]
-SW[10] => AccN:inst.dataIn[10]
-SW[11] => AccN:inst.dataIn[11]
-SW[12] => AccN:inst.dataIn[12]
-SW[13] => AccN:inst.dataIn[13]
-SW[14] => AccN:inst.dataIn[14]
-SW[15] => AccN:inst.dataIn[15]
-SW[16] => AccN:inst.dataIn[16]
-SW[17] => AccN:inst.enable
-CLOCK_50 => FreqDivider:inst2.clkIn
-
-
-|AccN_Demo|AccN:inst
-dataIn[0] => addern:adder.operand1[0]
-dataIn[1] => addern:adder.operand1[1]
-dataIn[2] => addern:adder.operand1[2]
-dataIn[3] => addern:adder.operand1[3]
-dataIn[4] => addern:adder.operand1[4]
-dataIn[5] => addern:adder.operand1[5]
-dataIn[6] => addern:adder.operand1[6]
-dataIn[7] => addern:adder.operand1[7]
-dataIn[8] => addern:adder.operand1[8]
-dataIn[9] => addern:adder.operand1[9]
-dataIn[10] => addern:adder.operand1[10]
-dataIn[11] => addern:adder.operand1[11]
-dataIn[12] => addern:adder.operand1[12]
-dataIn[13] => addern:adder.operand1[13]
-dataIn[14] => addern:adder.operand1[14]
-dataIn[15] => addern:adder.operand1[15]
-dataIn[16] => addern:adder.operand1[16]
-reset => regn:reg.reset
-enable => regn:reg.enable
-clk => regn:reg.clk
-dataOut[0] <= regn:reg.dataOut[0]
-dataOut[1] <= regn:reg.dataOut[1]
-dataOut[2] <= regn:reg.dataOut[2]
-dataOut[3] <= regn:reg.dataOut[3]
-dataOut[4] <= regn:reg.dataOut[4]
-dataOut[5] <= regn:reg.dataOut[5]
-dataOut[6] <= regn:reg.dataOut[6]
-dataOut[7] <= regn:reg.dataOut[7]
-dataOut[8] <= regn:reg.dataOut[8]
-dataOut[9] <= regn:reg.dataOut[9]
-dataOut[10] <= regn:reg.dataOut[10]
-dataOut[11] <= regn:reg.dataOut[11]
-dataOut[12] <= regn:reg.dataOut[12]
-dataOut[13] <= regn:reg.dataOut[13]
-dataOut[14] <= regn:reg.dataOut[14]
-dataOut[15] <= regn:reg.dataOut[15]
-dataOut[16] <= regn:reg.dataOut[16]
-
-
-|AccN_Demo|AccN:inst|AdderN:adder
-operand1[0] => Add0.IN17
-operand1[1] => Add0.IN16
-operand1[2] => Add0.IN15
-operand1[3] => Add0.IN14
-operand1[4] => Add0.IN13
-operand1[5] => Add0.IN12
-operand1[6] => Add0.IN11
-operand1[7] => Add0.IN10
-operand1[8] => Add0.IN9
-operand1[9] => Add0.IN8
-operand1[10] => Add0.IN7
-operand1[11] => Add0.IN6
-operand1[12] => Add0.IN5
-operand1[13] => Add0.IN4
-operand1[14] => Add0.IN3
-operand1[15] => Add0.IN2
-operand1[16] => Add0.IN1
-operand2[0] => Add0.IN34
-operand2[1] => Add0.IN33
-operand2[2] => Add0.IN32
-operand2[3] => Add0.IN31
-operand2[4] => Add0.IN30
-operand2[5] => Add0.IN29
-operand2[6] => Add0.IN28
-operand2[7] => Add0.IN27
-operand2[8] => Add0.IN26
-operand2[9] => Add0.IN25
-operand2[10] => Add0.IN24
-operand2[11] => Add0.IN23
-operand2[12] => Add0.IN22
-operand2[13] => Add0.IN21
-operand2[14] => Add0.IN20
-operand2[15] => Add0.IN19
-operand2[16] => Add0.IN18
-result[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-result[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|AccN_Demo|AccN:inst|RegN:reg
-dataIn[0] => dataOut[0]~reg0.DATAIN
-dataIn[1] => dataOut[1]~reg0.DATAIN
-dataIn[2] => dataOut[2]~reg0.DATAIN
-dataIn[3] => dataOut[3]~reg0.DATAIN
-dataIn[4] => dataOut[4]~reg0.DATAIN
-dataIn[5] => dataOut[5]~reg0.DATAIN
-dataIn[6] => dataOut[6]~reg0.DATAIN
-dataIn[7] => dataOut[7]~reg0.DATAIN
-dataIn[8] => dataOut[8]~reg0.DATAIN
-dataIn[9] => dataOut[9]~reg0.DATAIN
-dataIn[10] => dataOut[10]~reg0.DATAIN
-dataIn[11] => dataOut[11]~reg0.DATAIN
-dataIn[12] => dataOut[12]~reg0.DATAIN
-dataIn[13] => dataOut[13]~reg0.DATAIN
-dataIn[14] => dataOut[14]~reg0.DATAIN
-dataIn[15] => dataOut[15]~reg0.DATAIN
-dataIn[16] => dataOut[16]~reg0.DATAIN
-enable => dataOut[16]~reg0.ENA
-enable => dataOut[15]~reg0.ENA
-enable => dataOut[14]~reg0.ENA
-enable => dataOut[13]~reg0.ENA
-enable => dataOut[12]~reg0.ENA
-enable => dataOut[11]~reg0.ENA
-enable => dataOut[10]~reg0.ENA
-enable => dataOut[9]~reg0.ENA
-enable => dataOut[8]~reg0.ENA
-enable => dataOut[7]~reg0.ENA
-enable => dataOut[6]~reg0.ENA
-enable => dataOut[5]~reg0.ENA
-enable => dataOut[4]~reg0.ENA
-enable => dataOut[3]~reg0.ENA
-enable => dataOut[2]~reg0.ENA
-enable => dataOut[1]~reg0.ENA
-enable => dataOut[0]~reg0.ENA
-reset => dataOut[0]~reg0.ACLR
-reset => dataOut[1]~reg0.ACLR
-reset => dataOut[2]~reg0.ACLR
-reset => dataOut[3]~reg0.ACLR
-reset => dataOut[4]~reg0.ACLR
-reset => dataOut[5]~reg0.ACLR
-reset => dataOut[6]~reg0.ACLR
-reset => dataOut[7]~reg0.ACLR
-reset => dataOut[8]~reg0.ACLR
-reset => dataOut[9]~reg0.ACLR
-reset => dataOut[10]~reg0.ACLR
-reset => dataOut[11]~reg0.ACLR
-reset => dataOut[12]~reg0.ACLR
-reset => dataOut[13]~reg0.ACLR
-reset => dataOut[14]~reg0.ACLR
-reset => dataOut[15]~reg0.ACLR
-reset => dataOut[16]~reg0.ACLR
-clk => dataOut[0]~reg0.CLK
-clk => dataOut[1]~reg0.CLK
-clk => dataOut[2]~reg0.CLK
-clk => dataOut[3]~reg0.CLK
-clk => dataOut[4]~reg0.CLK
-clk => dataOut[5]~reg0.CLK
-clk => dataOut[6]~reg0.CLK
-clk => dataOut[7]~reg0.CLK
-clk => dataOut[8]~reg0.CLK
-clk => dataOut[9]~reg0.CLK
-clk => dataOut[10]~reg0.CLK
-clk => dataOut[11]~reg0.CLK
-clk => dataOut[12]~reg0.CLK
-clk => dataOut[13]~reg0.CLK
-clk => dataOut[14]~reg0.CLK
-clk => dataOut[15]~reg0.CLK
-clk => dataOut[16]~reg0.CLK
-dataOut[0] <= dataOut[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[1] <= dataOut[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[2] <= dataOut[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[3] <= dataOut[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[4] <= dataOut[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[5] <= dataOut[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[6] <= dataOut[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[7] <= dataOut[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[8] <= dataOut[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[9] <= dataOut[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[10] <= dataOut[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[11] <= dataOut[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[12] <= dataOut[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[13] <= dataOut[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[14] <= dataOut[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[15] <= dataOut[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-dataOut[16] <= dataOut[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|AccN_Demo|FreqDivider:inst2
-clkIn => s_counter[0].CLK
-clkIn => s_counter[1].CLK
-clkIn => s_counter[2].CLK
-clkIn => s_counter[3].CLK
-clkIn => s_counter[4].CLK
-clkIn => s_counter[5].CLK
-clkIn => s_counter[6].CLK
-clkIn => s_counter[7].CLK
-clkIn => s_counter[8].CLK
-clkIn => s_counter[9].CLK
-clkIn => s_counter[10].CLK
-clkIn => s_counter[11].CLK
-clkIn => s_counter[12].CLK
-clkIn => s_counter[13].CLK
-clkIn => s_counter[14].CLK
-clkIn => s_counter[15].CLK
-clkIn => s_counter[16].CLK
-clkIn => s_counter[17].CLK
-clkIn => s_counter[18].CLK
-clkIn => s_counter[19].CLK
-clkIn => s_counter[20].CLK
-clkIn => s_counter[21].CLK
-clkIn => s_counter[22].CLK
-clkIn => s_counter[23].CLK
-clkIn => s_counter[24].CLK
-clkIn => s_counter[25].CLK
-clkIn => s_counter[26].CLK
-clkIn => s_counter[27].CLK
-clkIn => s_counter[28].CLK
-clkIn => s_counter[29].CLK
-clkIn => s_counter[30].CLK
-clkIn => s_counter[31].CLK
-clkIn => clkOut~reg0.CLK
-clkOut <= clkOut~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.hif b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.hif
deleted file mode 100644
index 9decd85..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.lpc.html b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.lpc.html
deleted file mode 100644
index eaaf98f..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.lpc.html
+++ /dev/null
@@ -1,82 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| inst2 |
-1 |
-0 |
-0 |
-0 |
-1 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
-| inst|reg |
-20 |
-0 |
-0 |
-0 |
-17 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
-| inst|adder |
-34 |
-0 |
-0 |
-0 |
-17 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
-| inst |
-20 |
-0 |
-0 |
-0 |
-17 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.lpc.rdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.lpc.rdb
deleted file mode 100644
index 6edee74..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.lpc.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.lpc.txt b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.lpc.txt
deleted file mode 100644
index 009caeb..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.lpc.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; inst2 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; inst|reg ; 20 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; inst|adder ; 34 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; inst ; 20 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.ammdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.ammdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.bpm b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.bpm
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index 6d9e8a6..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.cdb
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index 337f4dd..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.hdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.kpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.kpt
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index 92d0555..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.logdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.qmsg b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.qmsg
deleted file mode 100644
index 456acc1..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.qmsg
+++ /dev/null
@@ -1,19 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680013313781 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680013313781 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 15:21:53 2023 " "Processing started: Tue Mar 28 15:21:53 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680013313781 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013313781 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013313781 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1680013313918 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1680013313918 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FreqDivider.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FreqDivider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FreqDivider-Behavioral " "Found design unit 1: FreqDivider-Behavioral" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318577 ""} { "Info" "ISGN_ENTITY_NAME" "1 FreqDivider " "Found entity 1: FreqDivider" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318577 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318577 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AccN_Demo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file AccN_Demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 AccN_Demo " "Found entity 1: AccN_Demo" { } { { "AccN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318578 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AccN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AccN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AccN-Behavioral " "Found design unit 1: AccN-Behavioral" { } { { "AccN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} { "Info" "ISGN_ENTITY_NAME" "1 AccN " "Found entity 1: AccN" { } { { "AccN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318578 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RegN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file RegN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RegN-Behavioral " "Found design unit 1: RegN-Behavioral" { } { { "RegN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} { "Info" "ISGN_ENTITY_NAME" "1 RegN " "Found entity 1: RegN" { } { { "RegN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318578 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AdderN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AdderN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AdderN-Behavioral " "Found design unit 1: AdderN-Behavioral" { } { { "AdderN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} { "Info" "ISGN_ENTITY_NAME" "1 AdderN " "Found entity 1: AdderN" { } { { "AdderN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318578 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "AccN_Demo " "Elaborating entity \"AccN_Demo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1680013318605 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AccN AccN:inst " "Elaborating entity \"AccN\" for hierarchy \"AccN:inst\"" { } { { "AccN_Demo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { { 216 512 720 328 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013318607 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "AdderN AccN:inst\|AdderN:adder A:behavioral " "Elaborating entity \"AdderN\" using architecture \"A:behavioral\" for hierarchy \"AccN:inst\|AdderN:adder\"" { } { { "AccN.vhd" "adder" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 18 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013318608 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "RegN AccN:inst\|RegN:reg A:behavioral " "Elaborating entity \"RegN\" using architecture \"A:behavioral\" for hierarchy \"AccN:inst\|RegN:reg\"" { } { { "AccN.vhd" "reg" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 27 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013318608 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FreqDivider FreqDivider:inst2 " "Elaborating entity \"FreqDivider\" for hierarchy \"FreqDivider:inst2\"" { } { { "AccN_Demo.bdf" "inst2" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { { 288 304 448 368 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013318609 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1680013318992 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1680013319320 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013319320 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "112 " "Implemented 112 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "20 " "Implemented 20 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1680013319375 ""} { "Info" "ICUT_CUT_TM_OPINS" "17 " "Implemented 17 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1680013319375 ""} { "Info" "ICUT_CUT_TM_LCELLS" "75 " "Implemented 75 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1680013319375 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1680013319375 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "453 " "Peak virtual memory: 453 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680013319378 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 15:21:59 2023 " "Processing ended: Tue Mar 28 15:21:59 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680013319378 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680013319378 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680013319378 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013319378 ""}
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.rdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.rdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.cdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.hdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.logdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.pre_map.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.pre_map.hdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.quiproj.3500.rdr.flock b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.quiproj.3500.rdr.flock
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.root_partition.map.reg_db.cdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.routing.rdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.routing.rdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv_sg.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv_sg.cdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv_sg_swap.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv_sg_swap.cdb
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sld_design_entry.sci b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.smart_action.txt b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.smart_action.txt
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--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.qmsg b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.qmsg
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--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.qmsg
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-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680013331463 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680013331463 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 15:22:11 2023 " "Processing started: Tue Mar 28 15:22:11 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680013331463 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331463 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta AccN_Demo -c AccN_Demo " "Command: quartus_sta AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331463 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1680013331484 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1680013331541 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1680013331541 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331582 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331582 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AccN_Demo.sdc " "Synopsys Design Constraints File file not found: 'AccN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1680013331871 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331871 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name FreqDivider:inst2\|clkOut FreqDivider:inst2\|clkOut " "create_clock -period 1.000 -name FreqDivider:inst2\|clkOut FreqDivider:inst2\|clkOut" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1680013331871 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1680013331871 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331871 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331872 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331872 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1680013331873 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1680013331876 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1680013331883 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1680013331883 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.308 " "Worst-case setup slack is -4.308" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.308 -65.920 CLOCK_50 " " -4.308 -65.920 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.349 -16.351 FreqDivider:inst2\|clkOut " " -1.349 -16.351 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331883 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331883 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.543 " "Worst-case hold slack is 0.543" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331884 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331884 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.543 0.000 FreqDivider:inst2\|clkOut " " 0.543 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331884 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.653 0.000 CLOCK_50 " " 0.653 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331884 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331884 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013331885 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013331885 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -21.845 FreqDivider:inst2\|clkOut " " -1.285 -21.845 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331885 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331885 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1680013331901 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1680013331913 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1680013332202 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1680013332217 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1680013332219 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1680013332219 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.850 " "Worst-case setup slack is -3.850" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332220 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332220 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.850 -55.792 CLOCK_50 " " -3.850 -55.792 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332220 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.081 -12.785 FreqDivider:inst2\|clkOut " " -1.081 -12.785 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332220 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332220 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.489 " "Worst-case hold slack is 0.489" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332221 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332221 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.489 0.000 FreqDivider:inst2\|clkOut " " 0.489 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332221 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.598 0.000 CLOCK_50 " " 0.598 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332221 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332221 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013332223 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013332224 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -21.845 FreqDivider:inst2\|clkOut " " -1.285 -21.845 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332225 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332225 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1680013332250 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1680013332290 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1680013332290 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1680013332290 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.676 " "Worst-case setup slack is -1.676" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.676 -16.763 CLOCK_50 " " -1.676 -16.763 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.170 -0.504 FreqDivider:inst2\|clkOut " " -0.170 -0.504 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332292 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332292 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.244 " "Worst-case hold slack is 0.244" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.244 0.000 FreqDivider:inst2\|clkOut " " 0.244 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.297 0.000 CLOCK_50 " " 0.297 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332294 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332294 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013332295 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013332296 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -38.036 CLOCK_50 " " -3.000 -38.036 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -17.000 FreqDivider:inst2\|clkOut " " -1.000 -17.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332298 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332298 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1680013332526 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1680013332526 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "537 " "Peak virtual memory: 537 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680013332549 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 15:22:12 2023 " "Processing ended: Tue Mar 28 15:22:12 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680013332549 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680013332549 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680013332549 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1680013332549 ""}
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.rdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.rdb
deleted file mode 100644
index 24ed10f..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta_cmp.7_slow_1200mv_85c.tdb
deleted file mode 100644
index a4fd6d9..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta_cmp.7_slow_1200mv_85c.tdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tis_db_list.ddb
deleted file mode 100644
index 73e5ec9..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tis_db_list.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index 7c67389..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.fast_1200mv_0c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index 97a1442..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_0c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index 4060691..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tmw_info b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tmw_info
deleted file mode 100644
index 6862dd4..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tmw_info
+++ /dev/null
@@ -1,7 +0,0 @@
-start_full_compilation:s:00:00:20
-start_analysis_synthesis:s:00:00:06-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:09-start_full_compilation
-start_assembler:s:00:00:02-start_full_compilation
-start_timing_analyzer:s:00:00:02-start_full_compilation
-start_eda_netlist_writer:s:00:00:01-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.vpr.ammdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.vpr.ammdb
deleted file mode 100644
index eb44e27..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo_partition_pins.json b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo_partition_pins.json
deleted file mode 100644
index 826e05a..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo_partition_pins.json
+++ /dev/null
@@ -1,157 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "LEDR[16]",
- "strict" : false
- },
- {
- "name" : "LEDR[15]",
- "strict" : false
- },
- {
- "name" : "LEDR[14]",
- "strict" : false
- },
- {
- "name" : "LEDR[13]",
- "strict" : false
- },
- {
- "name" : "LEDR[12]",
- "strict" : false
- },
- {
- "name" : "LEDR[11]",
- "strict" : false
- },
- {
- "name" : "LEDR[10]",
- "strict" : false
- },
- {
- "name" : "LEDR[9]",
- "strict" : false
- },
- {
- "name" : "LEDR[8]",
- "strict" : false
- },
- {
- "name" : "LEDR[7]",
- "strict" : false
- },
- {
- "name" : "LEDR[6]",
- "strict" : false
- },
- {
- "name" : "LEDR[5]",
- "strict" : false
- },
- {
- "name" : "LEDR[4]",
- "strict" : false
- },
- {
- "name" : "LEDR[3]",
- "strict" : false
- },
- {
- "name" : "LEDR[2]",
- "strict" : false
- },
- {
- "name" : "LEDR[1]",
- "strict" : false
- },
- {
- "name" : "LEDR[0]",
- "strict" : false
- },
- {
- "name" : "SW[16]",
- "strict" : false
- },
- {
- "name" : "SW[15]",
- "strict" : false
- },
- {
- "name" : "SW[14]",
- "strict" : false
- },
- {
- "name" : "SW[13]",
- "strict" : false
- },
- {
- "name" : "SW[12]",
- "strict" : false
- },
- {
- "name" : "SW[11]",
- "strict" : false
- },
- {
- "name" : "SW[10]",
- "strict" : false
- },
- {
- "name" : "SW[9]",
- "strict" : false
- },
- {
- "name" : "SW[8]",
- "strict" : false
- },
- {
- "name" : "SW[7]",
- "strict" : false
- },
- {
- "name" : "SW[6]",
- "strict" : false
- },
- {
- "name" : "SW[5]",
- "strict" : false
- },
- {
- "name" : "SW[4]",
- "strict" : false
- },
- {
- "name" : "SW[3]",
- "strict" : false
- },
- {
- "name" : "SW[2]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- },
- {
- "name" : "KEY[1]",
- "strict" : false
- },
- {
- "name" : "SW[17]",
- "strict" : false
- },
- {
- "name" : "CLOCK_50",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/prev_cmp_AccN_Demo.qmsg b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/prev_cmp_AccN_Demo.qmsg
deleted file mode 100644
index 8797897..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/prev_cmp_AccN_Demo.qmsg
+++ /dev/null
@@ -1,4 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679489430378 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus Prime " "Running Quartus Prime Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679489430378 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 12:50:30 2023 " "Processing started: Wed Mar 22 12:50:30 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679489430378 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1679489430378 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd " "Command: quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1679489430378 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus Prime " "Quartus Prime Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "693 " "Peak virtual memory: 693 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679489430699 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 12:50:30 2023 " "Processing ended: Wed Mar 22 12:50:30 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679489430699 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679489430699 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679489430699 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1679489430699 ""}
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/README b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.db_info b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.db_info
deleted file mode 100644
index e1d34e6..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Wed Mar 22 10:58:18 2023
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.ammdb
deleted file mode 100644
index 2bce3d4..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.cdb
deleted file mode 100644
index f2a311a..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.dfp and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.hdb
deleted file mode 100644
index 09f6e7a..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.rcfdb
deleted file mode 100644
index edd8a3e..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.rcfdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.cdb
deleted file mode 100644
index b207d3b..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.dpi
deleted file mode 100644
index 9f96a0f..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.dpi and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.cdb
deleted file mode 100644
index 6925e92..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.cdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.hdb
deleted file mode 100644
index 4d61c86..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hdb
deleted file mode 100644
index d60bc8e..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.kpt
deleted file mode 100644
index 2c5cc71..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.rrp.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.rrp.hdb
deleted file mode 100644
index 58bb8d8..0000000
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.asm.rpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.asm.rpt
deleted file mode 100644
index 67906fc..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for AccN_Demo
-Tue Mar 28 15:22:10 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: AccN_Demo.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Tue Mar 28 15:22:10 2023 ;
-; Revision Name ; AccN_Demo ;
-; Top-level Entity Name ; AccN_Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+----------------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+----------------------------------------------------------------------------------------------------+
-; File Name ;
-+----------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sof ;
-+----------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------+
-; Assembler Device Options: AccN_Demo.sof ;
-+----------------+------------------------+
-; Option ; Setting ;
-+----------------+------------------------+
-; JTAG usercode ; 0x0056E597 ;
-; Checksum ; 0x0056E597 ;
-+----------------+------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 28 15:22:09 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 367 megabytes
- Info: Processing ended: Tue Mar 28 15:22:10 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.cdf b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.cdf
deleted file mode 100644
index aedc5ef..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.cdf
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition */
-JedecChain;
- FileRevision(JESD32A);
- DefaultMfr(6E);
-
- P ActionCode(Cfg)
- Device PartName(EP4CE115F29) Path("/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/") File("AccN_Demo.sof") MfrSpec(OpMask(1));
-
-ChainEnd;
-
-AlteraBegin;
- ChainType(JTAG);
-AlteraEnd;
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.done b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.done
deleted file mode 100644
index e94abf6..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.done
+++ /dev/null
@@ -1 +0,0 @@
-Tue Mar 28 15:22:13 2023
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.eda.rpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.eda.rpt
deleted file mode 100644
index d5c4514..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.eda.rpt
+++ /dev/null
@@ -1,94 +0,0 @@
-EDA Netlist Writer report for AccN_Demo
-Tue Mar 28 15:22:13 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Tue Mar 28 15:22:13 2023 ;
-; Revision Name ; AccN_Demo ;
-; Top-level Entity Name ; AccN_Demo ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+-----------------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+-----------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo.vho ;
-+-----------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 28 15:22:12 2023
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file AccN_Demo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 612 megabytes
- Info: Processing ended: Tue Mar 28 15:22:13 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.rpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.rpt
deleted file mode 100644
index 8b4c794..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.rpt
+++ /dev/null
@@ -1,2795 +0,0 @@
-Fitter report for AccN_Demo
-Tue Mar 28 15:22:08 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Control Signals
- 22. Global & Other Fast Signals
- 23. Routing Usage Summary
- 24. LAB Logic Elements
- 25. LAB-wide Signals
- 26. LAB Signals Sourced
- 27. LAB Signals Sourced Out
- 28. LAB Distinct Inputs
- 29. I/O Rules Summary
- 30. I/O Rules Details
- 31. I/O Rules Matrix
- 32. Fitter Device Options
- 33. Operating Settings and Conditions
- 34. Estimated Delay Added for Hold Timing Summary
- 35. Estimated Delay Added for Hold Timing Details
- 36. Fitter Messages
- 37. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Tue Mar 28 15:22:08 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; AccN_Demo ;
-; Top-level Entity Name ; AccN_Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 76 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 75 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 50 / 114,480 ( < 1 % ) ;
-; Total registers ; 50 ;
-; Total pins ; 37 / 529 ( 7 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.2% ;
-; Processors 3-4 ; 0.2% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
-; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
-; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
-; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
-; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
-; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
-; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[0] ; PIN_M23 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[0] ; PIN_E21 ; QSF Assignment ;
-; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
-; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
-; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 212 ) ; 0.00 % ( 0 / 212 ) ; 0.00 % ( 0 / 212 ) ;
-; -- Achieved ; 0.00 % ( 0 / 212 ) ; 0.00 % ( 0 / 212 ) ; 0.00 % ( 0 / 212 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+--------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 202 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.pin.
-
-
-+----------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+------------------------+
-; Total logic elements ; 76 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 26 ;
-; -- Register only ; 1 ;
-; -- Combinational with a register ; 49 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 15 ;
-; -- 3 input functions ; 27 ;
-; -- <=2 input functions ; 33 ;
-; -- Register only ; 1 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 28 ;
-; -- arithmetic mode ; 47 ;
-; ; ;
-; Total registers* ; 50 / 117,053 ( < 1 % ) ;
-; -- Dedicated logic registers ; 50 / 114,480 ( < 1 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 6 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 37 / 529 ( 7 % ) ;
-; -- Clock pins ; 1 / 7 ( 14 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 2 ;
-; -- Global clocks ; 2 / 20 ( 10 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ;
-; Peak interconnect usage (total/H/V) ; 1.2% / 0.9% / 1.7% ;
-; Maximum fan-out ; 33 ;
-; Highest non-global fan-out ; 17 ;
-; Total fan-out ; 401 ;
-; Average fan-out ; 1.90 ;
-+---------------------------------------------+------------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 76 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 26 ; 0 ;
-; -- Register only ; 1 ; 0 ;
-; -- Combinational with a register ; 49 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 15 ; 0 ;
-; -- 3 input functions ; 27 ; 0 ;
-; -- <=2 input functions ; 33 ; 0 ;
-; -- Register only ; 1 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 28 ; 0 ;
-; -- arithmetic mode ; 47 ; 0 ;
-; ; ; ;
-; Total registers ; 50 ; 0 ;
-; -- Dedicated logic registers ; 50 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 6 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 37 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; Clock control block ; 2 / 24 ( 8 % ) ; 0 / 24 ( 0 % ) ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 396 ; 5 ;
-; -- Registered Connections ; 113 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 20 ; 0 ;
-; -- Output Ports ; 17 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+-----------------------+--------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; CLOCK_50 ; Y2 ; 2 ; 0 ; 36 ; 14 ; 33 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; KEY[1] ; M21 ; 6 ; 115 ; 53 ; 14 ; 17 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[10] ; AC24 ; 5 ; 115 ; 4 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[11] ; AB24 ; 5 ; 115 ; 5 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[12] ; AB23 ; 5 ; 115 ; 7 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[13] ; AA24 ; 5 ; 115 ; 9 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[14] ; AA23 ; 5 ; 115 ; 10 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[15] ; AA22 ; 5 ; 115 ; 6 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[16] ; Y24 ; 5 ; 115 ; 13 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[17] ; Y23 ; 5 ; 115 ; 14 ; 7 ; 17 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[3] ; AD27 ; 5 ; 115 ; 13 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[4] ; AB27 ; 5 ; 115 ; 18 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[5] ; AC26 ; 5 ; 115 ; 11 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[6] ; AD26 ; 5 ; 115 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[7] ; AB26 ; 5 ; 115 ; 15 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[8] ; AC25 ; 5 ; 115 ; 4 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[9] ; AB25 ; 5 ; 115 ; 16 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[10] ; J15 ; 7 ; 60 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[11] ; H16 ; 7 ; 65 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[12] ; J16 ; 7 ; 65 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[13] ; H17 ; 7 ; 67 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[14] ; F15 ; 7 ; 58 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[15] ; G15 ; 7 ; 65 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[16] ; G16 ; 7 ; 67 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[2] ; E19 ; 7 ; 94 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[3] ; F21 ; 7 ; 107 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[4] ; F18 ; 7 ; 87 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[5] ; E18 ; 7 ; 87 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[6] ; J19 ; 7 ; 72 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[7] ; H19 ; 7 ; 72 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[8] ; J17 ; 7 ; 69 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[9] ; G17 ; 7 ; 83 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 1 / 63 ( 2 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 18 / 65 ( 28 % ) ; 2.5V ; -- ;
-; 6 ; 2 / 58 ( 3 % ) ; 2.5V ; -- ;
-; 7 ; 17 / 72 ( 24 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; SW[15] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA23 ; 280 ; 5 ; SW[14] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA24 ; 279 ; 5 ; SW[13] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; SW[12] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB24 ; 274 ; 5 ; SW[11] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB25 ; 292 ; 5 ; SW[9] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB26 ; 291 ; 5 ; SW[7] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB27 ; 296 ; 5 ; SW[4] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; SW[10] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC25 ; 272 ; 5 ; SW[8] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC26 ; 282 ; 5 ; SW[5] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; SW[6] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD27 ; 286 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 427 ; 7 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E19 ; 421 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; LEDR[14] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; LEDR[15] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G16 ; 453 ; 7 ; LEDR[16] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G17 ; 437 ; 7 ; LEDR[9] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G18 ; 452 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; LEDR[11] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; H17 ; 454 ; 7 ; LEDR[13] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; LEDR[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; LEDR[10] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; J16 ; 458 ; 7 ; LEDR[12] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; J17 ; 450 ; 7 ; LEDR[8] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; KEY[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; CLOCK_50 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; SW[17] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y24 ; 287 ; 5 ; SW[16] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; LEDR[16] ; Incomplete set of assignments ;
-; LEDR[15] ; Incomplete set of assignments ;
-; LEDR[14] ; Incomplete set of assignments ;
-; LEDR[13] ; Incomplete set of assignments ;
-; LEDR[12] ; Incomplete set of assignments ;
-; LEDR[11] ; Incomplete set of assignments ;
-; LEDR[10] ; Incomplete set of assignments ;
-; LEDR[9] ; Incomplete set of assignments ;
-; LEDR[8] ; Incomplete set of assignments ;
-; LEDR[7] ; Incomplete set of assignments ;
-; LEDR[6] ; Incomplete set of assignments ;
-; LEDR[5] ; Incomplete set of assignments ;
-; LEDR[4] ; Incomplete set of assignments ;
-; LEDR[3] ; Incomplete set of assignments ;
-; LEDR[2] ; Incomplete set of assignments ;
-; LEDR[1] ; Incomplete set of assignments ;
-; LEDR[0] ; Incomplete set of assignments ;
-; SW[16] ; Incomplete set of assignments ;
-; SW[15] ; Incomplete set of assignments ;
-; SW[14] ; Incomplete set of assignments ;
-; SW[13] ; Incomplete set of assignments ;
-; SW[12] ; Incomplete set of assignments ;
-; SW[11] ; Incomplete set of assignments ;
-; SW[10] ; Incomplete set of assignments ;
-; SW[9] ; Incomplete set of assignments ;
-; SW[8] ; Incomplete set of assignments ;
-; SW[7] ; Incomplete set of assignments ;
-; SW[6] ; Incomplete set of assignments ;
-; SW[5] ; Incomplete set of assignments ;
-; SW[4] ; Incomplete set of assignments ;
-; SW[3] ; Incomplete set of assignments ;
-; SW[2] ; Incomplete set of assignments ;
-; SW[1] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-; KEY[1] ; Incomplete set of assignments ;
-; SW[17] ; Incomplete set of assignments ;
-; CLOCK_50 ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------+-------------+--------------+
-; |AccN_Demo ; 76 (0) ; 50 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 37 ; 0 ; 26 (0) ; 1 (0) ; 49 (0) ; |AccN_Demo ; AccN_Demo ; work ;
-; |AccN:inst| ; 17 (0) ; 17 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 17 (0) ; |AccN_Demo|AccN:inst ; AccN ; work ;
-; |RegN:reg| ; 17 (17) ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 17 (17) ; |AccN_Demo|AccN:inst|RegN:reg ; RegN ; work ;
-; |FreqDivider:inst2| ; 59 (59) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 (26) ; 1 (1) ; 32 (32) ; |AccN_Demo|FreqDivider:inst2 ; FreqDivider ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+----------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+----------+----------+---------------+---------------+-----------------------+-----+------+
-; LEDR[16] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[15] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[14] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[13] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[12] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[11] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[10] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[16] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[15] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[14] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[13] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[12] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[11] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[10] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[9] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[8] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[5] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[4] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; KEY[1] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[17] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; CLOCK_50 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
-+----------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+------------------------------------------+-------------------+---------+
-; SW[16] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[16]~49 ; 0 ; 6 ;
-; SW[15] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[15]~47 ; 0 ; 6 ;
-; SW[14] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[14]~45 ; 0 ; 6 ;
-; SW[13] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[13]~43 ; 0 ; 6 ;
-; SW[12] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[12]~41 ; 0 ; 6 ;
-; SW[11] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[11]~39 ; 0 ; 6 ;
-; SW[10] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[10]~37 ; 0 ; 6 ;
-; SW[9] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[9]~35 ; 1 ; 6 ;
-; SW[8] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[8]~33 ; 1 ; 6 ;
-; SW[7] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[7]~31 ; 0 ; 6 ;
-; SW[6] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[6]~29 ; 0 ; 6 ;
-; SW[5] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[5]~27 ; 1 ; 6 ;
-; SW[4] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[4]~25 ; 1 ; 6 ;
-; SW[3] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[3]~23 ; 1 ; 6 ;
-; SW[2] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[2]~21 ; 0 ; 6 ;
-; SW[1] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[1]~19 ; 0 ; 6 ;
-; SW[0] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[0]~17 ; 0 ; 6 ;
-; KEY[1] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[16] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[15] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[14] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[13] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[12] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[11] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[10] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[9] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[8] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[7] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[6] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[5] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[4] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[3] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[2] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[1] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[0] ; 1 ; 6 ;
-; SW[17] ; ; ;
-; - AccN:inst|RegN:reg|dataOut[16] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[15] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[14] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[13] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[12] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[11] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[10] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[9] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[8] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[7] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[6] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[5] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[4] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[3] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[2] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[1] ; 1 ; 6 ;
-; - AccN:inst|RegN:reg|dataOut[0] ; 1 ; 6 ;
-; CLOCK_50 ; ; ;
-+------------------------------------------+-------------------+---------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+--------------------------+----------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+--------------------------+----------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_Y2 ; 33 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ;
-; FreqDivider:inst2|clkOut ; FF_X56_Y71_N23 ; 17 ; Clock ; yes ; Global Clock ; GCLK12 ; -- ;
-; KEY[1] ; PIN_M21 ; 17 ; Async. clear ; no ; -- ; -- ; -- ;
-; SW[17] ; PIN_Y23 ; 17 ; Clock enable ; no ; -- ; -- ; -- ;
-+--------------------------+----------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals ;
-+--------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+--------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_Y2 ; 33 ; 0 ; Global Clock ; GCLK4 ; -- ;
-; FreqDivider:inst2|clkOut ; FF_X56_Y71_N23 ; 17 ; 9 ; Global Clock ; GCLK12 ; -- ;
-+--------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-
-
-+-------------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+-------------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+-------------------------+
-; Block interconnects ; 89 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 65 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 104 / 209,544 ( < 1 % ) ;
-; Direct links ; 29 / 342,891 ( < 1 % ) ;
-; Global clocks ; 2 / 20 ( 10 % ) ;
-; Local interconnects ; 61 / 119,088 ( < 1 % ) ;
-; R24 interconnects ; 40 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 92 / 289,782 ( < 1 % ) ;
-+-----------------------+-------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+---------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 12.67) ; Number of LABs (Total = 6) ;
-+---------------------------------------------+-----------------------------+
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-; 9 ; 1 ;
-; 10 ; 0 ;
-; 11 ; 1 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 3 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------------------------------+
-; LAB-wide Signals ;
-+------------------------------------+-----------------------------+
-; LAB-wide Signals (Average = 1.67) ; Number of LABs (Total = 6) ;
-+------------------------------------+-----------------------------+
-; 1 Async. clear ; 2 ;
-; 1 Clock ; 6 ;
-; 1 Clock enable ; 2 ;
-+------------------------------------+-----------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+----------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 20.83) ; Number of LABs (Total = 6) ;
-+----------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 2 ;
-; 17 ; 0 ;
-; 18 ; 1 ;
-; 19 ; 0 ;
-; 20 ; 0 ;
-; 21 ; 0 ;
-; 22 ; 1 ;
-; 23 ; 0 ;
-; 24 ; 0 ;
-; 25 ; 0 ;
-; 26 ; 1 ;
-; 27 ; 1 ;
-+----------------------------------------------+-----------------------------+
-
-
-+--------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+--------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 10.50) ; Number of LABs (Total = 6) ;
-+--------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 1 ;
-; 7 ; 0 ;
-; 8 ; 2 ;
-; 9 ; 1 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 2 ;
-+--------------------------------------------------+-----------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+----------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 12.33) ; Number of LABs (Total = 6) ;
-+----------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 1 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 1 ;
-; 12 ; 0 ;
-; 13 ; 1 ;
-; 14 ; 0 ;
-; 15 ; 1 ;
-; 16 ; 0 ;
-; 17 ; 0 ;
-; 18 ; 0 ;
-; 19 ; 0 ;
-; 20 ; 0 ;
-; 21 ; 1 ;
-+----------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 37 ; 37 ; 0 ; 0 ; 37 ; 37 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 20 ; 17 ; 0 ; 20 ; 0 ; 0 ; 17 ; 0 ; 37 ; 37 ; 37 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 37 ; 0 ; 0 ; 37 ; 37 ; 0 ; 0 ; 37 ; 37 ; 37 ; 37 ; 37 ; 37 ; 20 ; 37 ; 37 ; 37 ; 17 ; 20 ; 37 ; 17 ; 37 ; 37 ; 20 ; 37 ; 0 ; 0 ; 0 ; 37 ; 37 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; LEDR[16] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[15] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[14] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[13] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[12] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[11] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[10] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[9] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[16] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[15] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[14] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[13] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[12] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[11] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[10] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[9] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[17] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; CLOCK_50 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary ;
-+-----------------+----------------------+-------------------+
-; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-; CLOCK_50 ; CLOCK_50 ; 4.2 ;
-+-----------------+----------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
-
-
-+--------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details ;
-+---------------------------------+--------------------------+-------------------+
-; Source Register ; Destination Register ; Delay Added in ns ;
-+---------------------------------+--------------------------+-------------------+
-; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 4.173 ;
-; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; 1.574 ;
-; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; 1.574 ;
-+---------------------------------+--------------------------+-------------------+
-Note: This table only shows the top 33 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "AccN_Demo"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'AccN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
-Info (176353): Automatically promoted node FreqDivider:inst2|clkOut File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd Line: 7
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
- Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
- Info (176357): Destination node FreqDivider:inst2|clkOut~4 File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd Line: 7
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:03
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.07 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 488 warnings
- Info: Peak virtual memory: 1160 megabytes
- Info: Processing ended: Tue Mar 28 15:22:08 2023
- Info: Elapsed time: 00:00:09
- Info: Total CPU time (on all processors): 00:00:14
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.smsg b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.summary b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.summary
deleted file mode 100644
index 480ec20..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Tue Mar 28 15:22:08 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : AccN_Demo
-Top-level Entity Name : AccN_Demo
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 76 / 114,480 ( < 1 % )
- Total combinational functions : 75 / 114,480 ( < 1 % )
- Dedicated logic registers : 50 / 114,480 ( < 1 % )
-Total registers : 50
-Total pins : 37 / 529 ( 7 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.flow.rpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.flow.rpt
deleted file mode 100644
index 6a1c94a..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.flow.rpt
+++ /dev/null
@@ -1,136 +0,0 @@
-Flow report for AccN_Demo
-Tue Mar 28 15:22:13 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Tue Mar 28 15:22:13 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; AccN_Demo ;
-; Top-level Entity Name ; AccN_Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 76 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 75 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 50 / 114,480 ( < 1 % ) ;
-; Total registers ; 50 ;
-; Total pins ; 37 / 529 ( 7 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/28/2023 15:21:53 ;
-; Main task ; Compilation ;
-; Revision Name ; AccN_Demo ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 198516037997543.168001331303800 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 447 MB ; 00:00:13 ;
-; Fitter ; 00:00:09 ; 1.0 ; 1160 MB ; 00:00:14 ;
-; Assembler ; 00:00:01 ; 1.0 ; 367 MB ; 00:00:02 ;
-; Timing Analyzer ; 00:00:01 ; 1.0 ; 537 MB ; 00:00:01 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 612 MB ; 00:00:00 ;
-; Total ; 00:00:18 ; -- ; -- ; 00:00:30 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo
-quartus_fit --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo
-quartus_asm --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo
-quartus_sta AccN_Demo -c AccN_Demo
-quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo
-
-
-
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.jdi b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.jdi
deleted file mode 100644
index 724000a..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.rpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.rpt
deleted file mode 100644
index dddc5de..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.rpt
+++ /dev/null
@@ -1,348 +0,0 @@
-Analysis & Synthesis report for AccN_Demo
-Tue Mar 28 15:21:59 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Parameter Settings for User Entity Instance: AccN:inst
- 10. Parameter Settings for User Entity Instance: AccN:inst|AdderN:adder
- 11. Parameter Settings for User Entity Instance: AccN:inst|RegN:reg
- 12. Post-Synthesis Netlist Statistics for Top Partition
- 13. Elapsed Time Per Partition
- 14. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Tue Mar 28 15:21:59 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; AccN_Demo ;
-; Top-level Entity Name ; AccN_Demo ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 75 ;
-; Total combinational functions ; 75 ;
-; Dedicated logic registers ; 50 ;
-; Total registers ; 50 ;
-; Total pins ; 37 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; AccN_Demo ; AccN_Demo ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.0% ;
-; Processors 3-4 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------+---------+
-; FreqDivider.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd ; ;
-; AccN_Demo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf ; ;
-; AccN.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd ; ;
-; RegN.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd ; ;
-; AdderN.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd ; ;
-+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------+---------+
-
-
-+--------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+----------------+
-; Resource ; Usage ;
-+---------------------------------------------+----------------+
-; Estimated Total logic elements ; 75 ;
-; ; ;
-; Total combinational functions ; 75 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 15 ;
-; -- 3 input functions ; 27 ;
-; -- <=2 input functions ; 33 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 28 ;
-; -- arithmetic mode ; 47 ;
-; ; ;
-; Total registers ; 50 ;
-; -- Dedicated logic registers ; 50 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 37 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; CLOCK_50~input ;
-; Maximum fan-out ; 33 ;
-; Total fan-out ; 394 ;
-; Average fan-out ; 1.98 ;
-+---------------------------------------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+-------------+--------------+
-; |AccN_Demo ; 75 (0) ; 50 (0) ; 0 ; 0 ; 0 ; 0 ; 37 ; 0 ; |AccN_Demo ; AccN_Demo ; work ;
-; |AccN:inst| ; 17 (0) ; 17 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AccN_Demo|AccN:inst ; AccN ; work ;
-; |RegN:reg| ; 17 (17) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AccN_Demo|AccN:inst|RegN:reg ; RegN ; work ;
-; |FreqDivider:inst2| ; 58 (58) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AccN_Demo|FreqDivider:inst2 ; FreqDivider ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 50 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 17 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 17 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+--------------------------------------------------------+
-; Parameter Settings for User Entity Instance: AccN:inst ;
-+----------------+-------+-------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+-------------------------------+
-; n ; 17 ; Signed Integer ;
-+----------------+-------+-------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: AccN:inst|AdderN:adder ;
-+----------------+-------+--------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+--------------------------------------------+
-; n ; 17 ; Signed Integer ;
-+----------------+-------+--------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: AccN:inst|RegN:reg ;
-+----------------+-------+----------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+----------------------------------------+
-; n ; 17 ; Signed Integer ;
-+----------------+-------+----------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 37 ;
-; cycloneiii_ff ; 50 ;
-; ENA CLR ; 17 ;
-; plain ; 33 ;
-; cycloneiii_lcell_comb ; 75 ;
-; arith ; 47 ;
-; 2 data inputs ; 31 ;
-; 3 data inputs ; 16 ;
-; normal ; 28 ;
-; 1 data inputs ; 1 ;
-; 2 data inputs ; 1 ;
-; 3 data inputs ; 11 ;
-; 4 data inputs ; 15 ;
-; ; ;
-; Max LUT depth ; 4.50 ;
-; Average LUT depth ; 3.02 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 28 15:21:53 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 2 design units, including 1 entities, in source file FreqDivider.vhd
- Info (12022): Found design unit 1: FreqDivider-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd Line: 11
- Info (12023): Found entity 1: FreqDivider File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd Line: 5
-Info (12021): Found 1 design units, including 1 entities, in source file AccN_Demo.bdf
- Info (12023): Found entity 1: AccN_Demo
-Info (12021): Found 2 design units, including 1 entities, in source file AccN.vhd
- Info (12022): Found design unit 1: AccN-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd Line: 13
- Info (12023): Found entity 1: AccN File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd Line: 4
-Info (12021): Found 2 design units, including 1 entities, in source file RegN.vhd
- Info (12022): Found design unit 1: RegN-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd Line: 14
- Info (12023): Found entity 1: RegN File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd Line: 4
-Info (12021): Found 2 design units, including 1 entities, in source file AdderN.vhd
- Info (12022): Found design unit 1: AdderN-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd Line: 15
- Info (12023): Found entity 1: AdderN File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd Line: 5
-Info (12127): Elaborating entity "AccN_Demo" for the top level hierarchy
-Info (12128): Elaborating entity "AccN" for hierarchy "AccN:inst"
-Info (12129): Elaborating entity "AdderN" using architecture "A:behavioral" for hierarchy "AccN:inst|AdderN:adder" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd Line: 18
-Info (12129): Elaborating entity "RegN" using architecture "A:behavioral" for hierarchy "AccN:inst|RegN:reg" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd Line: 27
-Info (12128): Elaborating entity "FreqDivider" for hierarchy "FreqDivider:inst2"
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 112 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 20 input pins
- Info (21059): Implemented 17 output pins
- Info (21061): Implemented 75 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 453 megabytes
- Info: Processing ended: Tue Mar 28 15:21:59 2023
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:13
-
-
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.summary b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.summary
deleted file mode 100644
index af4a45a..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Tue Mar 28 15:21:59 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : AccN_Demo
-Top-level Entity Name : AccN_Demo
-Family : Cyclone IV E
-Total logic elements : 75
- Total combinational functions : 75
- Dedicated logic registers : 50
-Total registers : 50
-Total pins : 37
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.pin b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.pin
deleted file mode 100644
index bbdc987..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "AccN_Demo" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-SW[15] : AA22 : input : 2.5 V : : 5 : Y
-SW[14] : AA23 : input : 2.5 V : : 5 : Y
-SW[13] : AA24 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-SW[12] : AB23 : input : 2.5 V : : 5 : Y
-SW[11] : AB24 : input : 2.5 V : : 5 : Y
-SW[9] : AB25 : input : 2.5 V : : 5 : Y
-SW[7] : AB26 : input : 2.5 V : : 5 : Y
-SW[4] : AB27 : input : 2.5 V : : 5 : Y
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-SW[10] : AC24 : input : 2.5 V : : 5 : Y
-SW[8] : AC25 : input : 2.5 V : : 5 : Y
-SW[5] : AC26 : input : 2.5 V : : 5 : Y
-SW[2] : AC27 : input : 2.5 V : : 5 : Y
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-SW[6] : AD26 : input : 2.5 V : : 5 : Y
-SW[3] : AD27 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
-LEDR[5] : E18 : output : 2.5 V : : 7 : Y
-LEDR[2] : E19 : output : 2.5 V : : 7 : Y
-VCCIO7 : E20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
-VCCIO7 : E23 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-LEDR[14] : F15 : output : 2.5 V : : 7 : Y
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-LEDR[4] : F18 : output : 2.5 V : : 7 : Y
-LEDR[1] : F19 : output : 2.5 V : : 7 : Y
-GND : F20 : gnd : : : :
-LEDR[3] : F21 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-LEDR[15] : G15 : output : 2.5 V : : 7 : Y
-LEDR[16] : G16 : output : 2.5 V : : 7 : Y
-LEDR[9] : G17 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
-LEDR[0] : G19 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-LEDR[11] : H16 : output : 2.5 V : : 7 : Y
-LEDR[13] : H17 : output : 2.5 V : : 7 : Y
-VCCIO7 : H18 : power : : 2.5V : 7 :
-LEDR[7] : H19 : output : 2.5 V : : 7 : Y
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-LEDR[10] : J15 : output : 2.5 V : : 7 : Y
-LEDR[12] : J16 : output : 2.5 V : : 7 : Y
-LEDR[8] : J17 : output : 2.5 V : : 7 : Y
-GND : J18 : gnd : : : :
-LEDR[6] : J19 : output : 2.5 V : : 7 : Y
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-KEY[1] : M21 : input : 2.5 V : : 6 : Y
-MSEL2 : M22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-CLOCK_50 : Y2 : input : 2.5 V : : 2 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-SW[17] : Y23 : input : 2.5 V : : 5 : Y
-SW[16] : Y24 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sld b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sof b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sof
index 100e4ae..3e0278d 100644
Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sof and b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sof differ
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.rpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.rpt
deleted file mode 100644
index 1efe068..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.rpt
+++ /dev/null
@@ -1,2006 +0,0 @@
-Timing Analyzer report for AccN_Demo
-Tue Mar 28 15:22:12 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Setup: 'CLOCK_50'
- 13. Slow 1200mV 85C Model Setup: 'FreqDivider:inst2|clkOut'
- 14. Slow 1200mV 85C Model Hold: 'FreqDivider:inst2|clkOut'
- 15. Slow 1200mV 85C Model Hold: 'CLOCK_50'
- 16. Slow 1200mV 85C Model Metastability Summary
- 17. Slow 1200mV 0C Model Fmax Summary
- 18. Slow 1200mV 0C Model Setup Summary
- 19. Slow 1200mV 0C Model Hold Summary
- 20. Slow 1200mV 0C Model Recovery Summary
- 21. Slow 1200mV 0C Model Removal Summary
- 22. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 23. Slow 1200mV 0C Model Setup: 'CLOCK_50'
- 24. Slow 1200mV 0C Model Setup: 'FreqDivider:inst2|clkOut'
- 25. Slow 1200mV 0C Model Hold: 'FreqDivider:inst2|clkOut'
- 26. Slow 1200mV 0C Model Hold: 'CLOCK_50'
- 27. Slow 1200mV 0C Model Metastability Summary
- 28. Fast 1200mV 0C Model Setup Summary
- 29. Fast 1200mV 0C Model Hold Summary
- 30. Fast 1200mV 0C Model Recovery Summary
- 31. Fast 1200mV 0C Model Removal Summary
- 32. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 33. Fast 1200mV 0C Model Setup: 'CLOCK_50'
- 34. Fast 1200mV 0C Model Setup: 'FreqDivider:inst2|clkOut'
- 35. Fast 1200mV 0C Model Hold: 'FreqDivider:inst2|clkOut'
- 36. Fast 1200mV 0C Model Hold: 'CLOCK_50'
- 37. Fast 1200mV 0C Model Metastability Summary
- 38. Multicorner Timing Analysis Summary
- 39. Board Trace Model Assignments
- 40. Input Transition Times
- 41. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 42. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 43. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 44. Setup Transfers
- 45. Hold Transfers
- 46. Report TCCS
- 47. Report RSKM
- 48. Unconstrained Paths Summary
- 49. Clock Status Summary
- 50. Unconstrained Input Ports
- 51. Unconstrained Output Ports
- 52. Unconstrained Input Ports
- 53. Unconstrained Output Ports
- 54. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; AccN_Demo ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.4% ;
-; Processors 3-4 ; 0.4% ;
-+----------------------------+-------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks ;
-+--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
-; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
-+--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
-; CLOCK_50 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;
-; FreqDivider:inst2|clkOut ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { FreqDivider:inst2|clkOut } ;
-+--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
-
-
-+----------------------------------------------------------------+
-; Slow 1200mV 85C Model Fmax Summary ;
-+------------+-----------------+--------------------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+--------------------------+------+
-; 188.39 MHz ; 188.39 MHz ; CLOCK_50 ; ;
-; 425.71 MHz ; 425.71 MHz ; FreqDivider:inst2|clkOut ; ;
-+------------+-----------------+--------------------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
-+---------------------------------------------------+
-; Slow 1200mV 85C Model Setup Summary ;
-+--------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+--------+---------------+
-; CLOCK_50 ; -4.308 ; -65.920 ;
-; FreqDivider:inst2|clkOut ; -1.349 ; -16.351 ;
-+--------------------------+--------+---------------+
-
-
-+--------------------------------------------------+
-; Slow 1200mV 85C Model Hold Summary ;
-+--------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+-------+---------------+
-; FreqDivider:inst2|clkOut ; 0.543 ; 0.000 ;
-; CLOCK_50 ; 0.653 ; 0.000 ;
-+--------------------------+-------+---------------+
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
-+--------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+--------+---------------+
-; CLOCK_50 ; -3.000 ; -45.405 ;
-; FreqDivider:inst2|clkOut ; -1.285 ; -21.845 ;
-+--------------------------+--------+---------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Setup: 'CLOCK_50' ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; -4.308 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 5.223 ;
-; -4.298 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 5.213 ;
-; -4.283 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 5.201 ;
-; -4.274 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 5.192 ;
-; -4.258 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 5.176 ;
-; -4.178 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 5.096 ;
-; -4.175 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 5.093 ;
-; -4.162 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 5.076 ;
-; -4.155 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 5.069 ;
-; -4.055 ; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 4.969 ;
-; -4.051 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.966 ;
-; -4.048 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 4.962 ;
-; -4.026 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.944 ;
-; -3.936 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.851 ;
-; -3.922 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.837 ;
-; -3.902 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 4.816 ;
-; -3.899 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.814 ;
-; -3.824 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.739 ;
-; -3.787 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.705 ;
-; -3.621 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.538 ;
-; -3.509 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.427 ;
-; -3.491 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.408 ;
-; -3.467 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.382 ;
-; -3.376 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.294 ;
-; -3.347 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.264 ;
-; -3.336 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.254 ;
-; -3.316 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.231 ;
-; -3.278 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.193 ;
-; -3.194 ; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.111 ;
-; -3.137 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.052 ;
-; -3.107 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.024 ;
-; -3.096 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.013 ;
-; -2.825 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.740 ;
-; -2.769 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.684 ;
-; -2.698 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.612 ;
-; -2.698 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.613 ;
-; -2.694 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.609 ;
-; -2.687 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.601 ;
-; -2.681 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.599 ;
-; -2.668 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.582 ;
-; -2.647 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.561 ;
-; -2.635 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.550 ;
-; -2.631 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.546 ;
-; -2.596 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.511 ;
-; -2.596 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.511 ;
-; -2.596 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.510 ;
-; -2.594 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.509 ;
-; -2.590 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.505 ;
-; -2.590 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.508 ;
-; -2.586 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.501 ;
-; -2.584 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.499 ;
-; -2.584 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.499 ;
-; -2.571 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.489 ;
-; -2.571 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.489 ;
-; -2.569 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.487 ;
-; -2.567 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.481 ;
-; -2.567 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.482 ;
-; -2.566 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.480 ;
-; -2.566 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.484 ;
-; -2.566 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.484 ;
-; -2.564 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.482 ;
-; -2.562 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.477 ;
-; -2.562 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.480 ;
-; -2.562 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.480 ;
-; -2.560 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.478 ;
-; -2.555 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.469 ;
-; -2.553 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.467 ;
-; -2.547 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.465 ;
-; -2.536 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.450 ;
-; -2.534 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.448 ;
-; -2.526 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.441 ;
-; -2.524 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.439 ;
-; -2.520 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.085 ; 3.433 ;
-; -2.520 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.434 ;
-; -2.503 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.418 ;
-; -2.499 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.414 ;
-; -2.479 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.397 ;
-; -2.479 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.397 ;
-; -2.477 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.395 ;
-; -2.466 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.384 ;
-; -2.466 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.384 ;
-; -2.465 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.379 ;
-; -2.464 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.382 ;
-; -2.464 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.378 ;
-; -2.459 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.377 ;
-; -2.456 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.371 ;
-; -2.453 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.368 ;
-; -2.450 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.364 ;
-; -2.450 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.364 ;
-; -2.448 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.362 ;
-; -2.443 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.357 ;
-; -2.443 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.357 ;
-; -2.442 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.357 ;
-; -2.441 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.355 ;
-; -2.436 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.350 ;
-; -2.435 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.349 ;
-; -2.434 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.348 ;
-; -2.431 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.346 ;
-; -2.423 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.337 ;
-; -2.421 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.335 ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Setup: 'FreqDivider:inst2|clkOut' ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; -1.349 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.679 ;
-; -1.260 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.590 ;
-; -1.250 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 2.150 ;
-; -1.229 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.559 ;
-; -1.217 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.547 ;
-; -1.214 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.544 ;
-; -1.198 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.528 ;
-; -1.160 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 2.060 ;
-; -1.130 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 2.030 ;
-; -1.128 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.458 ;
-; -1.127 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.457 ;
-; -1.118 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 2.018 ;
-; -1.117 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 2.017 ;
-; -1.113 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 2.031 ;
-; -1.101 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 2.019 ;
-; -1.099 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.999 ;
-; -1.097 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.427 ;
-; -1.097 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.427 ;
-; -1.085 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.415 ;
-; -1.082 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.412 ;
-; -1.082 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.412 ;
-; -1.082 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 2.000 ;
-; -1.066 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.396 ;
-; -1.063 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.393 ;
-; -1.029 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.929 ;
-; -1.028 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.928 ;
-; -1.012 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.930 ;
-; -0.999 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.899 ;
-; -0.998 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.898 ;
-; -0.996 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.326 ;
-; -0.995 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.325 ;
-; -0.995 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.325 ;
-; -0.986 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.886 ;
-; -0.985 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.885 ;
-; -0.985 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.885 ;
-; -0.981 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.899 ;
-; -0.981 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.899 ;
-; -0.969 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.887 ;
-; -0.967 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.867 ;
-; -0.966 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.866 ;
-; -0.966 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.884 ;
-; -0.965 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.295 ;
-; -0.965 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.295 ;
-; -0.965 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.295 ;
-; -0.953 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.283 ;
-; -0.950 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.280 ;
-; -0.950 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.280 ;
-; -0.950 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.868 ;
-; -0.949 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.279 ;
-; -0.947 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.865 ;
-; -0.934 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.264 ;
-; -0.931 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.261 ;
-; -0.931 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.261 ;
-; -0.898 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.798 ;
-; -0.897 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.797 ;
-; -0.896 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.796 ;
-; -0.880 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.798 ;
-; -0.879 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.797 ;
-; -0.867 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.767 ;
-; -0.867 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.767 ;
-; -0.866 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.766 ;
-; -0.864 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.194 ;
-; -0.863 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.193 ;
-; -0.863 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.193 ;
-; -0.862 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.192 ;
-; -0.857 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.757 ;
-; -0.854 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.754 ;
-; -0.853 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.753 ;
-; -0.853 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.753 ;
-; -0.849 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.767 ;
-; -0.849 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.767 ;
-; -0.849 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.767 ;
-; -0.837 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.755 ;
-; -0.835 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.735 ;
-; -0.834 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.734 ;
-; -0.834 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.752 ;
-; -0.834 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.734 ;
-; -0.834 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.752 ;
-; -0.833 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.163 ;
-; -0.833 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.163 ;
-; -0.833 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.163 ;
-; -0.832 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.162 ;
-; -0.821 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.151 ;
-; -0.818 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.148 ;
-; -0.818 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.148 ;
-; -0.818 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.736 ;
-; -0.817 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.147 ;
-; -0.815 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.733 ;
-; -0.815 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.733 ;
-; -0.802 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.132 ;
-; -0.799 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.129 ;
-; -0.799 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.129 ;
-; -0.798 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.128 ;
-; -0.772 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.672 ;
-; -0.766 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.666 ;
-; -0.765 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.665 ;
-; -0.764 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.664 ;
-; -0.748 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.666 ;
-; -0.747 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.665 ;
-; -0.747 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.665 ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Hold: 'FreqDivider:inst2|clkOut' ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; 0.543 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.239 ;
-; 0.563 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.259 ;
-; 0.639 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.923 ;
-; 0.639 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.923 ;
-; 0.640 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.924 ;
-; 0.640 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.924 ;
-; 0.641 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.925 ;
-; 0.641 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.925 ;
-; 0.643 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.927 ;
-; 0.644 ; AccN:inst|RegN:reg|dataOut[16] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.928 ;
-; 0.645 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.929 ;
-; 0.657 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.923 ;
-; 0.658 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.924 ;
-; 0.658 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.924 ;
-; 0.658 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.924 ;
-; 0.658 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.924 ;
-; 0.659 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.925 ;
-; 0.662 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.928 ;
-; 0.664 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.360 ;
-; 0.669 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.365 ;
-; 0.670 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.366 ;
-; 0.676 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[0] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.942 ;
-; 0.684 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.380 ;
-; 0.689 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.385 ;
-; 0.689 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.385 ;
-; 0.790 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.486 ;
-; 0.791 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.487 ;
-; 0.795 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.491 ;
-; 0.796 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.492 ;
-; 0.796 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.492 ;
-; 0.810 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.506 ;
-; 0.810 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.506 ;
-; 0.815 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.511 ;
-; 0.815 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.511 ;
-; 0.816 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.512 ;
-; 0.916 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.612 ;
-; 0.917 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.613 ;
-; 0.917 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.613 ;
-; 0.921 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.617 ;
-; 0.922 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.618 ;
-; 0.922 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.618 ;
-; 0.924 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.620 ;
-; 0.936 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.632 ;
-; 0.936 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.632 ;
-; 0.937 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.633 ;
-; 0.941 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.637 ;
-; 0.941 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.637 ;
-; 0.942 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.638 ;
-; 0.942 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.638 ;
-; 0.956 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.240 ;
-; 0.957 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.241 ;
-; 0.957 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.241 ;
-; 0.959 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.243 ;
-; 0.968 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.252 ;
-; 0.969 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.253 ;
-; 0.970 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.254 ;
-; 0.971 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.255 ;
-; 0.973 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.257 ;
-; 0.974 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.240 ;
-; 0.974 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.240 ;
-; 0.974 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.258 ;
-; 0.975 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.259 ;
-; 0.976 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.242 ;
-; 0.976 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.260 ;
-; 0.988 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.254 ;
-; 0.988 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.254 ;
-; 0.989 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.255 ;
-; 0.989 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.255 ;
-; 0.993 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.259 ;
-; 0.994 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.260 ;
-; 0.994 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.260 ;
-; 1.042 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.738 ;
-; 1.043 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.739 ;
-; 1.043 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.739 ;
-; 1.045 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.741 ;
-; 1.047 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.743 ;
-; 1.048 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.744 ;
-; 1.048 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.744 ;
-; 1.050 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.746 ;
-; 1.062 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.758 ;
-; 1.062 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.758 ;
-; 1.063 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.759 ;
-; 1.063 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.759 ;
-; 1.067 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.763 ;
-; 1.067 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.763 ;
-; 1.068 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.764 ;
-; 1.068 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.764 ;
-; 1.077 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.361 ;
-; 1.078 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.362 ;
-; 1.078 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.362 ;
-; 1.082 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.366 ;
-; 1.083 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.367 ;
-; 1.083 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.367 ;
-; 1.095 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.379 ;
-; 1.095 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.361 ;
-; 1.095 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.361 ;
-; 1.096 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.380 ;
-; 1.097 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.363 ;
-; 1.097 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.381 ;
-; 1.100 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.384 ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Hold: 'CLOCK_50' ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; 0.653 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.920 ;
-; 0.654 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.921 ;
-; 0.654 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.921 ;
-; 0.655 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.922 ;
-; 0.655 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.922 ;
-; 0.656 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.923 ;
-; 0.656 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.923 ;
-; 0.657 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.924 ;
-; 0.657 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.924 ;
-; 0.657 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.924 ;
-; 0.657 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.924 ;
-; 0.659 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.926 ;
-; 0.660 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.927 ;
-; 0.660 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.927 ;
-; 0.660 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.927 ;
-; 0.660 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.927 ;
-; 0.661 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.928 ;
-; 0.661 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.928 ;
-; 0.661 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.928 ;
-; 0.661 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.928 ;
-; 0.681 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.948 ;
-; 0.972 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.239 ;
-; 0.972 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.239 ;
-; 0.973 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.240 ;
-; 0.974 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.241 ;
-; 0.974 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.241 ;
-; 0.974 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.241 ;
-; 0.985 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.252 ;
-; 0.986 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.253 ;
-; 0.987 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.254 ;
-; 0.987 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.254 ;
-; 0.988 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.255 ;
-; 0.988 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.255 ;
-; 0.988 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.255 ;
-; 0.989 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.256 ;
-; 0.990 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.257 ;
-; 0.991 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.258 ;
-; 0.992 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.259 ;
-; 0.992 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.259 ;
-; 0.993 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.260 ;
-; 0.993 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.260 ;
-; 0.993 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.260 ;
-; 1.093 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.360 ;
-; 1.093 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.360 ;
-; 1.093 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.360 ;
-; 1.094 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.361 ;
-; 1.095 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.359 ;
-; 1.095 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.362 ;
-; 1.095 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.362 ;
-; 1.098 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.365 ;
-; 1.098 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.365 ;
-; 1.099 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.366 ;
-; 1.100 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.367 ;
-; 1.100 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.367 ;
-; 1.111 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.378 ;
-; 1.112 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.379 ;
-; 1.113 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.380 ;
-; 1.114 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.381 ;
-; 1.114 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.381 ;
-; 1.114 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.381 ;
-; 1.115 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.382 ;
-; 1.116 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.383 ;
-; 1.117 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.385 ;
-; 1.118 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.385 ;
-; 1.118 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.385 ;
-; 1.119 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.386 ;
-; 1.119 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.386 ;
-; 1.139 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.405 ;
-; 1.140 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.406 ;
-; 1.152 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.418 ;
-; 1.172 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.438 ;
-; 1.182 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.448 ;
-; 1.193 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.459 ;
-; 1.199 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.465 ;
-; 1.219 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.486 ;
-; 1.219 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.486 ;
-; 1.219 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.486 ;
-; 1.221 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.488 ;
-; 1.224 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.491 ;
-; 1.224 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.491 ;
-; 1.225 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.492 ;
-; 1.226 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.490 ;
-; 1.236 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.503 ;
-; 1.237 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.504 ;
-; 1.238 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.505 ;
-; 1.239 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.506 ;
-; 1.239 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.506 ;
-; 1.240 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.507 ;
-; 1.240 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.507 ;
-; 1.241 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.508 ;
-; 1.243 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.510 ;
-; 1.244 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.511 ;
-; 1.244 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.511 ;
-; 1.245 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.513 ;
-; 1.245 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.512 ;
-; 1.256 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.522 ;
-; 1.259 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.525 ;
-; 1.265 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.531 ;
-; 1.266 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.532 ;
-; 1.275 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.541 ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Fmax Summary ;
-+------------+-----------------+--------------------------+------------------------------------------------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+--------------------------+------------------------------------------------+
-; 206.19 MHz ; 206.19 MHz ; CLOCK_50 ; ;
-; 480.54 MHz ; 437.64 MHz ; FreqDivider:inst2|clkOut ; limit due to minimum period restriction (tmin) ;
-+------------+-----------------+--------------------------+------------------------------------------------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+---------------------------------------------------+
-; Slow 1200mV 0C Model Setup Summary ;
-+--------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+--------+---------------+
-; CLOCK_50 ; -3.850 ; -55.792 ;
-; FreqDivider:inst2|clkOut ; -1.081 ; -12.785 ;
-+--------------------------+--------+---------------+
-
-
-+--------------------------------------------------+
-; Slow 1200mV 0C Model Hold Summary ;
-+--------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+-------+---------------+
-; FreqDivider:inst2|clkOut ; 0.489 ; 0.000 ;
-; CLOCK_50 ; 0.598 ; 0.000 ;
-+--------------------------+-------+---------------+
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-+--------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+--------+---------------+
-; CLOCK_50 ; -3.000 ; -45.405 ;
-; FreqDivider:inst2|clkOut ; -1.285 ; -21.845 ;
-+--------------------------+--------+---------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Setup: 'CLOCK_50' ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; -3.850 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.777 ;
-; -3.839 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.766 ;
-; -3.832 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.759 ;
-; -3.821 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.745 ;
-; -3.814 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.738 ;
-; -3.760 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.687 ;
-; -3.757 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.684 ;
-; -3.693 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 4.616 ;
-; -3.688 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 4.611 ;
-; -3.652 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.576 ;
-; -3.632 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.559 ;
-; -3.604 ; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 4.527 ;
-; -3.598 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 4.521 ;
-; -3.540 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.464 ;
-; -3.539 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.463 ;
-; -3.528 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 4.451 ;
-; -3.453 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.377 ;
-; -3.405 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.332 ;
-; -3.383 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.307 ;
-; -3.246 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 4.172 ;
-; -3.139 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.066 ;
-; -3.137 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 4.063 ;
-; -3.100 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.024 ;
-; -3.036 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.963 ;
-; -2.980 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.907 ;
-; -2.965 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.891 ;
-; -2.946 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.870 ;
-; -2.904 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.828 ;
-; -2.861 ; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.787 ;
-; -2.780 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.704 ;
-; -2.758 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.684 ;
-; -2.744 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.670 ;
-; -2.437 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.361 ;
-; -2.357 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.281 ;
-; -2.328 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.252 ;
-; -2.321 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.245 ;
-; -2.316 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.244 ;
-; -2.302 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.225 ;
-; -2.292 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.216 ;
-; -2.272 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.196 ;
-; -2.256 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.183 ;
-; -2.255 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.182 ;
-; -2.254 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.181 ;
-; -2.251 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.178 ;
-; -2.250 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.177 ;
-; -2.249 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.176 ;
-; -2.248 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.172 ;
-; -2.248 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.175 ;
-; -2.247 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.174 ;
-; -2.246 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.173 ;
-; -2.243 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.167 ;
-; -2.242 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.166 ;
-; -2.238 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.162 ;
-; -2.237 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.165 ;
-; -2.227 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.151 ;
-; -2.220 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.144 ;
-; -2.219 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.143 ;
-; -2.217 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.141 ;
-; -2.213 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.137 ;
-; -2.212 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.136 ;
-; -2.211 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.135 ;
-; -2.210 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.134 ;
-; -2.197 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.125 ;
-; -2.193 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.116 ;
-; -2.193 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.117 ;
-; -2.176 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.100 ;
-; -2.176 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.100 ;
-; -2.176 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.103 ;
-; -2.175 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.102 ;
-; -2.174 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.101 ;
-; -2.173 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.100 ;
-; -2.172 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.099 ;
-; -2.171 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.098 ;
-; -2.163 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.087 ;
-; -2.157 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.080 ;
-; -2.156 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.080 ;
-; -2.153 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.077 ;
-; -2.147 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.071 ;
-; -2.131 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.055 ;
-; -2.127 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.051 ;
-; -2.124 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.048 ;
-; -2.123 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.047 ;
-; -2.123 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.047 ;
-; -2.122 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.050 ;
-; -2.111 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.035 ;
-; -2.099 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.023 ;
-; -2.095 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.019 ;
-; -2.092 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.015 ;
-; -2.092 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.015 ;
-; -2.091 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.014 ;
-; -2.089 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.012 ;
-; -2.087 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.010 ;
-; -2.086 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.009 ;
-; -2.084 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.007 ;
-; -2.082 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.010 ;
-; -2.078 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.002 ;
-; -2.077 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.001 ;
-; -2.076 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 2.999 ;
-; -2.068 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 2.992 ;
-; -2.067 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 2.991 ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Setup: 'FreqDivider:inst2|clkOut' ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; -1.081 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.387 ;
-; -1.011 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.922 ;
-; -1.002 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.308 ;
-; -0.984 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.290 ;
-; -0.965 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.271 ;
-; -0.961 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.267 ;
-; -0.936 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.242 ;
-; -0.931 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.842 ;
-; -0.914 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.825 ;
-; -0.899 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.826 ;
-; -0.895 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.806 ;
-; -0.892 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.803 ;
-; -0.886 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.192 ;
-; -0.886 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.192 ;
-; -0.880 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.807 ;
-; -0.868 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.174 ;
-; -0.868 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.174 ;
-; -0.866 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.777 ;
-; -0.851 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.778 ;
-; -0.849 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.155 ;
-; -0.845 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.151 ;
-; -0.844 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.150 ;
-; -0.820 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.126 ;
-; -0.816 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.727 ;
-; -0.816 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.122 ;
-; -0.815 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.726 ;
-; -0.801 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.728 ;
-; -0.799 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.710 ;
-; -0.798 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.709 ;
-; -0.783 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.710 ;
-; -0.783 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.710 ;
-; -0.779 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.690 ;
-; -0.777 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.688 ;
-; -0.776 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.687 ;
-; -0.770 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.076 ;
-; -0.770 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.076 ;
-; -0.769 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.075 ;
-; -0.764 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.691 ;
-; -0.760 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.687 ;
-; -0.752 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.058 ;
-; -0.752 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.058 ;
-; -0.752 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.058 ;
-; -0.750 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.661 ;
-; -0.747 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.658 ;
-; -0.735 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.662 ;
-; -0.733 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.039 ;
-; -0.731 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.658 ;
-; -0.729 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.035 ;
-; -0.728 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.034 ;
-; -0.727 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.033 ;
-; -0.704 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.010 ;
-; -0.701 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.612 ;
-; -0.700 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.611 ;
-; -0.700 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.006 ;
-; -0.699 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.005 ;
-; -0.699 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.610 ;
-; -0.685 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.612 ;
-; -0.685 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.612 ;
-; -0.683 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.594 ;
-; -0.683 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.594 ;
-; -0.682 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.593 ;
-; -0.667 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.594 ;
-; -0.667 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.594 ;
-; -0.667 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.594 ;
-; -0.665 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.576 ;
-; -0.663 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.574 ;
-; -0.661 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.572 ;
-; -0.660 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.571 ;
-; -0.654 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.960 ;
-; -0.654 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.960 ;
-; -0.653 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.959 ;
-; -0.653 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.959 ;
-; -0.648 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.575 ;
-; -0.644 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.571 ;
-; -0.643 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.570 ;
-; -0.636 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.942 ;
-; -0.636 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.942 ;
-; -0.636 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.942 ;
-; -0.635 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.941 ;
-; -0.634 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.545 ;
-; -0.632 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.543 ;
-; -0.631 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.542 ;
-; -0.619 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.546 ;
-; -0.617 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.923 ;
-; -0.615 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.542 ;
-; -0.614 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.541 ;
-; -0.613 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.919 ;
-; -0.612 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.918 ;
-; -0.611 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.917 ;
-; -0.591 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.502 ;
-; -0.588 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.894 ;
-; -0.585 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.496 ;
-; -0.584 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.495 ;
-; -0.584 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.890 ;
-; -0.583 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.889 ;
-; -0.583 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.494 ;
-; -0.582 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.888 ;
-; -0.569 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.496 ;
-; -0.569 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.496 ;
-; -0.568 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.495 ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Hold: 'FreqDivider:inst2|clkOut' ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; 0.489 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.127 ;
-; 0.508 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.146 ;
-; 0.584 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.843 ;
-; 0.584 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.843 ;
-; 0.585 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.844 ;
-; 0.585 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.844 ;
-; 0.586 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.845 ;
-; 0.587 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.846 ;
-; 0.588 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.847 ;
-; 0.588 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.226 ;
-; 0.589 ; AccN:inst|RegN:reg|dataOut[16] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.848 ;
-; 0.590 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.849 ;
-; 0.599 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.842 ;
-; 0.599 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.237 ;
-; 0.600 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.843 ;
-; 0.600 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.843 ;
-; 0.600 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.238 ;
-; 0.602 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.845 ;
-; 0.602 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.845 ;
-; 0.603 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.846 ;
-; 0.605 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.848 ;
-; 0.607 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.245 ;
-; 0.618 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.256 ;
-; 0.618 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.256 ;
-; 0.620 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[0] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.863 ;
-; 0.698 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.336 ;
-; 0.699 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.337 ;
-; 0.709 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.347 ;
-; 0.710 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.348 ;
-; 0.710 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.348 ;
-; 0.717 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.355 ;
-; 0.717 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.355 ;
-; 0.728 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.366 ;
-; 0.728 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.366 ;
-; 0.729 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.367 ;
-; 0.808 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.446 ;
-; 0.809 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.447 ;
-; 0.809 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.447 ;
-; 0.819 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.457 ;
-; 0.820 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.458 ;
-; 0.820 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.458 ;
-; 0.825 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.463 ;
-; 0.827 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.465 ;
-; 0.827 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.465 ;
-; 0.828 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.466 ;
-; 0.838 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.476 ;
-; 0.838 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.476 ;
-; 0.839 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.477 ;
-; 0.839 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.477 ;
-; 0.869 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.128 ;
-; 0.870 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.129 ;
-; 0.873 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.132 ;
-; 0.873 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.132 ;
-; 0.875 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.134 ;
-; 0.875 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.134 ;
-; 0.876 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.135 ;
-; 0.877 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.136 ;
-; 0.884 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.143 ;
-; 0.885 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.128 ;
-; 0.885 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.128 ;
-; 0.886 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.145 ;
-; 0.887 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.146 ;
-; 0.888 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.147 ;
-; 0.890 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.133 ;
-; 0.892 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.135 ;
-; 0.892 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.135 ;
-; 0.893 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.136 ;
-; 0.893 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.136 ;
-; 0.903 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.146 ;
-; 0.904 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.147 ;
-; 0.904 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.147 ;
-; 0.918 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.556 ;
-; 0.919 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.557 ;
-; 0.919 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.557 ;
-; 0.924 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.562 ;
-; 0.929 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.567 ;
-; 0.930 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.568 ;
-; 0.930 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.568 ;
-; 0.935 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.573 ;
-; 0.937 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.575 ;
-; 0.937 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.575 ;
-; 0.938 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.576 ;
-; 0.938 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.576 ;
-; 0.948 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.586 ;
-; 0.948 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.586 ;
-; 0.949 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.587 ;
-; 0.949 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.587 ;
-; 0.968 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.227 ;
-; 0.969 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.228 ;
-; 0.972 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.231 ;
-; 0.979 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.238 ;
-; 0.980 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.239 ;
-; 0.983 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.242 ;
-; 0.984 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.227 ;
-; 0.984 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.227 ;
-; 0.985 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.244 ;
-; 0.986 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.245 ;
-; 0.987 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.246 ;
-; 0.989 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.232 ;
-; 0.995 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.238 ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Hold: 'CLOCK_50' ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; 0.598 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.841 ;
-; 0.598 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.841 ;
-; 0.598 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.841 ;
-; 0.599 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.842 ;
-; 0.600 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.843 ;
-; 0.600 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.843 ;
-; 0.600 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.843 ;
-; 0.601 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.844 ;
-; 0.601 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.844 ;
-; 0.602 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.845 ;
-; 0.602 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.845 ;
-; 0.603 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.846 ;
-; 0.604 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.847 ;
-; 0.604 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.847 ;
-; 0.604 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.847 ;
-; 0.604 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.847 ;
-; 0.604 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.847 ;
-; 0.605 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.848 ;
-; 0.605 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.848 ;
-; 0.605 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.848 ;
-; 0.623 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.866 ;
-; 0.884 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.127 ;
-; 0.885 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.128 ;
-; 0.886 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.129 ;
-; 0.888 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.131 ;
-; 0.889 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.132 ;
-; 0.889 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.132 ;
-; 0.890 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.133 ;
-; 0.891 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.134 ;
-; 0.892 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.135 ;
-; 0.892 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.135 ;
-; 0.892 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.135 ;
-; 0.893 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.136 ;
-; 0.893 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.136 ;
-; 0.899 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.142 ;
-; 0.901 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.144 ;
-; 0.902 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.145 ;
-; 0.903 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.146 ;
-; 0.903 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.146 ;
-; 0.904 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.147 ;
-; 0.904 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.147 ;
-; 0.904 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.147 ;
-; 0.983 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.226 ;
-; 0.983 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.226 ;
-; 0.984 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.227 ;
-; 0.985 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.228 ;
-; 0.986 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 1.226 ;
-; 0.987 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.230 ;
-; 0.988 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.231 ;
-; 0.994 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.237 ;
-; 0.996 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.239 ;
-; 0.998 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.241 ;
-; 0.998 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.241 ;
-; 0.999 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.242 ;
-; 1.000 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.243 ;
-; 1.001 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.244 ;
-; 1.002 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.245 ;
-; 1.003 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.246 ;
-; 1.003 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.246 ;
-; 1.003 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.246 ;
-; 1.009 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.252 ;
-; 1.011 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.254 ;
-; 1.013 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.256 ;
-; 1.013 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.256 ;
-; 1.014 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.257 ;
-; 1.014 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.257 ;
-; 1.029 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.273 ;
-; 1.048 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.291 ;
-; 1.048 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.291 ;
-; 1.050 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.293 ;
-; 1.063 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 1.305 ;
-; 1.082 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.325 ;
-; 1.092 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.335 ;
-; 1.093 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.336 ;
-; 1.093 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.336 ;
-; 1.095 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.338 ;
-; 1.097 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.340 ;
-; 1.104 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.347 ;
-; 1.104 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.347 ;
-; 1.106 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 1.348 ;
-; 1.107 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 1.347 ;
-; 1.108 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.351 ;
-; 1.108 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.351 ;
-; 1.110 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.353 ;
-; 1.111 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.354 ;
-; 1.112 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.355 ;
-; 1.112 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.355 ;
-; 1.113 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.356 ;
-; 1.113 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.356 ;
-; 1.119 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.362 ;
-; 1.120 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.363 ;
-; 1.122 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.365 ;
-; 1.123 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.366 ;
-; 1.123 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.366 ;
-; 1.124 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 1.366 ;
-; 1.124 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.367 ;
-; 1.147 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.391 ;
-; 1.158 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.401 ;
-; 1.158 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.401 ;
-; 1.160 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 1.402 ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+---------------------------------------------------+
-; Fast 1200mV 0C Model Setup Summary ;
-+--------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+--------+---------------+
-; CLOCK_50 ; -1.676 ; -16.763 ;
-; FreqDivider:inst2|clkOut ; -0.170 ; -0.504 ;
-+--------------------------+--------+---------------+
-
-
-+--------------------------------------------------+
-; Fast 1200mV 0C Model Hold Summary ;
-+--------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+-------+---------------+
-; FreqDivider:inst2|clkOut ; 0.244 ; 0.000 ;
-; CLOCK_50 ; 0.297 ; 0.000 ;
-+--------------------------+-------+---------------+
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-+--------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------------------+--------+---------------+
-; CLOCK_50 ; -3.000 ; -38.036 ;
-; FreqDivider:inst2|clkOut ; -1.000 ; -17.000 ;
-+--------------------------+--------+---------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Setup: 'CLOCK_50' ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; -1.676 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.619 ;
-; -1.674 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.617 ;
-; -1.622 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.567 ;
-; -1.603 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.548 ;
-; -1.602 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.545 ;
-; -1.601 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.546 ;
-; -1.601 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.544 ;
-; -1.569 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.514 ;
-; -1.559 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.504 ;
-; -1.539 ; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.482 ;
-; -1.536 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.479 ;
-; -1.526 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.469 ;
-; -1.503 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.446 ;
-; -1.493 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.438 ;
-; -1.471 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.414 ;
-; -1.465 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.408 ;
-; -1.458 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.401 ;
-; -1.454 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.397 ;
-; -1.441 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.386 ;
-; -1.292 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.237 ;
-; -1.286 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.229 ;
-; -1.229 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.174 ;
-; -1.222 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.167 ;
-; -1.213 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.158 ;
-; -1.179 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.122 ;
-; -1.122 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.065 ;
-; -1.107 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.052 ;
-; -1.103 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.046 ;
-; -1.086 ; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.031 ;
-; -1.053 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.998 ;
-; -1.031 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.976 ;
-; -0.939 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.884 ;
-; -0.893 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.836 ;
-; -0.879 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.822 ;
-; -0.847 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.790 ;
-; -0.843 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.786 ;
-; -0.833 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.776 ;
-; -0.822 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.765 ;
-; -0.822 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.765 ;
-; -0.812 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.755 ;
-; -0.808 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.753 ;
-; -0.808 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.751 ;
-; -0.801 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.744 ;
-; -0.800 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.743 ;
-; -0.799 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.742 ;
-; -0.798 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.741 ;
-; -0.796 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.739 ;
-; -0.795 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.738 ;
-; -0.785 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.728 ;
-; -0.779 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.722 ;
-; -0.776 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.719 ;
-; -0.775 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.718 ;
-; -0.772 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.715 ;
-; -0.768 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.711 ;
-; -0.766 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.709 ;
-; -0.765 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.708 ;
-; -0.763 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.706 ;
-; -0.760 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.705 ;
-; -0.757 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.700 ;
-; -0.754 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.697 ;
-; -0.754 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.697 ;
-; -0.747 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.692 ;
-; -0.746 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.691 ;
-; -0.744 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.689 ;
-; -0.743 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.686 ;
-; -0.741 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.684 ;
-; -0.737 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.682 ;
-; -0.737 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.680 ;
-; -0.728 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.671 ;
-; -0.728 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.673 ;
-; -0.727 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.670 ;
-; -0.727 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.672 ;
-; -0.727 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.670 ;
-; -0.726 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.669 ;
-; -0.726 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.671 ;
-; -0.726 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.669 ;
-; -0.725 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.670 ;
-; -0.725 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.670 ;
-; -0.725 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.668 ;
-; -0.724 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.667 ;
-; -0.723 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.668 ;
-; -0.723 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.666 ;
-; -0.717 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.660 ;
-; -0.714 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.657 ;
-; -0.711 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.654 ;
-; -0.708 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.651 ;
-; -0.708 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.651 ;
-; -0.707 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.650 ;
-; -0.704 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.647 ;
-; -0.704 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.647 ;
-; -0.698 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.641 ;
-; -0.698 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.641 ;
-; -0.698 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.641 ;
-; -0.697 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.640 ;
-; -0.694 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.639 ;
-; -0.693 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.638 ;
-; -0.693 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.638 ;
-; -0.692 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.635 ;
-; -0.691 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.636 ;
-; -0.690 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.633 ;
-+--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Setup: 'FreqDivider:inst2|clkOut' ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; -0.170 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.311 ;
-; -0.123 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.264 ;
-; -0.106 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.247 ;
-; -0.102 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.243 ;
-; -0.102 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 1.039 ;
-; -0.098 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.239 ;
-; -0.092 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.233 ;
-; -0.055 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.196 ;
-; -0.054 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.991 ;
-; -0.054 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.195 ;
-; -0.038 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.179 ;
-; -0.038 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.975 ;
-; -0.034 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.175 ;
-; -0.034 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.175 ;
-; -0.034 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.971 ;
-; -0.032 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.969 ;
-; -0.031 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.172 ;
-; -0.030 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.171 ;
-; -0.029 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.975 ;
-; -0.025 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.971 ;
-; -0.025 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.166 ;
-; -0.024 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.961 ;
-; -0.024 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.165 ;
-; -0.015 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.961 ;
-; 0.013 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.924 ;
-; 0.013 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.128 ;
-; 0.014 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.127 ;
-; 0.014 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.923 ;
-; 0.014 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.127 ;
-; 0.022 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.924 ;
-; 0.030 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.111 ;
-; 0.030 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.907 ;
-; 0.032 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.905 ;
-; 0.033 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.108 ;
-; 0.034 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.107 ;
-; 0.034 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.107 ;
-; 0.034 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.903 ;
-; 0.036 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.901 ;
-; 0.036 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.901 ;
-; 0.037 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.104 ;
-; 0.038 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.103 ;
-; 0.038 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.103 ;
-; 0.039 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.907 ;
-; 0.043 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.903 ;
-; 0.043 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.894 ;
-; 0.043 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.098 ;
-; 0.043 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.903 ;
-; 0.043 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.098 ;
-; 0.044 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.893 ;
-; 0.044 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.097 ;
-; 0.047 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.899 ;
-; 0.052 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.894 ;
-; 0.053 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.893 ;
-; 0.081 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.856 ;
-; 0.081 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.856 ;
-; 0.081 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.060 ;
-; 0.082 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.059 ;
-; 0.082 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.059 ;
-; 0.082 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.855 ;
-; 0.082 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.059 ;
-; 0.090 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.856 ;
-; 0.091 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.855 ;
-; 0.098 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.043 ;
-; 0.098 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.839 ;
-; 0.100 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.837 ;
-; 0.100 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.837 ;
-; 0.100 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.837 ;
-; 0.101 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.040 ;
-; 0.102 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.039 ;
-; 0.102 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.039 ;
-; 0.102 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.039 ;
-; 0.102 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.835 ;
-; 0.104 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.833 ;
-; 0.104 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.833 ;
-; 0.105 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.036 ;
-; 0.106 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.035 ;
-; 0.106 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.035 ;
-; 0.107 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.839 ;
-; 0.110 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.836 ;
-; 0.111 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.835 ;
-; 0.111 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.826 ;
-; 0.111 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.826 ;
-; 0.111 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.030 ;
-; 0.111 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.835 ;
-; 0.111 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.030 ;
-; 0.112 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.029 ;
-; 0.112 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.825 ;
-; 0.112 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.029 ;
-; 0.114 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.832 ;
-; 0.115 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.831 ;
-; 0.120 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.826 ;
-; 0.120 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.826 ;
-; 0.121 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.825 ;
-; 0.149 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.788 ;
-; 0.149 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.788 ;
-; 0.149 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 0.992 ;
-; 0.150 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.787 ;
-; 0.150 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 0.991 ;
-; 0.150 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 0.991 ;
-; 0.150 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.787 ;
-+--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Hold: 'FreqDivider:inst2|clkOut' ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-; 0.244 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.573 ;
-; 0.258 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.587 ;
-; 0.291 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.425 ;
-; 0.291 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.425 ;
-; 0.292 ; AccN:inst|RegN:reg|dataOut[16] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.426 ;
-; 0.292 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.426 ;
-; 0.292 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.426 ;
-; 0.292 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.426 ;
-; 0.292 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.426 ;
-; 0.293 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.427 ;
-; 0.293 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.427 ;
-; 0.300 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.425 ;
-; 0.300 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.425 ;
-; 0.300 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.425 ;
-; 0.301 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.426 ;
-; 0.301 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.426 ;
-; 0.301 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.426 ;
-; 0.302 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.427 ;
-; 0.307 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[0] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.432 ;
-; 0.307 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.636 ;
-; 0.310 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.639 ;
-; 0.310 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.639 ;
-; 0.321 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.650 ;
-; 0.324 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.653 ;
-; 0.325 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.654 ;
-; 0.373 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.702 ;
-; 0.373 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.702 ;
-; 0.376 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.705 ;
-; 0.376 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.705 ;
-; 0.377 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.706 ;
-; 0.387 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.716 ;
-; 0.388 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.717 ;
-; 0.390 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.719 ;
-; 0.391 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.720 ;
-; 0.391 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.720 ;
-; 0.439 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.768 ;
-; 0.439 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.768 ;
-; 0.440 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.574 ;
-; 0.440 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.574 ;
-; 0.440 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.574 ;
-; 0.440 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.769 ;
-; 0.441 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.575 ;
-; 0.442 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.771 ;
-; 0.442 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.771 ;
-; 0.443 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.772 ;
-; 0.444 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.773 ;
-; 0.448 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.573 ;
-; 0.449 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.574 ;
-; 0.450 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.584 ;
-; 0.450 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.575 ;
-; 0.450 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.584 ;
-; 0.451 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.585 ;
-; 0.452 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.586 ;
-; 0.453 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.587 ;
-; 0.453 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.782 ;
-; 0.453 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.587 ;
-; 0.454 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.588 ;
-; 0.454 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.783 ;
-; 0.454 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.783 ;
-; 0.455 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.589 ;
-; 0.456 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.785 ;
-; 0.457 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.786 ;
-; 0.457 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.786 ;
-; 0.457 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.786 ;
-; 0.459 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.584 ;
-; 0.460 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.585 ;
-; 0.460 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.585 ;
-; 0.460 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.585 ;
-; 0.463 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.588 ;
-; 0.463 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.588 ;
-; 0.463 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.588 ;
-; 0.503 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.637 ;
-; 0.503 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.637 ;
-; 0.503 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.637 ;
-; 0.505 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.834 ;
-; 0.505 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.834 ;
-; 0.506 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.640 ;
-; 0.506 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.640 ;
-; 0.506 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.640 ;
-; 0.506 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.835 ;
-; 0.507 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.836 ;
-; 0.508 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.837 ;
-; 0.508 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.837 ;
-; 0.509 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.838 ;
-; 0.510 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.839 ;
-; 0.511 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.636 ;
-; 0.512 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.637 ;
-; 0.513 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.638 ;
-; 0.515 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.640 ;
-; 0.516 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.650 ;
-; 0.516 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.641 ;
-; 0.517 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.651 ;
-; 0.518 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.652 ;
-; 0.519 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.653 ;
-; 0.519 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.848 ;
-; 0.520 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.654 ;
-; 0.520 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.849 ;
-; 0.520 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.849 ;
-; 0.520 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.849 ;
-; 0.521 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.655 ;
-+-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Hold: 'CLOCK_50' ;
-+-------+---------------------------------+---------------------------------+--------------------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+---------------------------------+---------------------------------+--------------------------+-------------+--------------+------------+------------+
-; 0.297 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.423 ;
-; 0.298 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.424 ;
-; 0.298 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.424 ;
-; 0.298 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.424 ;
-; 0.299 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ;
-; 0.299 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ;
-; 0.299 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ;
-; 0.299 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ;
-; 0.299 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ;
-; 0.300 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.426 ;
-; 0.300 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.426 ;
-; 0.300 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.426 ;
-; 0.300 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.426 ;
-; 0.301 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.427 ;
-; 0.301 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.427 ;
-; 0.301 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.427 ;
-; 0.301 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.427 ;
-; 0.301 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.427 ;
-; 0.302 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.428 ;
-; 0.302 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.428 ;
-; 0.310 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.436 ;
-; 0.447 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.573 ;
-; 0.448 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.574 ;
-; 0.448 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.574 ;
-; 0.448 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.574 ;
-; 0.448 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.574 ;
-; 0.449 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.575 ;
-; 0.457 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.583 ;
-; 0.458 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.584 ;
-; 0.458 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.584 ;
-; 0.459 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.585 ;
-; 0.459 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.585 ;
-; 0.460 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.586 ;
-; 0.460 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.586 ;
-; 0.460 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.586 ;
-; 0.461 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.587 ;
-; 0.461 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.587 ;
-; 0.461 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.587 ;
-; 0.462 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.588 ;
-; 0.462 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.588 ;
-; 0.463 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.589 ;
-; 0.463 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.589 ;
-; 0.510 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.636 ;
-; 0.510 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.636 ;
-; 0.511 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ;
-; 0.511 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.040 ; 0.635 ;
-; 0.511 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ;
-; 0.511 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ;
-; 0.511 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ;
-; 0.511 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ;
-; 0.513 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.639 ;
-; 0.514 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.640 ;
-; 0.514 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.640 ;
-; 0.514 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.640 ;
-; 0.514 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.640 ;
-; 0.517 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.643 ;
-; 0.517 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.643 ;
-; 0.523 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.649 ;
-; 0.524 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.650 ;
-; 0.525 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.651 ;
-; 0.525 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.651 ;
-; 0.526 ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; CLOCK_50 ; 0.000 ; 1.647 ; 2.392 ;
-; 0.526 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.652 ;
-; 0.526 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.652 ;
-; 0.526 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.652 ;
-; 0.526 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.652 ;
-; 0.527 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.653 ;
-; 0.528 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.654 ;
-; 0.528 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.654 ;
-; 0.528 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.654 ;
-; 0.528 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.654 ;
-; 0.529 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.655 ;
-; 0.533 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.659 ;
-; 0.542 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.668 ;
-; 0.545 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.671 ;
-; 0.568 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.694 ;
-; 0.576 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.702 ;
-; 0.576 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.702 ;
-; 0.577 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.703 ;
-; 0.577 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.703 ;
-; 0.579 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.705 ;
-; 0.579 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.705 ;
-; 0.580 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.706 ;
-; 0.580 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.706 ;
-; 0.580 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.040 ; 0.704 ;
-; 0.580 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.706 ;
-; 0.583 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.709 ;
-; 0.583 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.709 ;
-; 0.587 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.713 ;
-; 0.589 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.715 ;
-; 0.590 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.716 ;
-; 0.590 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.716 ;
-; 0.591 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.717 ;
-; 0.591 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.717 ;
-; 0.591 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.717 ;
-; 0.592 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.718 ;
-; 0.592 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.718 ;
-; 0.593 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.719 ;
-; 0.593 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.719 ;
-; 0.594 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.720 ;
-+-------+---------------------------------+---------------------------------+--------------------------+-------------+--------------+------------+------------+
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+---------------------------+---------+-------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+---------------------------+---------+-------+----------+---------+---------------------+
-; Worst-case Slack ; -4.308 ; 0.244 ; N/A ; N/A ; -3.000 ;
-; CLOCK_50 ; -4.308 ; 0.297 ; N/A ; N/A ; -3.000 ;
-; FreqDivider:inst2|clkOut ; -1.349 ; 0.244 ; N/A ; N/A ; -1.285 ;
-; Design-wide TNS ; -82.271 ; 0.0 ; 0.0 ; 0.0 ; -67.25 ;
-; CLOCK_50 ; -65.920 ; 0.000 ; N/A ; N/A ; -45.405 ;
-; FreqDivider:inst2|clkOut ; -16.351 ; 0.000 ; N/A ; N/A ; -21.845 ;
-+---------------------------+---------+-------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDR[16] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; SW[16] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[15] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[14] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[13] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[12] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[11] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[10] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[17] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; CLOCK_50 ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ;
-; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ;
-; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ;
-; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ;
-; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[16] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[15] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ;
-; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ;
-; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Setup Transfers ;
-+--------------------------+--------------------------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+--------------------------+--------------------------+----------+----------+----------+----------+
-; CLOCK_50 ; CLOCK_50 ; 925 ; 0 ; 0 ; 0 ;
-; FreqDivider:inst2|clkOut ; CLOCK_50 ; 1 ; 1 ; 0 ; 0 ;
-; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 153 ; 0 ; 0 ; 0 ;
-+--------------------------+--------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-------------------------------------------------------------------------------------------------+
-; Hold Transfers ;
-+--------------------------+--------------------------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+--------------------------+--------------------------+----------+----------+----------+----------+
-; CLOCK_50 ; CLOCK_50 ; 925 ; 0 ; 0 ; 0 ;
-; FreqDivider:inst2|clkOut ; CLOCK_50 ; 1 ; 1 ; 0 ; 0 ;
-; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 153 ; 0 ; 0 ; 0 ;
-+--------------------------+--------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 19 ; 19 ;
-; Unconstrained Input Port Paths ; 187 ; 187 ;
-; Unconstrained Output Ports ; 17 ; 17 ;
-; Unconstrained Output Port Paths ; 17 ; 17 ;
-+---------------------------------+-------+------+
-
-
-+--------------------------------------------------------------------------+
-; Clock Status Summary ;
-+--------------------------+--------------------------+------+-------------+
-; Target ; Clock ; Type ; Status ;
-+--------------------------+--------------------------+------+-------------+
-; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ;
-; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; Base ; Constrained ;
-+--------------------------+--------------------------+------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[16] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[17] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[13] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[14] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[15] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[16] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[16] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[17] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[13] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[14] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[15] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[16] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Tue Mar 28 15:22:11 2023
-Info: Command: quartus_sta AccN_Demo -c AccN_Demo
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'AccN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
- Info (332105): create_clock -period 1.000 -name FreqDivider:inst2|clkOut FreqDivider:inst2|clkOut
- Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1200mV 85C Model
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case setup slack is -4.308
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -4.308 -65.920 CLOCK_50
- Info (332119): -1.349 -16.351 FreqDivider:inst2|clkOut
-Info (332146): Worst-case hold slack is 0.543
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.543 0.000 FreqDivider:inst2|clkOut
- Info (332119): 0.653 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -45.405 CLOCK_50
- Info (332119): -1.285 -21.845 FreqDivider:inst2|clkOut
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.850
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.850 -55.792 CLOCK_50
- Info (332119): -1.081 -12.785 FreqDivider:inst2|clkOut
-Info (332146): Worst-case hold slack is 0.489
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.489 0.000 FreqDivider:inst2|clkOut
- Info (332119): 0.598 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -45.405 CLOCK_50
- Info (332119): -1.285 -21.845 FreqDivider:inst2|clkOut
-Info: Analyzing Fast 1200mV 0C Model
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.676
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -1.676 -16.763 CLOCK_50
- Info (332119): -0.170 -0.504 FreqDivider:inst2|clkOut
-Info (332146): Worst-case hold slack is 0.244
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.244 0.000 FreqDivider:inst2|clkOut
- Info (332119): 0.297 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -38.036 CLOCK_50
- Info (332119): -1.000 -17.000 FreqDivider:inst2|clkOut
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 537 megabytes
- Info: Processing ended: Tue Mar 28 15:22:12 2023
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.summary b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.summary
deleted file mode 100644
index 3297e55..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.summary
+++ /dev/null
@@ -1,77 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-Type : Slow 1200mV 85C Model Setup 'CLOCK_50'
-Slack : -4.308
-TNS : -65.920
-
-Type : Slow 1200mV 85C Model Setup 'FreqDivider:inst2|clkOut'
-Slack : -1.349
-TNS : -16.351
-
-Type : Slow 1200mV 85C Model Hold 'FreqDivider:inst2|clkOut'
-Slack : 0.543
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Hold 'CLOCK_50'
-Slack : 0.653
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -3.000
-TNS : -45.405
-
-Type : Slow 1200mV 85C Model Minimum Pulse Width 'FreqDivider:inst2|clkOut'
-Slack : -1.285
-TNS : -21.845
-
-Type : Slow 1200mV 0C Model Setup 'CLOCK_50'
-Slack : -3.850
-TNS : -55.792
-
-Type : Slow 1200mV 0C Model Setup 'FreqDivider:inst2|clkOut'
-Slack : -1.081
-TNS : -12.785
-
-Type : Slow 1200mV 0C Model Hold 'FreqDivider:inst2|clkOut'
-Slack : 0.489
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Hold 'CLOCK_50'
-Slack : 0.598
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -3.000
-TNS : -45.405
-
-Type : Slow 1200mV 0C Model Minimum Pulse Width 'FreqDivider:inst2|clkOut'
-Slack : -1.285
-TNS : -21.845
-
-Type : Fast 1200mV 0C Model Setup 'CLOCK_50'
-Slack : -1.676
-TNS : -16.763
-
-Type : Fast 1200mV 0C Model Setup 'FreqDivider:inst2|clkOut'
-Slack : -0.170
-TNS : -0.504
-
-Type : Fast 1200mV 0C Model Hold 'FreqDivider:inst2|clkOut'
-Slack : 0.244
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
-Slack : 0.297
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -3.000
-TNS : -38.036
-
-Type : Fast 1200mV 0C Model Minimum Pulse Width 'FreqDivider:inst2|clkOut'
-Slack : -1.000
-TNS : -17.000
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/serv_req_info.txt b/1ano/2semestre/lsd/pratica05/AccN_Demo/serv_req_info.txt
deleted file mode 100644
index 715bc76..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/serv_req_info.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-
-ERR
-
- 0x7fec11bb7be6: ccl_err + 0x7be6 (_ZN15ERR_STACKWALKER15get_stack_traceEPPKviiPv + 0xd8)
- 0x7fec11bbae95: ccl_err + 0xae95 (_Z14err_terminatorv + 0x5a)
- 0x7fec2213eae6: jtag_client + 0x82ae6 (_ZN10__cxxabiv111__terminateEPFvvE + 0x6)
- 0x7fec2213eb31: jtag_client + 0x82b31
- 0x7fec2213ec86: jtag_client + 0x82c86 (__cxa_rethrow + 0x46)
- 0x7fec1d7b5074: QtCore.so.4 + 0x1b5074 (_ZN10QEventLoop4execE6QFlagsINS_17ProcessEventsFlagEE + 0x2f4)
- 0x7fec1d7b9cc4: QtCore.so.4 + 0x1b9cc4 (_ZN16QCoreApplication4execEv + 0xb4)
- 0x401eab: quartus + 0x1eab (_Z8qgq_mainiPPKc + 0x7b)
- 0x7fec12b4fe30: ccl_msg + 0x3ee30 (_Z15msg_main_threadPv + 0x10)
- 0x7fec11b81acc: ccl_thr + 0x5acc (thr_final_wrapper + 0xc)
- 0x7fec12b4feef: ccl_msg + 0x3eeef (_Z18msg_thread_wrapperPFPvS_ES_ + 0x62)
- 0x7fec11be9f9c: ccl_mem + 0x9f9c (_Z18mem_thread_wrapperPFPvS_ES_ + 0x5c)
- 0x7fec11bb8b39: ccl_err + 0x8b39 (_Z18err_thread_wrapperPFPvS_ES_ + 0x27)
- 0x7fec11b81b0f: ccl_thr + 0x5b0f (thr_thread_wrapper + 0x15)
- 0x7fec12b51ea1: ccl_msg + 0x40ea1 (_Z12msg_exe_mainiPPKcPFiiS1_E + 0xb2)
- 0x401f91: quartus + 0x1f91 (main + 0x26)
- 0x7febff429d90: c.so.6 + 0x29d90
- 0x7febff429e40: c.so.6 + 0x29e40 (__libc_start_main + 0x80)
- 0x401d39: quartus + 0x1d39
-
-*** Fatal Error: Unhandled Exception
-Wed Mar 22 12:37:34 2023
-
-Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo.sft b/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo.vho b/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo.vho
deleted file mode 100644
index 040c504..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo.vho
+++ /dev/null
@@ -1,2886 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/28/2023 15:22:13"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY ALTERA;
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY AccN_Demo IS
- PORT (
- LEDR : OUT std_logic_vector(16 DOWNTO 0);
- KEY : IN std_logic_vector(1 DOWNTO 1);
- SW : IN std_logic_vector(17 DOWNTO 0);
- CLOCK_50 : IN std_logic
- );
-END AccN_Demo;
-
--- Design Ports Information
--- LEDR[16] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[15] => Location: PIN_G15, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[14] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[13] => Location: PIN_H17, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[12] => Location: PIN_J16, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[11] => Location: PIN_H16, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[10] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[9] => Location: PIN_G17, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[8] => Location: PIN_J17, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[7] => Location: PIN_H19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[6] => Location: PIN_J19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[5] => Location: PIN_E18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[4] => Location: PIN_F18, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- SW[16] => Location: PIN_Y24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[15] => Location: PIN_AA22, I/O Standard: 2.5 V, Current Strength: Default
--- SW[14] => Location: PIN_AA23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[13] => Location: PIN_AA24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[12] => Location: PIN_AB23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[11] => Location: PIN_AB24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[10] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[9] => Location: PIN_AB25, I/O Standard: 2.5 V, Current Strength: Default
--- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default
--- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
--- SW[17] => Location: PIN_Y23, I/O Standard: 2.5 V, Current Strength: Default
--- CLOCK_50 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF AccN_Demo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDR : std_logic_vector(16 DOWNTO 0);
-SIGNAL ww_KEY : std_logic_vector(1 DOWNTO 1);
-SIGNAL ww_SW : std_logic_vector(17 DOWNTO 0);
-SIGNAL ww_CLOCK_50 : std_logic;
-SIGNAL \CLOCK_50~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
-SIGNAL \inst2|clkOut~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
-SIGNAL \LEDR[16]~output_o\ : std_logic;
-SIGNAL \LEDR[15]~output_o\ : std_logic;
-SIGNAL \LEDR[14]~output_o\ : std_logic;
-SIGNAL \LEDR[13]~output_o\ : std_logic;
-SIGNAL \LEDR[12]~output_o\ : std_logic;
-SIGNAL \LEDR[11]~output_o\ : std_logic;
-SIGNAL \LEDR[10]~output_o\ : std_logic;
-SIGNAL \LEDR[9]~output_o\ : std_logic;
-SIGNAL \LEDR[8]~output_o\ : std_logic;
-SIGNAL \LEDR[7]~output_o\ : std_logic;
-SIGNAL \LEDR[6]~output_o\ : std_logic;
-SIGNAL \LEDR[5]~output_o\ : std_logic;
-SIGNAL \LEDR[4]~output_o\ : std_logic;
-SIGNAL \LEDR[3]~output_o\ : std_logic;
-SIGNAL \LEDR[2]~output_o\ : std_logic;
-SIGNAL \LEDR[1]~output_o\ : std_logic;
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \CLOCK_50~input_o\ : std_logic;
-SIGNAL \CLOCK_50~inputclkctrl_outclk\ : std_logic;
-SIGNAL \inst2|Add2~0_combout\ : std_logic;
-SIGNAL \inst2|Add2~1\ : std_logic;
-SIGNAL \inst2|Add2~2_combout\ : std_logic;
-SIGNAL \inst2|Add2~3\ : std_logic;
-SIGNAL \inst2|Add2~4_combout\ : std_logic;
-SIGNAL \inst2|Add2~5\ : std_logic;
-SIGNAL \inst2|Add2~6_combout\ : std_logic;
-SIGNAL \inst2|Add2~7\ : std_logic;
-SIGNAL \inst2|Add2~8_combout\ : std_logic;
-SIGNAL \inst2|Add2~9\ : std_logic;
-SIGNAL \inst2|Add2~10_combout\ : std_logic;
-SIGNAL \inst2|Add2~11\ : std_logic;
-SIGNAL \inst2|Add2~12_combout\ : std_logic;
-SIGNAL \inst2|s_counter~10_combout\ : std_logic;
-SIGNAL \inst2|Add2~13\ : std_logic;
-SIGNAL \inst2|Add2~14_combout\ : std_logic;
-SIGNAL \inst2|Equal0~3_combout\ : std_logic;
-SIGNAL \inst2|Add2~15\ : std_logic;
-SIGNAL \inst2|Add2~16_combout\ : std_logic;
-SIGNAL \inst2|Add2~17\ : std_logic;
-SIGNAL \inst2|Add2~18_combout\ : std_logic;
-SIGNAL \inst2|Add2~19\ : std_logic;
-SIGNAL \inst2|Add2~20_combout\ : std_logic;
-SIGNAL \inst2|Add2~21\ : std_logic;
-SIGNAL \inst2|Add2~22_combout\ : std_logic;
-SIGNAL \inst2|s_counter~9_combout\ : std_logic;
-SIGNAL \inst2|Add2~23\ : std_logic;
-SIGNAL \inst2|Add2~24_combout\ : std_logic;
-SIGNAL \inst2|s_counter~8_combout\ : std_logic;
-SIGNAL \inst2|Equal0~2_combout\ : std_logic;
-SIGNAL \inst2|Add2~25\ : std_logic;
-SIGNAL \inst2|Add2~26_combout\ : std_logic;
-SIGNAL \inst2|s_counter~7_combout\ : std_logic;
-SIGNAL \inst2|Add2~27\ : std_logic;
-SIGNAL \inst2|Add2~28_combout\ : std_logic;
-SIGNAL \inst2|s_counter~5_combout\ : std_logic;
-SIGNAL \inst2|Add2~29\ : std_logic;
-SIGNAL \inst2|Add2~30_combout\ : std_logic;
-SIGNAL \inst2|Add2~31\ : std_logic;
-SIGNAL \inst2|Add2~32_combout\ : std_logic;
-SIGNAL \inst2|s_counter~4_combout\ : std_logic;
-SIGNAL \inst2|Add2~33\ : std_logic;
-SIGNAL \inst2|Add2~34_combout\ : std_logic;
-SIGNAL \inst2|Add2~35\ : std_logic;
-SIGNAL \inst2|Add2~36_combout\ : std_logic;
-SIGNAL \inst2|s_counter~6_combout\ : std_logic;
-SIGNAL \inst2|Add2~45\ : std_logic;
-SIGNAL \inst2|Add2~46_combout\ : std_logic;
-SIGNAL \inst2|s_counter~1_combout\ : std_logic;
-SIGNAL \inst2|Add2~47\ : std_logic;
-SIGNAL \inst2|Add2~48_combout\ : std_logic;
-SIGNAL \inst2|Add2~49\ : std_logic;
-SIGNAL \inst2|Add2~50_combout\ : std_logic;
-SIGNAL \inst2|s_counter~0_combout\ : std_logic;
-SIGNAL \inst2|Add2~51\ : std_logic;
-SIGNAL \inst2|Add2~52_combout\ : std_logic;
-SIGNAL \inst2|Add2~53\ : std_logic;
-SIGNAL \inst2|Add2~54_combout\ : std_logic;
-SIGNAL \inst2|Equal0~1_combout\ : std_logic;
-SIGNAL \inst2|Add2~55\ : std_logic;
-SIGNAL \inst2|Add2~56_combout\ : std_logic;
-SIGNAL \inst2|Add2~57\ : std_logic;
-SIGNAL \inst2|Add2~58_combout\ : std_logic;
-SIGNAL \inst2|Add2~59\ : std_logic;
-SIGNAL \inst2|Add2~60_combout\ : std_logic;
-SIGNAL \inst2|Add2~61\ : std_logic;
-SIGNAL \inst2|Add2~62_combout\ : std_logic;
-SIGNAL \inst2|Equal0~0_combout\ : std_logic;
-SIGNAL \inst2|Equal0~4_combout\ : std_logic;
-SIGNAL \inst2|Equal0~5_combout\ : std_logic;
-SIGNAL \inst2|Add2~37\ : std_logic;
-SIGNAL \inst2|Add2~39\ : std_logic;
-SIGNAL \inst2|Add2~40_combout\ : std_logic;
-SIGNAL \inst2|Add2~41\ : std_logic;
-SIGNAL \inst2|Add2~42_combout\ : std_logic;
-SIGNAL \inst2|s_counter~2_combout\ : std_logic;
-SIGNAL \inst2|Add2~43\ : std_logic;
-SIGNAL \inst2|Add2~44_combout\ : std_logic;
-SIGNAL \inst2|Equal0~6_combout\ : std_logic;
-SIGNAL \inst2|Equal0~7_combout\ : std_logic;
-SIGNAL \inst2|Equal0~8_combout\ : std_logic;
-SIGNAL \inst2|Equal0~9_combout\ : std_logic;
-SIGNAL \inst2|Add2~38_combout\ : std_logic;
-SIGNAL \inst2|s_counter~3_combout\ : std_logic;
-SIGNAL \inst2|clkOut~1_combout\ : std_logic;
-SIGNAL \inst2|clkOut~2_combout\ : std_logic;
-SIGNAL \inst2|clkOut~0_combout\ : std_logic;
-SIGNAL \inst2|clkOut~3_combout\ : std_logic;
-SIGNAL \inst2|clkOut~4_combout\ : std_logic;
-SIGNAL \inst2|clkOut~q\ : std_logic;
-SIGNAL \inst2|clkOut~clkctrl_outclk\ : std_logic;
-SIGNAL \SW[16]~input_o\ : std_logic;
-SIGNAL \SW[15]~input_o\ : std_logic;
-SIGNAL \SW[14]~input_o\ : std_logic;
-SIGNAL \SW[13]~input_o\ : std_logic;
-SIGNAL \SW[12]~input_o\ : std_logic;
-SIGNAL \SW[11]~input_o\ : std_logic;
-SIGNAL \SW[10]~input_o\ : std_logic;
-SIGNAL \SW[9]~input_o\ : std_logic;
-SIGNAL \SW[8]~input_o\ : std_logic;
-SIGNAL \SW[7]~input_o\ : std_logic;
-SIGNAL \SW[6]~input_o\ : std_logic;
-SIGNAL \SW[5]~input_o\ : std_logic;
-SIGNAL \SW[4]~input_o\ : std_logic;
-SIGNAL \SW[3]~input_o\ : std_logic;
-SIGNAL \SW[2]~input_o\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \inst|reg|dataOut[0]~17_combout\ : std_logic;
-SIGNAL \KEY[1]~input_o\ : std_logic;
-SIGNAL \SW[17]~input_o\ : std_logic;
-SIGNAL \inst|reg|dataOut[0]~18\ : std_logic;
-SIGNAL \inst|reg|dataOut[1]~19_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[1]~20\ : std_logic;
-SIGNAL \inst|reg|dataOut[2]~21_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[2]~22\ : std_logic;
-SIGNAL \inst|reg|dataOut[3]~23_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[3]~24\ : std_logic;
-SIGNAL \inst|reg|dataOut[4]~25_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[4]~26\ : std_logic;
-SIGNAL \inst|reg|dataOut[5]~27_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[5]~28\ : std_logic;
-SIGNAL \inst|reg|dataOut[6]~29_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[6]~30\ : std_logic;
-SIGNAL \inst|reg|dataOut[7]~31_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[7]~32\ : std_logic;
-SIGNAL \inst|reg|dataOut[8]~33_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[8]~34\ : std_logic;
-SIGNAL \inst|reg|dataOut[9]~35_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[9]~36\ : std_logic;
-SIGNAL \inst|reg|dataOut[10]~37_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[10]~38\ : std_logic;
-SIGNAL \inst|reg|dataOut[11]~39_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[11]~40\ : std_logic;
-SIGNAL \inst|reg|dataOut[12]~41_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[12]~42\ : std_logic;
-SIGNAL \inst|reg|dataOut[13]~43_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[13]~44\ : std_logic;
-SIGNAL \inst|reg|dataOut[14]~45_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[14]~46\ : std_logic;
-SIGNAL \inst|reg|dataOut[15]~47_combout\ : std_logic;
-SIGNAL \inst|reg|dataOut[15]~48\ : std_logic;
-SIGNAL \inst|reg|dataOut[16]~49_combout\ : std_logic;
-SIGNAL \inst2|s_counter\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \inst|reg|dataOut\ : std_logic_vector(16 DOWNTO 0);
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-LEDR <= ww_LEDR;
-ww_KEY <= KEY;
-ww_SW <= SW;
-ww_CLOCK_50 <= CLOCK_50;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
-\CLOCK_50~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLOCK_50~input_o\);
-
-\inst2|clkOut~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst2|clkOut~q\);
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X67_Y73_N2
-\LEDR[16]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(16),
- devoe => ww_devoe,
- o => \LEDR[16]~output_o\);
-
--- Location: IOOBUF_X65_Y73_N9
-\LEDR[15]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(15),
- devoe => ww_devoe,
- o => \LEDR[15]~output_o\);
-
--- Location: IOOBUF_X58_Y73_N2
-\LEDR[14]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(14),
- devoe => ww_devoe,
- o => \LEDR[14]~output_o\);
-
--- Location: IOOBUF_X67_Y73_N9
-\LEDR[13]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(13),
- devoe => ww_devoe,
- o => \LEDR[13]~output_o\);
-
--- Location: IOOBUF_X65_Y73_N16
-\LEDR[12]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(12),
- devoe => ww_devoe,
- o => \LEDR[12]~output_o\);
-
--- Location: IOOBUF_X65_Y73_N23
-\LEDR[11]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(11),
- devoe => ww_devoe,
- o => \LEDR[11]~output_o\);
-
--- Location: IOOBUF_X60_Y73_N23
-\LEDR[10]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(10),
- devoe => ww_devoe,
- o => \LEDR[10]~output_o\);
-
--- Location: IOOBUF_X83_Y73_N23
-\LEDR[9]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(9),
- devoe => ww_devoe,
- o => \LEDR[9]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N2
-\LEDR[8]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(8),
- devoe => ww_devoe,
- o => \LEDR[8]~output_o\);
-
--- Location: IOOBUF_X72_Y73_N2
-\LEDR[7]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(7),
- devoe => ww_devoe,
- o => \LEDR[7]~output_o\);
-
--- Location: IOOBUF_X72_Y73_N9
-\LEDR[6]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(6),
- devoe => ww_devoe,
- o => \LEDR[6]~output_o\);
-
--- Location: IOOBUF_X87_Y73_N9
-\LEDR[5]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(5),
- devoe => ww_devoe,
- o => \LEDR[5]~output_o\);
-
--- Location: IOOBUF_X87_Y73_N16
-\LEDR[4]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(4),
- devoe => ww_devoe,
- o => \LEDR[4]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N16
-\LEDR[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(3),
- devoe => ww_devoe,
- o => \LEDR[3]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N9
-\LEDR[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(2),
- devoe => ww_devoe,
- o => \LEDR[2]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N2
-\LEDR[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(1),
- devoe => ww_devoe,
- o => \LEDR[1]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N16
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|reg|dataOut\(0),
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
--- Location: IOIBUF_X0_Y36_N15
-\CLOCK_50~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_CLOCK_50,
- o => \CLOCK_50~input_o\);
-
--- Location: CLKCTRL_G4
-\CLOCK_50~inputclkctrl\ : cycloneive_clkctrl
--- pragma translate_off
-GENERIC MAP (
- clock_type => "global clock",
- ena_register_mode => "none")
--- pragma translate_on
-PORT MAP (
- inclk => \CLOCK_50~inputclkctrl_INCLK_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- outclk => \CLOCK_50~inputclkctrl_outclk\);
-
--- Location: LCCOMB_X55_Y72_N0
-\inst2|Add2~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~0_combout\ = \inst2|s_counter\(0) $ (VCC)
--- \inst2|Add2~1\ = CARRY(\inst2|s_counter\(0))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011001111001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(0),
- datad => VCC,
- combout => \inst2|Add2~0_combout\,
- cout => \inst2|Add2~1\);
-
--- Location: FF_X55_Y72_N1
-\inst2|s_counter[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(0));
-
--- Location: LCCOMB_X55_Y72_N2
-\inst2|Add2~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~2_combout\ = (\inst2|s_counter\(1) & (!\inst2|Add2~1\)) # (!\inst2|s_counter\(1) & ((\inst2|Add2~1\) # (GND)))
--- \inst2|Add2~3\ = CARRY((!\inst2|Add2~1\) # (!\inst2|s_counter\(1)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(1),
- datad => VCC,
- cin => \inst2|Add2~1\,
- combout => \inst2|Add2~2_combout\,
- cout => \inst2|Add2~3\);
-
--- Location: FF_X55_Y72_N3
-\inst2|s_counter[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(1));
-
--- Location: LCCOMB_X55_Y72_N4
-\inst2|Add2~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~4_combout\ = (\inst2|s_counter\(2) & (\inst2|Add2~3\ $ (GND))) # (!\inst2|s_counter\(2) & (!\inst2|Add2~3\ & VCC))
--- \inst2|Add2~5\ = CARRY((\inst2|s_counter\(2) & !\inst2|Add2~3\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(2),
- datad => VCC,
- cin => \inst2|Add2~3\,
- combout => \inst2|Add2~4_combout\,
- cout => \inst2|Add2~5\);
-
--- Location: FF_X55_Y72_N5
-\inst2|s_counter[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(2));
-
--- Location: LCCOMB_X55_Y72_N6
-\inst2|Add2~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~6_combout\ = (\inst2|s_counter\(3) & (!\inst2|Add2~5\)) # (!\inst2|s_counter\(3) & ((\inst2|Add2~5\) # (GND)))
--- \inst2|Add2~7\ = CARRY((!\inst2|Add2~5\) # (!\inst2|s_counter\(3)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(3),
- datad => VCC,
- cin => \inst2|Add2~5\,
- combout => \inst2|Add2~6_combout\,
- cout => \inst2|Add2~7\);
-
--- Location: FF_X55_Y72_N7
-\inst2|s_counter[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(3));
-
--- Location: LCCOMB_X55_Y72_N8
-\inst2|Add2~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~8_combout\ = (\inst2|s_counter\(4) & (\inst2|Add2~7\ $ (GND))) # (!\inst2|s_counter\(4) & (!\inst2|Add2~7\ & VCC))
--- \inst2|Add2~9\ = CARRY((\inst2|s_counter\(4) & !\inst2|Add2~7\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(4),
- datad => VCC,
- cin => \inst2|Add2~7\,
- combout => \inst2|Add2~8_combout\,
- cout => \inst2|Add2~9\);
-
--- Location: FF_X55_Y72_N9
-\inst2|s_counter[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(4));
-
--- Location: LCCOMB_X55_Y72_N10
-\inst2|Add2~10\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~10_combout\ = (\inst2|s_counter\(5) & (!\inst2|Add2~9\)) # (!\inst2|s_counter\(5) & ((\inst2|Add2~9\) # (GND)))
--- \inst2|Add2~11\ = CARRY((!\inst2|Add2~9\) # (!\inst2|s_counter\(5)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(5),
- datad => VCC,
- cin => \inst2|Add2~9\,
- combout => \inst2|Add2~10_combout\,
- cout => \inst2|Add2~11\);
-
--- Location: FF_X55_Y72_N11
-\inst2|s_counter[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~10_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(5));
-
--- Location: LCCOMB_X55_Y72_N12
-\inst2|Add2~12\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~12_combout\ = (\inst2|s_counter\(6) & (\inst2|Add2~11\ $ (GND))) # (!\inst2|s_counter\(6) & (!\inst2|Add2~11\ & VCC))
--- \inst2|Add2~13\ = CARRY((\inst2|s_counter\(6) & !\inst2|Add2~11\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(6),
- datad => VCC,
- cin => \inst2|Add2~11\,
- combout => \inst2|Add2~12_combout\,
- cout => \inst2|Add2~13\);
-
--- Location: LCCOMB_X56_Y72_N26
-\inst2|s_counter~10\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|s_counter~10_combout\ = (\inst2|Add2~12_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011111100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|Equal0~5_combout\,
- datac => \inst2|Equal0~9_combout\,
- datad => \inst2|Add2~12_combout\,
- combout => \inst2|s_counter~10_combout\);
-
--- Location: FF_X56_Y72_N27
-\inst2|s_counter[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|s_counter~10_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(6));
-
--- Location: LCCOMB_X55_Y72_N14
-\inst2|Add2~14\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~14_combout\ = (\inst2|s_counter\(7) & (!\inst2|Add2~13\)) # (!\inst2|s_counter\(7) & ((\inst2|Add2~13\) # (GND)))
--- \inst2|Add2~15\ = CARRY((!\inst2|Add2~13\) # (!\inst2|s_counter\(7)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(7),
- datad => VCC,
- cin => \inst2|Add2~13\,
- combout => \inst2|Add2~14_combout\,
- cout => \inst2|Add2~15\);
-
--- Location: FF_X55_Y72_N15
-\inst2|s_counter[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~14_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(7));
-
--- Location: LCCOMB_X56_Y72_N12
-\inst2|Equal0~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Equal0~3_combout\ = (\inst2|s_counter\(4) & (\inst2|s_counter\(3) & (!\inst2|s_counter\(6) & !\inst2|s_counter\(7))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(4),
- datab => \inst2|s_counter\(3),
- datac => \inst2|s_counter\(6),
- datad => \inst2|s_counter\(7),
- combout => \inst2|Equal0~3_combout\);
-
--- Location: LCCOMB_X55_Y72_N16
-\inst2|Add2~16\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~16_combout\ = (\inst2|s_counter\(8) & (\inst2|Add2~15\ $ (GND))) # (!\inst2|s_counter\(8) & (!\inst2|Add2~15\ & VCC))
--- \inst2|Add2~17\ = CARRY((\inst2|s_counter\(8) & !\inst2|Add2~15\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(8),
- datad => VCC,
- cin => \inst2|Add2~15\,
- combout => \inst2|Add2~16_combout\,
- cout => \inst2|Add2~17\);
-
--- Location: FF_X55_Y72_N17
-\inst2|s_counter[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~16_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(8));
-
--- Location: LCCOMB_X55_Y72_N18
-\inst2|Add2~18\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~18_combout\ = (\inst2|s_counter\(9) & (!\inst2|Add2~17\)) # (!\inst2|s_counter\(9) & ((\inst2|Add2~17\) # (GND)))
--- \inst2|Add2~19\ = CARRY((!\inst2|Add2~17\) # (!\inst2|s_counter\(9)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(9),
- datad => VCC,
- cin => \inst2|Add2~17\,
- combout => \inst2|Add2~18_combout\,
- cout => \inst2|Add2~19\);
-
--- Location: FF_X55_Y72_N19
-\inst2|s_counter[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~18_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(9));
-
--- Location: LCCOMB_X55_Y72_N20
-\inst2|Add2~20\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~20_combout\ = (\inst2|s_counter\(10) & (\inst2|Add2~19\ $ (GND))) # (!\inst2|s_counter\(10) & (!\inst2|Add2~19\ & VCC))
--- \inst2|Add2~21\ = CARRY((\inst2|s_counter\(10) & !\inst2|Add2~19\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(10),
- datad => VCC,
- cin => \inst2|Add2~19\,
- combout => \inst2|Add2~20_combout\,
- cout => \inst2|Add2~21\);
-
--- Location: FF_X55_Y72_N21
-\inst2|s_counter[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~20_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(10));
-
--- Location: LCCOMB_X55_Y72_N22
-\inst2|Add2~22\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~22_combout\ = (\inst2|s_counter\(11) & (!\inst2|Add2~21\)) # (!\inst2|s_counter\(11) & ((\inst2|Add2~21\) # (GND)))
--- \inst2|Add2~23\ = CARRY((!\inst2|Add2~21\) # (!\inst2|s_counter\(11)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(11),
- datad => VCC,
- cin => \inst2|Add2~21\,
- combout => \inst2|Add2~22_combout\,
- cout => \inst2|Add2~23\);
-
--- Location: LCCOMB_X56_Y72_N22
-\inst2|s_counter~9\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|s_counter~9_combout\ = (\inst2|Add2~22_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011111100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|Equal0~5_combout\,
- datac => \inst2|Equal0~9_combout\,
- datad => \inst2|Add2~22_combout\,
- combout => \inst2|s_counter~9_combout\);
-
--- Location: FF_X56_Y72_N23
-\inst2|s_counter[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|s_counter~9_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(11));
-
--- Location: LCCOMB_X55_Y72_N24
-\inst2|Add2~24\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~24_combout\ = (\inst2|s_counter\(12) & (\inst2|Add2~23\ $ (GND))) # (!\inst2|s_counter\(12) & (!\inst2|Add2~23\ & VCC))
--- \inst2|Add2~25\ = CARRY((\inst2|s_counter\(12) & !\inst2|Add2~23\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010010100001010",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(12),
- datad => VCC,
- cin => \inst2|Add2~23\,
- combout => \inst2|Add2~24_combout\,
- cout => \inst2|Add2~25\);
-
--- Location: LCCOMB_X56_Y72_N20
-\inst2|s_counter~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|s_counter~8_combout\ = (\inst2|Add2~24_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011111100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|Equal0~5_combout\,
- datac => \inst2|Equal0~9_combout\,
- datad => \inst2|Add2~24_combout\,
- combout => \inst2|s_counter~8_combout\);
-
--- Location: FF_X56_Y72_N21
-\inst2|s_counter[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|s_counter~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(12));
-
--- Location: LCCOMB_X56_Y72_N8
-\inst2|Equal0~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Equal0~2_combout\ = (\inst2|s_counter\(11) & (\inst2|s_counter\(12) & (!\inst2|s_counter\(8) & !\inst2|s_counter\(9))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(11),
- datab => \inst2|s_counter\(12),
- datac => \inst2|s_counter\(8),
- datad => \inst2|s_counter\(9),
- combout => \inst2|Equal0~2_combout\);
-
--- Location: LCCOMB_X55_Y72_N26
-\inst2|Add2~26\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~26_combout\ = (\inst2|s_counter\(13) & (!\inst2|Add2~25\)) # (!\inst2|s_counter\(13) & ((\inst2|Add2~25\) # (GND)))
--- \inst2|Add2~27\ = CARRY((!\inst2|Add2~25\) # (!\inst2|s_counter\(13)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(13),
- datad => VCC,
- cin => \inst2|Add2~25\,
- combout => \inst2|Add2~26_combout\,
- cout => \inst2|Add2~27\);
-
--- Location: LCCOMB_X56_Y72_N16
-\inst2|s_counter~7\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|s_counter~7_combout\ = (\inst2|Add2~26_combout\ & ((!\inst2|Equal0~5_combout\) # (!\inst2|Equal0~9_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011000011110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|Equal0~9_combout\,
- datac => \inst2|Add2~26_combout\,
- datad => \inst2|Equal0~5_combout\,
- combout => \inst2|s_counter~7_combout\);
-
--- Location: FF_X56_Y72_N17
-\inst2|s_counter[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|s_counter~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(13));
-
--- Location: LCCOMB_X55_Y72_N28
-\inst2|Add2~28\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~28_combout\ = (\inst2|s_counter\(14) & (\inst2|Add2~27\ $ (GND))) # (!\inst2|s_counter\(14) & (!\inst2|Add2~27\ & VCC))
--- \inst2|Add2~29\ = CARRY((\inst2|s_counter\(14) & !\inst2|Add2~27\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010010100001010",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(14),
- datad => VCC,
- cin => \inst2|Add2~27\,
- combout => \inst2|Add2~28_combout\,
- cout => \inst2|Add2~29\);
-
--- Location: LCCOMB_X56_Y71_N14
-\inst2|s_counter~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|s_counter~5_combout\ = (\inst2|Add2~28_combout\ & ((!\inst2|Equal0~5_combout\) # (!\inst2|Equal0~9_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011000011110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|Equal0~9_combout\,
- datac => \inst2|Add2~28_combout\,
- datad => \inst2|Equal0~5_combout\,
- combout => \inst2|s_counter~5_combout\);
-
--- Location: FF_X56_Y71_N15
-\inst2|s_counter[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|s_counter~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(14));
-
--- Location: LCCOMB_X55_Y72_N30
-\inst2|Add2~30\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~30_combout\ = (\inst2|s_counter\(15) & (!\inst2|Add2~29\)) # (!\inst2|s_counter\(15) & ((\inst2|Add2~29\) # (GND)))
--- \inst2|Add2~31\ = CARRY((!\inst2|Add2~29\) # (!\inst2|s_counter\(15)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(15),
- datad => VCC,
- cin => \inst2|Add2~29\,
- combout => \inst2|Add2~30_combout\,
- cout => \inst2|Add2~31\);
-
--- Location: FF_X55_Y72_N31
-\inst2|s_counter[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~30_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(15));
-
--- Location: LCCOMB_X55_Y71_N0
-\inst2|Add2~32\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~32_combout\ = (\inst2|s_counter\(16) & (\inst2|Add2~31\ $ (GND))) # (!\inst2|s_counter\(16) & (!\inst2|Add2~31\ & VCC))
--- \inst2|Add2~33\ = CARRY((\inst2|s_counter\(16) & !\inst2|Add2~31\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010010100001010",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(16),
- datad => VCC,
- cin => \inst2|Add2~31\,
- combout => \inst2|Add2~32_combout\,
- cout => \inst2|Add2~33\);
-
--- Location: LCCOMB_X56_Y71_N2
-\inst2|s_counter~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|s_counter~4_combout\ = (\inst2|Add2~32_combout\ & ((!\inst2|Equal0~5_combout\) # (!\inst2|Equal0~9_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011000011110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|Equal0~9_combout\,
- datac => \inst2|Add2~32_combout\,
- datad => \inst2|Equal0~5_combout\,
- combout => \inst2|s_counter~4_combout\);
-
--- Location: FF_X56_Y71_N3
-\inst2|s_counter[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|s_counter~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(16));
-
--- Location: LCCOMB_X55_Y71_N2
-\inst2|Add2~34\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~34_combout\ = (\inst2|s_counter\(17) & (!\inst2|Add2~33\)) # (!\inst2|s_counter\(17) & ((\inst2|Add2~33\) # (GND)))
--- \inst2|Add2~35\ = CARRY((!\inst2|Add2~33\) # (!\inst2|s_counter\(17)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(17),
- datad => VCC,
- cin => \inst2|Add2~33\,
- combout => \inst2|Add2~34_combout\,
- cout => \inst2|Add2~35\);
-
--- Location: FF_X55_Y71_N3
-\inst2|s_counter[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(17));
-
--- Location: LCCOMB_X55_Y71_N4
-\inst2|Add2~36\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~36_combout\ = (\inst2|s_counter\(18) & (\inst2|Add2~35\ $ (GND))) # (!\inst2|s_counter\(18) & (!\inst2|Add2~35\ & VCC))
--- \inst2|Add2~37\ = CARRY((\inst2|s_counter\(18) & !\inst2|Add2~35\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(18),
- datad => VCC,
- cin => \inst2|Add2~35\,
- combout => \inst2|Add2~36_combout\,
- cout => \inst2|Add2~37\);
-
--- Location: LCCOMB_X56_Y72_N30
-\inst2|s_counter~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|s_counter~6_combout\ = (\inst2|Add2~36_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011111100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|Equal0~5_combout\,
- datac => \inst2|Equal0~9_combout\,
- datad => \inst2|Add2~36_combout\,
- combout => \inst2|s_counter~6_combout\);
-
--- Location: FF_X56_Y72_N31
-\inst2|s_counter[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|s_counter~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(18));
-
--- Location: LCCOMB_X55_Y71_N12
-\inst2|Add2~44\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~44_combout\ = (\inst2|s_counter\(22) & (\inst2|Add2~43\ $ (GND))) # (!\inst2|s_counter\(22) & (!\inst2|Add2~43\ & VCC))
--- \inst2|Add2~45\ = CARRY((\inst2|s_counter\(22) & !\inst2|Add2~43\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1010010100001010",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(22),
- datad => VCC,
- cin => \inst2|Add2~43\,
- combout => \inst2|Add2~44_combout\,
- cout => \inst2|Add2~45\);
-
--- Location: LCCOMB_X55_Y71_N14
-\inst2|Add2~46\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~46_combout\ = (\inst2|s_counter\(23) & (!\inst2|Add2~45\)) # (!\inst2|s_counter\(23) & ((\inst2|Add2~45\) # (GND)))
--- \inst2|Add2~47\ = CARRY((!\inst2|Add2~45\) # (!\inst2|s_counter\(23)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110000111111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(23),
- datad => VCC,
- cin => \inst2|Add2~45\,
- combout => \inst2|Add2~46_combout\,
- cout => \inst2|Add2~47\);
-
--- Location: LCCOMB_X56_Y71_N18
-\inst2|s_counter~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|s_counter~1_combout\ = (\inst2|Add2~46_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011111100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|Equal0~5_combout\,
- datac => \inst2|Equal0~9_combout\,
- datad => \inst2|Add2~46_combout\,
- combout => \inst2|s_counter~1_combout\);
-
--- Location: FF_X56_Y71_N19
-\inst2|s_counter[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|s_counter~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(23));
-
--- Location: LCCOMB_X55_Y71_N16
-\inst2|Add2~48\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~48_combout\ = (\inst2|s_counter\(24) & (\inst2|Add2~47\ $ (GND))) # (!\inst2|s_counter\(24) & (!\inst2|Add2~47\ & VCC))
--- \inst2|Add2~49\ = CARRY((\inst2|s_counter\(24) & !\inst2|Add2~47\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(24),
- datad => VCC,
- cin => \inst2|Add2~47\,
- combout => \inst2|Add2~48_combout\,
- cout => \inst2|Add2~49\);
-
--- Location: FF_X55_Y71_N17
-\inst2|s_counter[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~48_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(24));
-
--- Location: LCCOMB_X55_Y71_N18
-\inst2|Add2~50\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~50_combout\ = (\inst2|s_counter\(25) & (!\inst2|Add2~49\)) # (!\inst2|s_counter\(25) & ((\inst2|Add2~49\) # (GND)))
--- \inst2|Add2~51\ = CARRY((!\inst2|Add2~49\) # (!\inst2|s_counter\(25)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(25),
- datad => VCC,
- cin => \inst2|Add2~49\,
- combout => \inst2|Add2~50_combout\,
- cout => \inst2|Add2~51\);
-
--- Location: LCCOMB_X56_Y71_N20
-\inst2|s_counter~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|s_counter~0_combout\ = (\inst2|Add2~50_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011111100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|Equal0~5_combout\,
- datac => \inst2|Equal0~9_combout\,
- datad => \inst2|Add2~50_combout\,
- combout => \inst2|s_counter~0_combout\);
-
--- Location: FF_X56_Y71_N21
-\inst2|s_counter[25]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|s_counter~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(25));
-
--- Location: LCCOMB_X55_Y71_N20
-\inst2|Add2~52\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~52_combout\ = (\inst2|s_counter\(26) & (\inst2|Add2~51\ $ (GND))) # (!\inst2|s_counter\(26) & (!\inst2|Add2~51\ & VCC))
--- \inst2|Add2~53\ = CARRY((\inst2|s_counter\(26) & !\inst2|Add2~51\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(26),
- datad => VCC,
- cin => \inst2|Add2~51\,
- combout => \inst2|Add2~52_combout\,
- cout => \inst2|Add2~53\);
-
--- Location: FF_X55_Y71_N21
-\inst2|s_counter[26]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~52_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(26));
-
--- Location: LCCOMB_X55_Y71_N22
-\inst2|Add2~54\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~54_combout\ = (\inst2|s_counter\(27) & (!\inst2|Add2~53\)) # (!\inst2|s_counter\(27) & ((\inst2|Add2~53\) # (GND)))
--- \inst2|Add2~55\ = CARRY((!\inst2|Add2~53\) # (!\inst2|s_counter\(27)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(27),
- datad => VCC,
- cin => \inst2|Add2~53\,
- combout => \inst2|Add2~54_combout\,
- cout => \inst2|Add2~55\);
-
--- Location: FF_X55_Y71_N23
-\inst2|s_counter[27]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~54_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(27));
-
--- Location: LCCOMB_X56_Y72_N14
-\inst2|Equal0~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Equal0~1_combout\ = (\inst2|s_counter\(18) & (\inst2|s_counter\(13) & (!\inst2|s_counter\(27) & !\inst2|s_counter\(26))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(18),
- datab => \inst2|s_counter\(13),
- datac => \inst2|s_counter\(27),
- datad => \inst2|s_counter\(26),
- combout => \inst2|Equal0~1_combout\);
-
--- Location: LCCOMB_X55_Y71_N24
-\inst2|Add2~56\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~56_combout\ = (\inst2|s_counter\(28) & (\inst2|Add2~55\ $ (GND))) # (!\inst2|s_counter\(28) & (!\inst2|Add2~55\ & VCC))
--- \inst2|Add2~57\ = CARRY((\inst2|s_counter\(28) & !\inst2|Add2~55\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(28),
- datad => VCC,
- cin => \inst2|Add2~55\,
- combout => \inst2|Add2~56_combout\,
- cout => \inst2|Add2~57\);
-
--- Location: FF_X55_Y71_N25
-\inst2|s_counter[28]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~56_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(28));
-
--- Location: LCCOMB_X55_Y71_N26
-\inst2|Add2~58\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~58_combout\ = (\inst2|s_counter\(29) & (!\inst2|Add2~57\)) # (!\inst2|s_counter\(29) & ((\inst2|Add2~57\) # (GND)))
--- \inst2|Add2~59\ = CARRY((!\inst2|Add2~57\) # (!\inst2|s_counter\(29)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(29),
- datad => VCC,
- cin => \inst2|Add2~57\,
- combout => \inst2|Add2~58_combout\,
- cout => \inst2|Add2~59\);
-
--- Location: FF_X55_Y71_N27
-\inst2|s_counter[29]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~58_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(29));
-
--- Location: LCCOMB_X55_Y71_N28
-\inst2|Add2~60\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~60_combout\ = (\inst2|s_counter\(30) & (\inst2|Add2~59\ $ (GND))) # (!\inst2|s_counter\(30) & (!\inst2|Add2~59\ & VCC))
--- \inst2|Add2~61\ = CARRY((\inst2|s_counter\(30) & !\inst2|Add2~59\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(30),
- datad => VCC,
- cin => \inst2|Add2~59\,
- combout => \inst2|Add2~60_combout\,
- cout => \inst2|Add2~61\);
-
--- Location: FF_X55_Y71_N29
-\inst2|s_counter[30]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~60_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(30));
-
--- Location: LCCOMB_X55_Y71_N30
-\inst2|Add2~62\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~62_combout\ = \inst2|s_counter\(31) $ (\inst2|Add2~61\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011010",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(31),
- cin => \inst2|Add2~61\,
- combout => \inst2|Add2~62_combout\);
-
--- Location: FF_X55_Y71_N31
-\inst2|s_counter[31]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~62_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(31));
-
--- Location: LCCOMB_X56_Y72_N24
-\inst2|Equal0~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Equal0~0_combout\ = (!\inst2|s_counter\(29) & (!\inst2|s_counter\(30) & (!\inst2|s_counter\(28) & !\inst2|s_counter\(31))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000000001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(29),
- datab => \inst2|s_counter\(30),
- datac => \inst2|s_counter\(28),
- datad => \inst2|s_counter\(31),
- combout => \inst2|Equal0~0_combout\);
-
--- Location: LCCOMB_X56_Y72_N18
-\inst2|Equal0~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Equal0~4_combout\ = (\inst2|Equal0~3_combout\ & (\inst2|Equal0~2_combout\ & (\inst2|Equal0~1_combout\ & \inst2|Equal0~0_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|Equal0~3_combout\,
- datab => \inst2|Equal0~2_combout\,
- datac => \inst2|Equal0~1_combout\,
- datad => \inst2|Equal0~0_combout\,
- combout => \inst2|Equal0~4_combout\);
-
--- Location: LCCOMB_X56_Y72_N28
-\inst2|Equal0~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Equal0~5_combout\ = (\inst2|s_counter\(0) & (\inst2|s_counter\(1) & (\inst2|s_counter\(2) & \inst2|Equal0~4_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(0),
- datab => \inst2|s_counter\(1),
- datac => \inst2|s_counter\(2),
- datad => \inst2|Equal0~4_combout\,
- combout => \inst2|Equal0~5_combout\);
-
--- Location: LCCOMB_X55_Y71_N6
-\inst2|Add2~38\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~38_combout\ = (\inst2|s_counter\(19) & (!\inst2|Add2~37\)) # (!\inst2|s_counter\(19) & ((\inst2|Add2~37\) # (GND)))
--- \inst2|Add2~39\ = CARRY((!\inst2|Add2~37\) # (!\inst2|s_counter\(19)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(19),
- datad => VCC,
- cin => \inst2|Add2~37\,
- combout => \inst2|Add2~38_combout\,
- cout => \inst2|Add2~39\);
-
--- Location: LCCOMB_X55_Y71_N8
-\inst2|Add2~40\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~40_combout\ = (\inst2|s_counter\(20) & (\inst2|Add2~39\ $ (GND))) # (!\inst2|s_counter\(20) & (!\inst2|Add2~39\ & VCC))
--- \inst2|Add2~41\ = CARRY((\inst2|s_counter\(20) & !\inst2|Add2~39\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100001100001100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|s_counter\(20),
- datad => VCC,
- cin => \inst2|Add2~39\,
- combout => \inst2|Add2~40_combout\,
- cout => \inst2|Add2~41\);
-
--- Location: FF_X55_Y71_N9
-\inst2|s_counter[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~40_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(20));
-
--- Location: LCCOMB_X55_Y71_N10
-\inst2|Add2~42\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Add2~42_combout\ = (\inst2|s_counter\(21) & (!\inst2|Add2~41\)) # (!\inst2|s_counter\(21) & ((\inst2|Add2~41\) # (GND)))
--- \inst2|Add2~43\ = CARRY((!\inst2|Add2~41\) # (!\inst2|s_counter\(21)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(21),
- datad => VCC,
- cin => \inst2|Add2~41\,
- combout => \inst2|Add2~42_combout\,
- cout => \inst2|Add2~43\);
-
--- Location: LCCOMB_X56_Y71_N30
-\inst2|s_counter~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|s_counter~2_combout\ = (\inst2|Add2~42_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011111100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|Equal0~5_combout\,
- datac => \inst2|Equal0~9_combout\,
- datad => \inst2|Add2~42_combout\,
- combout => \inst2|s_counter~2_combout\);
-
--- Location: FF_X56_Y71_N31
-\inst2|s_counter[21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|s_counter~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(21));
-
--- Location: FF_X55_Y71_N13
-\inst2|s_counter[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|Add2~44_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(22));
-
--- Location: LCCOMB_X56_Y71_N12
-\inst2|Equal0~6\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Equal0~6_combout\ = (!\inst2|s_counter\(22) & (\inst2|s_counter\(25) & (!\inst2|s_counter\(24) & \inst2|s_counter\(23))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000010000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(22),
- datab => \inst2|s_counter\(25),
- datac => \inst2|s_counter\(24),
- datad => \inst2|s_counter\(23),
- combout => \inst2|Equal0~6_combout\);
-
--- Location: LCCOMB_X56_Y71_N16
-\inst2|Equal0~7\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Equal0~7_combout\ = (\inst2|s_counter\(19) & (\inst2|s_counter\(21) & (!\inst2|s_counter\(20) & !\inst2|s_counter\(17))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(19),
- datab => \inst2|s_counter\(21),
- datac => \inst2|s_counter\(20),
- datad => \inst2|s_counter\(17),
- combout => \inst2|Equal0~7_combout\);
-
--- Location: LCCOMB_X56_Y71_N24
-\inst2|Equal0~8\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Equal0~8_combout\ = (!\inst2|s_counter\(15) & (\inst2|s_counter\(16) & (\inst2|s_counter\(14) & !\inst2|s_counter\(10))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000001000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(15),
- datab => \inst2|s_counter\(16),
- datac => \inst2|s_counter\(14),
- datad => \inst2|s_counter\(10),
- combout => \inst2|Equal0~8_combout\);
-
--- Location: LCCOMB_X56_Y71_N8
-\inst2|Equal0~9\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|Equal0~9_combout\ = (\inst2|Equal0~6_combout\ & (\inst2|Equal0~7_combout\ & (\inst2|s_counter\(5) & \inst2|Equal0~8_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|Equal0~6_combout\,
- datab => \inst2|Equal0~7_combout\,
- datac => \inst2|s_counter\(5),
- datad => \inst2|Equal0~8_combout\,
- combout => \inst2|Equal0~9_combout\);
-
--- Location: LCCOMB_X56_Y71_N6
-\inst2|s_counter~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|s_counter~3_combout\ = (\inst2|Add2~38_combout\ & ((!\inst2|Equal0~5_combout\) # (!\inst2|Equal0~9_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011000011110000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datab => \inst2|Equal0~9_combout\,
- datac => \inst2|Add2~38_combout\,
- datad => \inst2|Equal0~5_combout\,
- combout => \inst2|s_counter~3_combout\);
-
--- Location: FF_X56_Y71_N7
-\inst2|s_counter[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- d => \inst2|s_counter~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|s_counter\(19));
-
--- Location: LCCOMB_X56_Y71_N4
-\inst2|clkOut~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|clkOut~1_combout\ = (!\inst2|s_counter\(19) & (!\inst2|s_counter\(21) & (\inst2|s_counter\(20) & \inst2|s_counter\(17))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0001000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(19),
- datab => \inst2|s_counter\(21),
- datac => \inst2|s_counter\(20),
- datad => \inst2|s_counter\(17),
- combout => \inst2|clkOut~1_combout\);
-
--- Location: LCCOMB_X56_Y71_N28
-\inst2|clkOut~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|clkOut~2_combout\ = (\inst2|s_counter\(15) & (\inst2|s_counter\(10) & (!\inst2|s_counter\(14) & !\inst2|s_counter\(16))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(15),
- datab => \inst2|s_counter\(10),
- datac => \inst2|s_counter\(14),
- datad => \inst2|s_counter\(16),
- combout => \inst2|clkOut~2_combout\);
-
--- Location: LCCOMB_X56_Y71_N10
-\inst2|clkOut~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|clkOut~0_combout\ = (\inst2|s_counter\(22) & (!\inst2|s_counter\(25) & (\inst2|s_counter\(24) & !\inst2|s_counter\(23))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000100000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|s_counter\(22),
- datab => \inst2|s_counter\(25),
- datac => \inst2|s_counter\(24),
- datad => \inst2|s_counter\(23),
- combout => \inst2|clkOut~0_combout\);
-
--- Location: LCCOMB_X56_Y71_N26
-\inst2|clkOut~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|clkOut~3_combout\ = (\inst2|clkOut~1_combout\ & (\inst2|clkOut~2_combout\ & (!\inst2|s_counter\(5) & \inst2|clkOut~0_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000100000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|clkOut~1_combout\,
- datab => \inst2|clkOut~2_combout\,
- datac => \inst2|s_counter\(5),
- datad => \inst2|clkOut~0_combout\,
- combout => \inst2|clkOut~3_combout\);
-
--- Location: LCCOMB_X56_Y71_N0
-\inst2|clkOut~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst2|clkOut~4_combout\ = (\inst2|Equal0~5_combout\ & (!\inst2|Equal0~9_combout\ & ((\inst2|clkOut~3_combout\) # (\inst2|clkOut~q\)))) # (!\inst2|Equal0~5_combout\ & (((\inst2|clkOut~q\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000111011001100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst2|clkOut~3_combout\,
- datab => \inst2|clkOut~q\,
- datac => \inst2|Equal0~9_combout\,
- datad => \inst2|Equal0~5_combout\,
- combout => \inst2|clkOut~4_combout\);
-
--- Location: FF_X56_Y71_N23
-\inst2|clkOut\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \CLOCK_50~inputclkctrl_outclk\,
- asdata => \inst2|clkOut~4_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst2|clkOut~q\);
-
--- Location: CLKCTRL_G12
-\inst2|clkOut~clkctrl\ : cycloneive_clkctrl
--- pragma translate_off
-GENERIC MAP (
- clock_type => "global clock",
- ena_register_mode => "none")
--- pragma translate_on
-PORT MAP (
- inclk => \inst2|clkOut~clkctrl_INCLK_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- outclk => \inst2|clkOut~clkctrl_outclk\);
-
--- Location: IOIBUF_X115_Y13_N1
-\SW[16]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(16),
- o => \SW[16]~input_o\);
-
--- Location: IOIBUF_X115_Y6_N15
-\SW[15]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(15),
- o => \SW[15]~input_o\);
-
--- Location: IOIBUF_X115_Y10_N8
-\SW[14]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(14),
- o => \SW[14]~input_o\);
-
--- Location: IOIBUF_X115_Y9_N22
-\SW[13]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(13),
- o => \SW[13]~input_o\);
-
--- Location: IOIBUF_X115_Y7_N15
-\SW[12]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(12),
- o => \SW[12]~input_o\);
-
--- Location: IOIBUF_X115_Y5_N15
-\SW[11]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(11),
- o => \SW[11]~input_o\);
-
--- Location: IOIBUF_X115_Y4_N15
-\SW[10]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(10),
- o => \SW[10]~input_o\);
-
--- Location: IOIBUF_X115_Y16_N8
-\SW[9]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(9),
- o => \SW[9]~input_o\);
-
--- Location: IOIBUF_X115_Y4_N22
-\SW[8]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(8),
- o => \SW[8]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N1
-\SW[7]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(7),
- o => \SW[7]~input_o\);
-
--- Location: IOIBUF_X115_Y10_N1
-\SW[6]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(6),
- o => \SW[6]~input_o\);
-
--- Location: IOIBUF_X115_Y11_N8
-\SW[5]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(5),
- o => \SW[5]~input_o\);
-
--- Location: IOIBUF_X115_Y18_N8
-\SW[4]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(4),
- o => \SW[4]~input_o\);
-
--- Location: IOIBUF_X115_Y13_N8
-\SW[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(3),
- o => \SW[3]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N8
-\SW[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(2),
- o => \SW[2]~input_o\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: LCCOMB_X114_Y42_N16
-\inst|reg|dataOut[0]~17\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[0]~17_combout\ = (\SW[0]~input_o\ & (\inst|reg|dataOut\(0) $ (VCC))) # (!\SW[0]~input_o\ & (\inst|reg|dataOut\(0) & VCC))
--- \inst|reg|dataOut[0]~18\ = CARRY((\SW[0]~input_o\ & \inst|reg|dataOut\(0)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110011010001000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[0]~input_o\,
- datab => \inst|reg|dataOut\(0),
- datad => VCC,
- combout => \inst|reg|dataOut[0]~17_combout\,
- cout => \inst|reg|dataOut[0]~18\);
-
--- Location: IOIBUF_X115_Y53_N15
-\KEY[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY(1),
- o => \KEY[1]~input_o\);
-
--- Location: IOIBUF_X115_Y14_N8
-\SW[17]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(17),
- o => \SW[17]~input_o\);
-
--- Location: FF_X114_Y42_N17
-\inst|reg|dataOut[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[0]~17_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(0));
-
--- Location: LCCOMB_X114_Y42_N18
-\inst|reg|dataOut[1]~19\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[1]~19_combout\ = (\SW[1]~input_o\ & ((\inst|reg|dataOut\(1) & (\inst|reg|dataOut[0]~18\ & VCC)) # (!\inst|reg|dataOut\(1) & (!\inst|reg|dataOut[0]~18\)))) # (!\SW[1]~input_o\ & ((\inst|reg|dataOut\(1) & (!\inst|reg|dataOut[0]~18\)) #
--- (!\inst|reg|dataOut\(1) & ((\inst|reg|dataOut[0]~18\) # (GND)))))
--- \inst|reg|dataOut[1]~20\ = CARRY((\SW[1]~input_o\ & (!\inst|reg|dataOut\(1) & !\inst|reg|dataOut[0]~18\)) # (!\SW[1]~input_o\ & ((!\inst|reg|dataOut[0]~18\) # (!\inst|reg|dataOut\(1)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[1]~input_o\,
- datab => \inst|reg|dataOut\(1),
- datad => VCC,
- cin => \inst|reg|dataOut[0]~18\,
- combout => \inst|reg|dataOut[1]~19_combout\,
- cout => \inst|reg|dataOut[1]~20\);
-
--- Location: FF_X114_Y42_N19
-\inst|reg|dataOut[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[1]~19_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(1));
-
--- Location: LCCOMB_X114_Y42_N20
-\inst|reg|dataOut[2]~21\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[2]~21_combout\ = ((\SW[2]~input_o\ $ (\inst|reg|dataOut\(2) $ (!\inst|reg|dataOut[1]~20\)))) # (GND)
--- \inst|reg|dataOut[2]~22\ = CARRY((\SW[2]~input_o\ & ((\inst|reg|dataOut\(2)) # (!\inst|reg|dataOut[1]~20\))) # (!\SW[2]~input_o\ & (\inst|reg|dataOut\(2) & !\inst|reg|dataOut[1]~20\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[2]~input_o\,
- datab => \inst|reg|dataOut\(2),
- datad => VCC,
- cin => \inst|reg|dataOut[1]~20\,
- combout => \inst|reg|dataOut[2]~21_combout\,
- cout => \inst|reg|dataOut[2]~22\);
-
--- Location: FF_X114_Y42_N21
-\inst|reg|dataOut[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[2]~21_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(2));
-
--- Location: LCCOMB_X114_Y42_N22
-\inst|reg|dataOut[3]~23\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[3]~23_combout\ = (\inst|reg|dataOut\(3) & ((\SW[3]~input_o\ & (\inst|reg|dataOut[2]~22\ & VCC)) # (!\SW[3]~input_o\ & (!\inst|reg|dataOut[2]~22\)))) # (!\inst|reg|dataOut\(3) & ((\SW[3]~input_o\ & (!\inst|reg|dataOut[2]~22\)) #
--- (!\SW[3]~input_o\ & ((\inst|reg|dataOut[2]~22\) # (GND)))))
--- \inst|reg|dataOut[3]~24\ = CARRY((\inst|reg|dataOut\(3) & (!\SW[3]~input_o\ & !\inst|reg|dataOut[2]~22\)) # (!\inst|reg|dataOut\(3) & ((!\inst|reg|dataOut[2]~22\) # (!\SW[3]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|reg|dataOut\(3),
- datab => \SW[3]~input_o\,
- datad => VCC,
- cin => \inst|reg|dataOut[2]~22\,
- combout => \inst|reg|dataOut[3]~23_combout\,
- cout => \inst|reg|dataOut[3]~24\);
-
--- Location: FF_X114_Y42_N23
-\inst|reg|dataOut[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[3]~23_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(3));
-
--- Location: LCCOMB_X114_Y42_N24
-\inst|reg|dataOut[4]~25\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[4]~25_combout\ = ((\SW[4]~input_o\ $ (\inst|reg|dataOut\(4) $ (!\inst|reg|dataOut[3]~24\)))) # (GND)
--- \inst|reg|dataOut[4]~26\ = CARRY((\SW[4]~input_o\ & ((\inst|reg|dataOut\(4)) # (!\inst|reg|dataOut[3]~24\))) # (!\SW[4]~input_o\ & (\inst|reg|dataOut\(4) & !\inst|reg|dataOut[3]~24\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[4]~input_o\,
- datab => \inst|reg|dataOut\(4),
- datad => VCC,
- cin => \inst|reg|dataOut[3]~24\,
- combout => \inst|reg|dataOut[4]~25_combout\,
- cout => \inst|reg|dataOut[4]~26\);
-
--- Location: FF_X114_Y42_N25
-\inst|reg|dataOut[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[4]~25_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(4));
-
--- Location: LCCOMB_X114_Y42_N26
-\inst|reg|dataOut[5]~27\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[5]~27_combout\ = (\inst|reg|dataOut\(5) & ((\SW[5]~input_o\ & (\inst|reg|dataOut[4]~26\ & VCC)) # (!\SW[5]~input_o\ & (!\inst|reg|dataOut[4]~26\)))) # (!\inst|reg|dataOut\(5) & ((\SW[5]~input_o\ & (!\inst|reg|dataOut[4]~26\)) #
--- (!\SW[5]~input_o\ & ((\inst|reg|dataOut[4]~26\) # (GND)))))
--- \inst|reg|dataOut[5]~28\ = CARRY((\inst|reg|dataOut\(5) & (!\SW[5]~input_o\ & !\inst|reg|dataOut[4]~26\)) # (!\inst|reg|dataOut\(5) & ((!\inst|reg|dataOut[4]~26\) # (!\SW[5]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|reg|dataOut\(5),
- datab => \SW[5]~input_o\,
- datad => VCC,
- cin => \inst|reg|dataOut[4]~26\,
- combout => \inst|reg|dataOut[5]~27_combout\,
- cout => \inst|reg|dataOut[5]~28\);
-
--- Location: FF_X114_Y42_N27
-\inst|reg|dataOut[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[5]~27_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(5));
-
--- Location: LCCOMB_X114_Y42_N28
-\inst|reg|dataOut[6]~29\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[6]~29_combout\ = ((\SW[6]~input_o\ $ (\inst|reg|dataOut\(6) $ (!\inst|reg|dataOut[5]~28\)))) # (GND)
--- \inst|reg|dataOut[6]~30\ = CARRY((\SW[6]~input_o\ & ((\inst|reg|dataOut\(6)) # (!\inst|reg|dataOut[5]~28\))) # (!\SW[6]~input_o\ & (\inst|reg|dataOut\(6) & !\inst|reg|dataOut[5]~28\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[6]~input_o\,
- datab => \inst|reg|dataOut\(6),
- datad => VCC,
- cin => \inst|reg|dataOut[5]~28\,
- combout => \inst|reg|dataOut[6]~29_combout\,
- cout => \inst|reg|dataOut[6]~30\);
-
--- Location: FF_X114_Y42_N29
-\inst|reg|dataOut[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[6]~29_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(6));
-
--- Location: LCCOMB_X114_Y42_N30
-\inst|reg|dataOut[7]~31\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[7]~31_combout\ = (\inst|reg|dataOut\(7) & ((\SW[7]~input_o\ & (\inst|reg|dataOut[6]~30\ & VCC)) # (!\SW[7]~input_o\ & (!\inst|reg|dataOut[6]~30\)))) # (!\inst|reg|dataOut\(7) & ((\SW[7]~input_o\ & (!\inst|reg|dataOut[6]~30\)) #
--- (!\SW[7]~input_o\ & ((\inst|reg|dataOut[6]~30\) # (GND)))))
--- \inst|reg|dataOut[7]~32\ = CARRY((\inst|reg|dataOut\(7) & (!\SW[7]~input_o\ & !\inst|reg|dataOut[6]~30\)) # (!\inst|reg|dataOut\(7) & ((!\inst|reg|dataOut[6]~30\) # (!\SW[7]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|reg|dataOut\(7),
- datab => \SW[7]~input_o\,
- datad => VCC,
- cin => \inst|reg|dataOut[6]~30\,
- combout => \inst|reg|dataOut[7]~31_combout\,
- cout => \inst|reg|dataOut[7]~32\);
-
--- Location: FF_X114_Y42_N31
-\inst|reg|dataOut[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[7]~31_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(7));
-
--- Location: LCCOMB_X114_Y41_N0
-\inst|reg|dataOut[8]~33\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[8]~33_combout\ = ((\SW[8]~input_o\ $ (\inst|reg|dataOut\(8) $ (!\inst|reg|dataOut[7]~32\)))) # (GND)
--- \inst|reg|dataOut[8]~34\ = CARRY((\SW[8]~input_o\ & ((\inst|reg|dataOut\(8)) # (!\inst|reg|dataOut[7]~32\))) # (!\SW[8]~input_o\ & (\inst|reg|dataOut\(8) & !\inst|reg|dataOut[7]~32\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[8]~input_o\,
- datab => \inst|reg|dataOut\(8),
- datad => VCC,
- cin => \inst|reg|dataOut[7]~32\,
- combout => \inst|reg|dataOut[8]~33_combout\,
- cout => \inst|reg|dataOut[8]~34\);
-
--- Location: FF_X114_Y41_N1
-\inst|reg|dataOut[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[8]~33_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(8));
-
--- Location: LCCOMB_X114_Y41_N2
-\inst|reg|dataOut[9]~35\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[9]~35_combout\ = (\SW[9]~input_o\ & ((\inst|reg|dataOut\(9) & (\inst|reg|dataOut[8]~34\ & VCC)) # (!\inst|reg|dataOut\(9) & (!\inst|reg|dataOut[8]~34\)))) # (!\SW[9]~input_o\ & ((\inst|reg|dataOut\(9) & (!\inst|reg|dataOut[8]~34\)) #
--- (!\inst|reg|dataOut\(9) & ((\inst|reg|dataOut[8]~34\) # (GND)))))
--- \inst|reg|dataOut[9]~36\ = CARRY((\SW[9]~input_o\ & (!\inst|reg|dataOut\(9) & !\inst|reg|dataOut[8]~34\)) # (!\SW[9]~input_o\ & ((!\inst|reg|dataOut[8]~34\) # (!\inst|reg|dataOut\(9)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[9]~input_o\,
- datab => \inst|reg|dataOut\(9),
- datad => VCC,
- cin => \inst|reg|dataOut[8]~34\,
- combout => \inst|reg|dataOut[9]~35_combout\,
- cout => \inst|reg|dataOut[9]~36\);
-
--- Location: FF_X114_Y41_N3
-\inst|reg|dataOut[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[9]~35_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(9));
-
--- Location: LCCOMB_X114_Y41_N4
-\inst|reg|dataOut[10]~37\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[10]~37_combout\ = ((\SW[10]~input_o\ $ (\inst|reg|dataOut\(10) $ (!\inst|reg|dataOut[9]~36\)))) # (GND)
--- \inst|reg|dataOut[10]~38\ = CARRY((\SW[10]~input_o\ & ((\inst|reg|dataOut\(10)) # (!\inst|reg|dataOut[9]~36\))) # (!\SW[10]~input_o\ & (\inst|reg|dataOut\(10) & !\inst|reg|dataOut[9]~36\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[10]~input_o\,
- datab => \inst|reg|dataOut\(10),
- datad => VCC,
- cin => \inst|reg|dataOut[9]~36\,
- combout => \inst|reg|dataOut[10]~37_combout\,
- cout => \inst|reg|dataOut[10]~38\);
-
--- Location: FF_X114_Y41_N5
-\inst|reg|dataOut[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[10]~37_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(10));
-
--- Location: LCCOMB_X114_Y41_N6
-\inst|reg|dataOut[11]~39\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[11]~39_combout\ = (\inst|reg|dataOut\(11) & ((\SW[11]~input_o\ & (\inst|reg|dataOut[10]~38\ & VCC)) # (!\SW[11]~input_o\ & (!\inst|reg|dataOut[10]~38\)))) # (!\inst|reg|dataOut\(11) & ((\SW[11]~input_o\ & (!\inst|reg|dataOut[10]~38\)) #
--- (!\SW[11]~input_o\ & ((\inst|reg|dataOut[10]~38\) # (GND)))))
--- \inst|reg|dataOut[11]~40\ = CARRY((\inst|reg|dataOut\(11) & (!\SW[11]~input_o\ & !\inst|reg|dataOut[10]~38\)) # (!\inst|reg|dataOut\(11) & ((!\inst|reg|dataOut[10]~38\) # (!\SW[11]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|reg|dataOut\(11),
- datab => \SW[11]~input_o\,
- datad => VCC,
- cin => \inst|reg|dataOut[10]~38\,
- combout => \inst|reg|dataOut[11]~39_combout\,
- cout => \inst|reg|dataOut[11]~40\);
-
--- Location: FF_X114_Y41_N7
-\inst|reg|dataOut[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[11]~39_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(11));
-
--- Location: LCCOMB_X114_Y41_N8
-\inst|reg|dataOut[12]~41\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[12]~41_combout\ = ((\SW[12]~input_o\ $ (\inst|reg|dataOut\(12) $ (!\inst|reg|dataOut[11]~40\)))) # (GND)
--- \inst|reg|dataOut[12]~42\ = CARRY((\SW[12]~input_o\ & ((\inst|reg|dataOut\(12)) # (!\inst|reg|dataOut[11]~40\))) # (!\SW[12]~input_o\ & (\inst|reg|dataOut\(12) & !\inst|reg|dataOut[11]~40\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[12]~input_o\,
- datab => \inst|reg|dataOut\(12),
- datad => VCC,
- cin => \inst|reg|dataOut[11]~40\,
- combout => \inst|reg|dataOut[12]~41_combout\,
- cout => \inst|reg|dataOut[12]~42\);
-
--- Location: FF_X114_Y41_N9
-\inst|reg|dataOut[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[12]~41_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(12));
-
--- Location: LCCOMB_X114_Y41_N10
-\inst|reg|dataOut[13]~43\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[13]~43_combout\ = (\inst|reg|dataOut\(13) & ((\SW[13]~input_o\ & (\inst|reg|dataOut[12]~42\ & VCC)) # (!\SW[13]~input_o\ & (!\inst|reg|dataOut[12]~42\)))) # (!\inst|reg|dataOut\(13) & ((\SW[13]~input_o\ & (!\inst|reg|dataOut[12]~42\)) #
--- (!\SW[13]~input_o\ & ((\inst|reg|dataOut[12]~42\) # (GND)))))
--- \inst|reg|dataOut[13]~44\ = CARRY((\inst|reg|dataOut\(13) & (!\SW[13]~input_o\ & !\inst|reg|dataOut[12]~42\)) # (!\inst|reg|dataOut\(13) & ((!\inst|reg|dataOut[12]~42\) # (!\SW[13]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|reg|dataOut\(13),
- datab => \SW[13]~input_o\,
- datad => VCC,
- cin => \inst|reg|dataOut[12]~42\,
- combout => \inst|reg|dataOut[13]~43_combout\,
- cout => \inst|reg|dataOut[13]~44\);
-
--- Location: FF_X114_Y41_N11
-\inst|reg|dataOut[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[13]~43_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(13));
-
--- Location: LCCOMB_X114_Y41_N12
-\inst|reg|dataOut[14]~45\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[14]~45_combout\ = ((\inst|reg|dataOut\(14) $ (\SW[14]~input_o\ $ (!\inst|reg|dataOut[13]~44\)))) # (GND)
--- \inst|reg|dataOut[14]~46\ = CARRY((\inst|reg|dataOut\(14) & ((\SW[14]~input_o\) # (!\inst|reg|dataOut[13]~44\))) # (!\inst|reg|dataOut\(14) & (\SW[14]~input_o\ & !\inst|reg|dataOut[13]~44\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0110100110001110",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|reg|dataOut\(14),
- datab => \SW[14]~input_o\,
- datad => VCC,
- cin => \inst|reg|dataOut[13]~44\,
- combout => \inst|reg|dataOut[14]~45_combout\,
- cout => \inst|reg|dataOut[14]~46\);
-
--- Location: FF_X114_Y41_N13
-\inst|reg|dataOut[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[14]~45_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(14));
-
--- Location: LCCOMB_X114_Y41_N14
-\inst|reg|dataOut[15]~47\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[15]~47_combout\ = (\SW[15]~input_o\ & ((\inst|reg|dataOut\(15) & (\inst|reg|dataOut[14]~46\ & VCC)) # (!\inst|reg|dataOut\(15) & (!\inst|reg|dataOut[14]~46\)))) # (!\SW[15]~input_o\ & ((\inst|reg|dataOut\(15) &
--- (!\inst|reg|dataOut[14]~46\)) # (!\inst|reg|dataOut\(15) & ((\inst|reg|dataOut[14]~46\) # (GND)))))
--- \inst|reg|dataOut[15]~48\ = CARRY((\SW[15]~input_o\ & (!\inst|reg|dataOut\(15) & !\inst|reg|dataOut[14]~46\)) # (!\SW[15]~input_o\ & ((!\inst|reg|dataOut[14]~46\) # (!\inst|reg|dataOut\(15)))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001011000010111",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[15]~input_o\,
- datab => \inst|reg|dataOut\(15),
- datad => VCC,
- cin => \inst|reg|dataOut[14]~46\,
- combout => \inst|reg|dataOut[15]~47_combout\,
- cout => \inst|reg|dataOut[15]~48\);
-
--- Location: FF_X114_Y41_N15
-\inst|reg|dataOut[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[15]~47_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(15));
-
--- Location: LCCOMB_X114_Y41_N16
-\inst|reg|dataOut[16]~49\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|reg|dataOut[16]~49_combout\ = \inst|reg|dataOut\(16) $ (\inst|reg|dataOut[15]~48\ $ (!\SW[16]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0011110011000011",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- datab => \inst|reg|dataOut\(16),
- datad => \SW[16]~input_o\,
- cin => \inst|reg|dataOut[15]~48\,
- combout => \inst|reg|dataOut[16]~49_combout\);
-
--- Location: FF_X114_Y41_N17
-\inst|reg|dataOut[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \inst2|clkOut~clkctrl_outclk\,
- d => \inst|reg|dataOut[16]~49_combout\,
- clrn => \KEY[1]~input_o\,
- ena => \SW[17]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \inst|reg|dataOut\(16));
-
-ww_LEDR(16) <= \LEDR[16]~output_o\;
-
-ww_LEDR(15) <= \LEDR[15]~output_o\;
-
-ww_LEDR(14) <= \LEDR[14]~output_o\;
-
-ww_LEDR(13) <= \LEDR[13]~output_o\;
-
-ww_LEDR(12) <= \LEDR[12]~output_o\;
-
-ww_LEDR(11) <= \LEDR[11]~output_o\;
-
-ww_LEDR(10) <= \LEDR[10]~output_o\;
-
-ww_LEDR(9) <= \LEDR[9]~output_o\;
-
-ww_LEDR(8) <= \LEDR[8]~output_o\;
-
-ww_LEDR(7) <= \LEDR[7]~output_o\;
-
-ww_LEDR(6) <= \LEDR[6]~output_o\;
-
-ww_LEDR(5) <= \LEDR[5]~output_o\;
-
-ww_LEDR(4) <= \LEDR[4]~output_o\;
-
-ww_LEDR(3) <= \LEDR[3]~output_o\;
-
-ww_LEDR(2) <= \LEDR[2]~output_o\;
-
-ww_LEDR(1) <= \LEDR[1]~output_o\;
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo_modelsim.xrf b/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo_modelsim.xrf
deleted file mode 100644
index e4c0284..0000000
--- a/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo_modelsim.xrf
+++ /dev/null
@@ -1,177 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cbx.xml
-design_name = hard_block
-design_name = AccN_Demo
-instance = comp, \LEDR[16]~output\, LEDR[16]~output, AccN_Demo, 1
-instance = comp, \LEDR[15]~output\, LEDR[15]~output, AccN_Demo, 1
-instance = comp, \LEDR[14]~output\, LEDR[14]~output, AccN_Demo, 1
-instance = comp, \LEDR[13]~output\, LEDR[13]~output, AccN_Demo, 1
-instance = comp, \LEDR[12]~output\, LEDR[12]~output, AccN_Demo, 1
-instance = comp, \LEDR[11]~output\, LEDR[11]~output, AccN_Demo, 1
-instance = comp, \LEDR[10]~output\, LEDR[10]~output, AccN_Demo, 1
-instance = comp, \LEDR[9]~output\, LEDR[9]~output, AccN_Demo, 1
-instance = comp, \LEDR[8]~output\, LEDR[8]~output, AccN_Demo, 1
-instance = comp, \LEDR[7]~output\, LEDR[7]~output, AccN_Demo, 1
-instance = comp, \LEDR[6]~output\, LEDR[6]~output, AccN_Demo, 1
-instance = comp, \LEDR[5]~output\, LEDR[5]~output, AccN_Demo, 1
-instance = comp, \LEDR[4]~output\, LEDR[4]~output, AccN_Demo, 1
-instance = comp, \LEDR[3]~output\, LEDR[3]~output, AccN_Demo, 1
-instance = comp, \LEDR[2]~output\, LEDR[2]~output, AccN_Demo, 1
-instance = comp, \LEDR[1]~output\, LEDR[1]~output, AccN_Demo, 1
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, AccN_Demo, 1
-instance = comp, \CLOCK_50~input\, CLOCK_50~input, AccN_Demo, 1
-instance = comp, \CLOCK_50~inputclkctrl\, CLOCK_50~inputclkctrl, AccN_Demo, 1
-instance = comp, \inst2|Add2~0\, inst2|Add2~0, AccN_Demo, 1
-instance = comp, \inst2|s_counter[0]\, inst2|s_counter[0], AccN_Demo, 1
-instance = comp, \inst2|Add2~2\, inst2|Add2~2, AccN_Demo, 1
-instance = comp, \inst2|s_counter[1]\, inst2|s_counter[1], AccN_Demo, 1
-instance = comp, \inst2|Add2~4\, inst2|Add2~4, AccN_Demo, 1
-instance = comp, \inst2|s_counter[2]\, inst2|s_counter[2], AccN_Demo, 1
-instance = comp, \inst2|Add2~6\, inst2|Add2~6, AccN_Demo, 1
-instance = comp, \inst2|s_counter[3]\, inst2|s_counter[3], AccN_Demo, 1
-instance = comp, \inst2|Add2~8\, inst2|Add2~8, AccN_Demo, 1
-instance = comp, \inst2|s_counter[4]\, inst2|s_counter[4], AccN_Demo, 1
-instance = comp, \inst2|Add2~10\, inst2|Add2~10, AccN_Demo, 1
-instance = comp, \inst2|s_counter[5]\, inst2|s_counter[5], AccN_Demo, 1
-instance = comp, \inst2|Add2~12\, inst2|Add2~12, AccN_Demo, 1
-instance = comp, \inst2|s_counter~10\, inst2|s_counter~10, AccN_Demo, 1
-instance = comp, \inst2|s_counter[6]\, inst2|s_counter[6], AccN_Demo, 1
-instance = comp, \inst2|Add2~14\, inst2|Add2~14, AccN_Demo, 1
-instance = comp, \inst2|s_counter[7]\, inst2|s_counter[7], AccN_Demo, 1
-instance = comp, \inst2|Equal0~3\, inst2|Equal0~3, AccN_Demo, 1
-instance = comp, \inst2|Add2~16\, inst2|Add2~16, AccN_Demo, 1
-instance = comp, \inst2|s_counter[8]\, inst2|s_counter[8], AccN_Demo, 1
-instance = comp, \inst2|Add2~18\, inst2|Add2~18, AccN_Demo, 1
-instance = comp, \inst2|s_counter[9]\, inst2|s_counter[9], AccN_Demo, 1
-instance = comp, \inst2|Add2~20\, inst2|Add2~20, AccN_Demo, 1
-instance = comp, \inst2|s_counter[10]\, inst2|s_counter[10], AccN_Demo, 1
-instance = comp, \inst2|Add2~22\, inst2|Add2~22, AccN_Demo, 1
-instance = comp, \inst2|s_counter~9\, inst2|s_counter~9, AccN_Demo, 1
-instance = comp, \inst2|s_counter[11]\, inst2|s_counter[11], AccN_Demo, 1
-instance = comp, \inst2|Add2~24\, inst2|Add2~24, AccN_Demo, 1
-instance = comp, \inst2|s_counter~8\, inst2|s_counter~8, AccN_Demo, 1
-instance = comp, \inst2|s_counter[12]\, inst2|s_counter[12], AccN_Demo, 1
-instance = comp, \inst2|Equal0~2\, inst2|Equal0~2, AccN_Demo, 1
-instance = comp, \inst2|Add2~26\, inst2|Add2~26, AccN_Demo, 1
-instance = comp, \inst2|s_counter~7\, inst2|s_counter~7, AccN_Demo, 1
-instance = comp, \inst2|s_counter[13]\, inst2|s_counter[13], AccN_Demo, 1
-instance = comp, \inst2|Add2~28\, inst2|Add2~28, AccN_Demo, 1
-instance = comp, \inst2|s_counter~5\, inst2|s_counter~5, AccN_Demo, 1
-instance = comp, \inst2|s_counter[14]\, inst2|s_counter[14], AccN_Demo, 1
-instance = comp, \inst2|Add2~30\, inst2|Add2~30, AccN_Demo, 1
-instance = comp, \inst2|s_counter[15]\, inst2|s_counter[15], AccN_Demo, 1
-instance = comp, \inst2|Add2~32\, inst2|Add2~32, AccN_Demo, 1
-instance = comp, \inst2|s_counter~4\, inst2|s_counter~4, AccN_Demo, 1
-instance = comp, \inst2|s_counter[16]\, inst2|s_counter[16], AccN_Demo, 1
-instance = comp, \inst2|Add2~34\, inst2|Add2~34, AccN_Demo, 1
-instance = comp, \inst2|s_counter[17]\, inst2|s_counter[17], AccN_Demo, 1
-instance = comp, \inst2|Add2~36\, inst2|Add2~36, AccN_Demo, 1
-instance = comp, \inst2|s_counter~6\, inst2|s_counter~6, AccN_Demo, 1
-instance = comp, \inst2|s_counter[18]\, inst2|s_counter[18], AccN_Demo, 1
-instance = comp, \inst2|Add2~44\, inst2|Add2~44, AccN_Demo, 1
-instance = comp, \inst2|Add2~46\, inst2|Add2~46, AccN_Demo, 1
-instance = comp, \inst2|s_counter~1\, inst2|s_counter~1, AccN_Demo, 1
-instance = comp, \inst2|s_counter[23]\, inst2|s_counter[23], AccN_Demo, 1
-instance = comp, \inst2|Add2~48\, inst2|Add2~48, AccN_Demo, 1
-instance = comp, \inst2|s_counter[24]\, inst2|s_counter[24], AccN_Demo, 1
-instance = comp, \inst2|Add2~50\, inst2|Add2~50, AccN_Demo, 1
-instance = comp, \inst2|s_counter~0\, inst2|s_counter~0, AccN_Demo, 1
-instance = comp, \inst2|s_counter[25]\, inst2|s_counter[25], AccN_Demo, 1
-instance = comp, \inst2|Add2~52\, inst2|Add2~52, AccN_Demo, 1
-instance = comp, \inst2|s_counter[26]\, inst2|s_counter[26], AccN_Demo, 1
-instance = comp, \inst2|Add2~54\, inst2|Add2~54, AccN_Demo, 1
-instance = comp, \inst2|s_counter[27]\, inst2|s_counter[27], AccN_Demo, 1
-instance = comp, \inst2|Equal0~1\, inst2|Equal0~1, AccN_Demo, 1
-instance = comp, \inst2|Add2~56\, inst2|Add2~56, AccN_Demo, 1
-instance = comp, \inst2|s_counter[28]\, inst2|s_counter[28], AccN_Demo, 1
-instance = comp, \inst2|Add2~58\, inst2|Add2~58, AccN_Demo, 1
-instance = comp, \inst2|s_counter[29]\, inst2|s_counter[29], AccN_Demo, 1
-instance = comp, \inst2|Add2~60\, inst2|Add2~60, AccN_Demo, 1
-instance = comp, \inst2|s_counter[30]\, inst2|s_counter[30], AccN_Demo, 1
-instance = comp, \inst2|Add2~62\, inst2|Add2~62, AccN_Demo, 1
-instance = comp, \inst2|s_counter[31]\, inst2|s_counter[31], AccN_Demo, 1
-instance = comp, \inst2|Equal0~0\, inst2|Equal0~0, AccN_Demo, 1
-instance = comp, \inst2|Equal0~4\, inst2|Equal0~4, AccN_Demo, 1
-instance = comp, \inst2|Equal0~5\, inst2|Equal0~5, AccN_Demo, 1
-instance = comp, \inst2|Add2~38\, inst2|Add2~38, AccN_Demo, 1
-instance = comp, \inst2|Add2~40\, inst2|Add2~40, AccN_Demo, 1
-instance = comp, \inst2|s_counter[20]\, inst2|s_counter[20], AccN_Demo, 1
-instance = comp, \inst2|Add2~42\, inst2|Add2~42, AccN_Demo, 1
-instance = comp, \inst2|s_counter~2\, inst2|s_counter~2, AccN_Demo, 1
-instance = comp, \inst2|s_counter[21]\, inst2|s_counter[21], AccN_Demo, 1
-instance = comp, \inst2|s_counter[22]\, inst2|s_counter[22], AccN_Demo, 1
-instance = comp, \inst2|Equal0~6\, inst2|Equal0~6, AccN_Demo, 1
-instance = comp, \inst2|Equal0~7\, inst2|Equal0~7, AccN_Demo, 1
-instance = comp, \inst2|Equal0~8\, inst2|Equal0~8, AccN_Demo, 1
-instance = comp, \inst2|Equal0~9\, inst2|Equal0~9, AccN_Demo, 1
-instance = comp, \inst2|s_counter~3\, inst2|s_counter~3, AccN_Demo, 1
-instance = comp, \inst2|s_counter[19]\, inst2|s_counter[19], AccN_Demo, 1
-instance = comp, \inst2|clkOut~1\, inst2|clkOut~1, AccN_Demo, 1
-instance = comp, \inst2|clkOut~2\, inst2|clkOut~2, AccN_Demo, 1
-instance = comp, \inst2|clkOut~0\, inst2|clkOut~0, AccN_Demo, 1
-instance = comp, \inst2|clkOut~3\, inst2|clkOut~3, AccN_Demo, 1
-instance = comp, \inst2|clkOut~4\, inst2|clkOut~4, AccN_Demo, 1
-instance = comp, \inst2|clkOut\, inst2|clkOut, AccN_Demo, 1
-instance = comp, \inst2|clkOut~clkctrl\, inst2|clkOut~clkctrl, AccN_Demo, 1
-instance = comp, \SW[16]~input\, SW[16]~input, AccN_Demo, 1
-instance = comp, \SW[15]~input\, SW[15]~input, AccN_Demo, 1
-instance = comp, \SW[14]~input\, SW[14]~input, AccN_Demo, 1
-instance = comp, \SW[13]~input\, SW[13]~input, AccN_Demo, 1
-instance = comp, \SW[12]~input\, SW[12]~input, AccN_Demo, 1
-instance = comp, \SW[11]~input\, SW[11]~input, AccN_Demo, 1
-instance = comp, \SW[10]~input\, SW[10]~input, AccN_Demo, 1
-instance = comp, \SW[9]~input\, SW[9]~input, AccN_Demo, 1
-instance = comp, \SW[8]~input\, SW[8]~input, AccN_Demo, 1
-instance = comp, \SW[7]~input\, SW[7]~input, AccN_Demo, 1
-instance = comp, \SW[6]~input\, SW[6]~input, AccN_Demo, 1
-instance = comp, \SW[5]~input\, SW[5]~input, AccN_Demo, 1
-instance = comp, \SW[4]~input\, SW[4]~input, AccN_Demo, 1
-instance = comp, \SW[3]~input\, SW[3]~input, AccN_Demo, 1
-instance = comp, \SW[2]~input\, SW[2]~input, AccN_Demo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, AccN_Demo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[0]~17\, inst|reg|dataOut[0]~17, AccN_Demo, 1
-instance = comp, \KEY[1]~input\, KEY[1]~input, AccN_Demo, 1
-instance = comp, \SW[17]~input\, SW[17]~input, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[0]\, inst|reg|dataOut[0], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[1]~19\, inst|reg|dataOut[1]~19, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[1]\, inst|reg|dataOut[1], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[2]~21\, inst|reg|dataOut[2]~21, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[2]\, inst|reg|dataOut[2], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[3]~23\, inst|reg|dataOut[3]~23, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[3]\, inst|reg|dataOut[3], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[4]~25\, inst|reg|dataOut[4]~25, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[4]\, inst|reg|dataOut[4], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[5]~27\, inst|reg|dataOut[5]~27, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[5]\, inst|reg|dataOut[5], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[6]~29\, inst|reg|dataOut[6]~29, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[6]\, inst|reg|dataOut[6], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[7]~31\, inst|reg|dataOut[7]~31, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[7]\, inst|reg|dataOut[7], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[8]~33\, inst|reg|dataOut[8]~33, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[8]\, inst|reg|dataOut[8], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[9]~35\, inst|reg|dataOut[9]~35, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[9]\, inst|reg|dataOut[9], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[10]~37\, inst|reg|dataOut[10]~37, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[10]\, inst|reg|dataOut[10], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[11]~39\, inst|reg|dataOut[11]~39, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[11]\, inst|reg|dataOut[11], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[12]~41\, inst|reg|dataOut[12]~41, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[12]\, inst|reg|dataOut[12], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[13]~43\, inst|reg|dataOut[13]~43, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[13]\, inst|reg|dataOut[13], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[14]~45\, inst|reg|dataOut[14]~45, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[14]\, inst|reg|dataOut[14], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[15]~47\, inst|reg|dataOut[15]~47, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[15]\, inst|reg|dataOut[15], AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[16]~49\, inst|reg|dataOut[16]~49, AccN_Demo, 1
-instance = comp, \inst|reg|dataOut[16]\, inst|reg|dataOut[16], AccN_Demo, 1
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd.bak b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd.bak
deleted file mode 100644
index 1193ba4..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd.bak
+++ /dev/null
@@ -1,21 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-
-entity Cmp4 is
- port(
- input0 : in std_logic_vector(3 downto 0);
- input1 : in std_logic_vector(3 downto 0);
- equal : out std_logic;
- notEqual : out std_logic;
- ltSigned : out std_logic;
- ltUnsigned : out std_logic);
-end Cmp4;
-
-architecture Behavioral of Cmp4 is
-begin
- equal <= '1' when (input0 = input1) else '0';
- notEqual <= '1' when (input0 /= input1) else '0';
- ltSigned <= '1' when (signed(input0) < signed(input1)) else '0';
- ltUnsigned <= '1' when (unsigned(input0) < unsigned(input1)) else '0';
-end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qpf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qpf
deleted file mode 100644
index e3f2c0d..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 11:22:49 March 17, 2023
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "20.1"
-DATE = "11:22:49 March 17, 2023"
-
-# Revisions
-
-PROJECT_REVISION = "CmpN_Demo"
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf
deleted file mode 100644
index 646af9b..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf
+++ /dev/null
@@ -1,585 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 11:22:49 March 17, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# CmpN_Demo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY CmpN_Demo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:22:49 MARCH 17, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VECTOR_WAVEFORM_FILE Cmp8.vwf
-set_global_assignment -name VHDL_FILE CmpN.vhd
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name BDF_FILE CmpN_Demo.bdf
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf.bak b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf.bak
deleted file mode 100644
index 646af9b..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf.bak
+++ /dev/null
@@ -1,585 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2020 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details, at
-# https://fpgasoftware.intel.com/eula.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-# Date created = 11:22:49 March 17, 2023
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# CmpN_Demo_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY CmpN_Demo
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:22:49 MARCH 17, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VECTOR_WAVEFORM_FILE Cmp8.vwf
-set_global_assignment -name VHDL_FILE CmpN.vhd
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name BDF_FILE CmpN_Demo.bdf
-set_location_assignment PIN_Y2 -to CLOCK_50
-set_location_assignment PIN_AG14 -to CLOCK2_50
-set_location_assignment PIN_AG15 -to CLOCK3_50
-set_location_assignment PIN_AH14 -to SMA_CLKIN
-set_location_assignment PIN_AE23 -to SMA_CLKOUT
-set_location_assignment PIN_M23 -to KEY[0]
-set_location_assignment PIN_M21 -to KEY[1]
-set_location_assignment PIN_N21 -to KEY[2]
-set_location_assignment PIN_R24 -to KEY[3]
-set_location_assignment PIN_AB28 -to SW[0]
-set_location_assignment PIN_AC28 -to SW[1]
-set_location_assignment PIN_AC27 -to SW[2]
-set_location_assignment PIN_AD27 -to SW[3]
-set_location_assignment PIN_AB27 -to SW[4]
-set_location_assignment PIN_AC26 -to SW[5]
-set_location_assignment PIN_AD26 -to SW[6]
-set_location_assignment PIN_AB26 -to SW[7]
-set_location_assignment PIN_AC25 -to SW[8]
-set_location_assignment PIN_AB25 -to SW[9]
-set_location_assignment PIN_AC24 -to SW[10]
-set_location_assignment PIN_AB24 -to SW[11]
-set_location_assignment PIN_AB23 -to SW[12]
-set_location_assignment PIN_AA24 -to SW[13]
-set_location_assignment PIN_AA23 -to SW[14]
-set_location_assignment PIN_AA22 -to SW[15]
-set_location_assignment PIN_Y24 -to SW[16]
-set_location_assignment PIN_Y23 -to SW[17]
-set_location_assignment PIN_G19 -to LEDR[0]
-set_location_assignment PIN_F19 -to LEDR[1]
-set_location_assignment PIN_E19 -to LEDR[2]
-set_location_assignment PIN_F21 -to LEDR[3]
-set_location_assignment PIN_F18 -to LEDR[4]
-set_location_assignment PIN_E18 -to LEDR[5]
-set_location_assignment PIN_J19 -to LEDR[6]
-set_location_assignment PIN_H19 -to LEDR[7]
-set_location_assignment PIN_J17 -to LEDR[8]
-set_location_assignment PIN_G17 -to LEDR[9]
-set_location_assignment PIN_J15 -to LEDR[10]
-set_location_assignment PIN_H16 -to LEDR[11]
-set_location_assignment PIN_J16 -to LEDR[12]
-set_location_assignment PIN_H17 -to LEDR[13]
-set_location_assignment PIN_F15 -to LEDR[14]
-set_location_assignment PIN_G15 -to LEDR[15]
-set_location_assignment PIN_G16 -to LEDR[16]
-set_location_assignment PIN_H15 -to LEDR[17]
-set_location_assignment PIN_E21 -to LEDG[0]
-set_location_assignment PIN_E22 -to LEDG[1]
-set_location_assignment PIN_E25 -to LEDG[2]
-set_location_assignment PIN_E24 -to LEDG[3]
-set_location_assignment PIN_H21 -to LEDG[4]
-set_location_assignment PIN_G20 -to LEDG[5]
-set_location_assignment PIN_G22 -to LEDG[6]
-set_location_assignment PIN_G21 -to LEDG[7]
-set_location_assignment PIN_F17 -to LEDG[8]
-set_location_assignment PIN_G18 -to HEX0[0]
-set_location_assignment PIN_F22 -to HEX0[1]
-set_location_assignment PIN_E17 -to HEX0[2]
-set_location_assignment PIN_L26 -to HEX0[3]
-set_location_assignment PIN_L25 -to HEX0[4]
-set_location_assignment PIN_J22 -to HEX0[5]
-set_location_assignment PIN_H22 -to HEX0[6]
-set_location_assignment PIN_M24 -to HEX1[0]
-set_location_assignment PIN_Y22 -to HEX1[1]
-set_location_assignment PIN_W21 -to HEX1[2]
-set_location_assignment PIN_W22 -to HEX1[3]
-set_location_assignment PIN_W25 -to HEX1[4]
-set_location_assignment PIN_U23 -to HEX1[5]
-set_location_assignment PIN_U24 -to HEX1[6]
-set_location_assignment PIN_AA25 -to HEX2[0]
-set_location_assignment PIN_AA26 -to HEX2[1]
-set_location_assignment PIN_Y25 -to HEX2[2]
-set_location_assignment PIN_W26 -to HEX2[3]
-set_location_assignment PIN_Y26 -to HEX2[4]
-set_location_assignment PIN_W27 -to HEX2[5]
-set_location_assignment PIN_W28 -to HEX2[6]
-set_location_assignment PIN_V21 -to HEX3[0]
-set_location_assignment PIN_U21 -to HEX3[1]
-set_location_assignment PIN_AB20 -to HEX3[2]
-set_location_assignment PIN_AA21 -to HEX3[3]
-set_location_assignment PIN_AD24 -to HEX3[4]
-set_location_assignment PIN_AF23 -to HEX3[5]
-set_location_assignment PIN_Y19 -to HEX3[6]
-set_location_assignment PIN_AB19 -to HEX4[0]
-set_location_assignment PIN_AA19 -to HEX4[1]
-set_location_assignment PIN_AG21 -to HEX4[2]
-set_location_assignment PIN_AH21 -to HEX4[3]
-set_location_assignment PIN_AE19 -to HEX4[4]
-set_location_assignment PIN_AF19 -to HEX4[5]
-set_location_assignment PIN_AE18 -to HEX4[6]
-set_location_assignment PIN_AD18 -to HEX5[0]
-set_location_assignment PIN_AC18 -to HEX5[1]
-set_location_assignment PIN_AB18 -to HEX5[2]
-set_location_assignment PIN_AH19 -to HEX5[3]
-set_location_assignment PIN_AG19 -to HEX5[4]
-set_location_assignment PIN_AF18 -to HEX5[5]
-set_location_assignment PIN_AH18 -to HEX5[6]
-set_location_assignment PIN_AA17 -to HEX6[0]
-set_location_assignment PIN_AB16 -to HEX6[1]
-set_location_assignment PIN_AA16 -to HEX6[2]
-set_location_assignment PIN_AB17 -to HEX6[3]
-set_location_assignment PIN_AB15 -to HEX6[4]
-set_location_assignment PIN_AA15 -to HEX6[5]
-set_location_assignment PIN_AC17 -to HEX6[6]
-set_location_assignment PIN_AD17 -to HEX7[0]
-set_location_assignment PIN_AE17 -to HEX7[1]
-set_location_assignment PIN_AG17 -to HEX7[2]
-set_location_assignment PIN_AH17 -to HEX7[3]
-set_location_assignment PIN_AF17 -to HEX7[4]
-set_location_assignment PIN_AG18 -to HEX7[5]
-set_location_assignment PIN_AA14 -to HEX7[6]
-set_location_assignment PIN_L3 -to LCD_DATA[0]
-set_location_assignment PIN_L1 -to LCD_DATA[1]
-set_location_assignment PIN_L2 -to LCD_DATA[2]
-set_location_assignment PIN_K7 -to LCD_DATA[3]
-set_location_assignment PIN_K1 -to LCD_DATA[4]
-set_location_assignment PIN_K2 -to LCD_DATA[5]
-set_location_assignment PIN_M3 -to LCD_DATA[6]
-set_location_assignment PIN_M5 -to LCD_DATA[7]
-set_location_assignment PIN_L6 -to LCD_BLON
-set_location_assignment PIN_M1 -to LCD_RW
-set_location_assignment PIN_L4 -to LCD_EN
-set_location_assignment PIN_M2 -to LCD_RS
-set_location_assignment PIN_L5 -to LCD_ON
-set_location_assignment PIN_G9 -to UART_TXD
-set_location_assignment PIN_G12 -to UART_RXD
-set_location_assignment PIN_G14 -to UART_CTS
-set_location_assignment PIN_J13 -to UART_RTS
-set_location_assignment PIN_G6 -to PS2_CLK
-set_location_assignment PIN_H5 -to PS2_DAT
-set_location_assignment PIN_G5 -to PS2_CLK2
-set_location_assignment PIN_F5 -to PS2_DAT2
-set_location_assignment PIN_AE13 -to SD_CLK
-set_location_assignment PIN_AD14 -to SD_CMD
-set_location_assignment PIN_AF14 -to SD_WP_N
-set_location_assignment PIN_AE14 -to SD_DAT[0]
-set_location_assignment PIN_AF13 -to SD_DAT[1]
-set_location_assignment PIN_AB14 -to SD_DAT[2]
-set_location_assignment PIN_AC14 -to SD_DAT[3]
-set_location_assignment PIN_G13 -to VGA_HS
-set_location_assignment PIN_C13 -to VGA_VS
-set_location_assignment PIN_C10 -to VGA_SYNC_N
-set_location_assignment PIN_A12 -to VGA_CLK
-set_location_assignment PIN_F11 -to VGA_BLANK_N
-set_location_assignment PIN_E12 -to VGA_R[0]
-set_location_assignment PIN_E11 -to VGA_R[1]
-set_location_assignment PIN_D10 -to VGA_R[2]
-set_location_assignment PIN_F12 -to VGA_R[3]
-set_location_assignment PIN_G10 -to VGA_R[4]
-set_location_assignment PIN_J12 -to VGA_R[5]
-set_location_assignment PIN_H8 -to VGA_R[6]
-set_location_assignment PIN_H10 -to VGA_R[7]
-set_location_assignment PIN_G8 -to VGA_G[0]
-set_location_assignment PIN_G11 -to VGA_G[1]
-set_location_assignment PIN_F8 -to VGA_G[2]
-set_location_assignment PIN_H12 -to VGA_G[3]
-set_location_assignment PIN_C8 -to VGA_G[4]
-set_location_assignment PIN_B8 -to VGA_G[5]
-set_location_assignment PIN_F10 -to VGA_G[6]
-set_location_assignment PIN_C9 -to VGA_G[7]
-set_location_assignment PIN_B10 -to VGA_B[0]
-set_location_assignment PIN_A10 -to VGA_B[1]
-set_location_assignment PIN_C11 -to VGA_B[2]
-set_location_assignment PIN_B11 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_B[4]
-set_location_assignment PIN_C12 -to VGA_B[5]
-set_location_assignment PIN_D11 -to VGA_B[6]
-set_location_assignment PIN_D12 -to VGA_B[7]
-set_location_assignment PIN_C2 -to AUD_ADCLRCK
-set_location_assignment PIN_D2 -to AUD_ADCDAT
-set_location_assignment PIN_E3 -to AUD_DACLRCK
-set_location_assignment PIN_D1 -to AUD_DACDAT
-set_location_assignment PIN_E1 -to AUD_XCK
-set_location_assignment PIN_F2 -to AUD_BCLK
-set_location_assignment PIN_D14 -to EEP_I2C_SCLK
-set_location_assignment PIN_E14 -to EEP_I2C_SDAT
-set_location_assignment PIN_B7 -to I2C_SCLK
-set_location_assignment PIN_A8 -to I2C_SDAT
-set_location_assignment PIN_A14 -to ENETCLK_25
-set_location_assignment PIN_C14 -to ENET0_LINK100
-set_location_assignment PIN_A17 -to ENET0_GTX_CLK
-set_location_assignment PIN_C19 -to ENET0_RST_N
-set_location_assignment PIN_C20 -to ENET0_MDC
-set_location_assignment PIN_B21 -to ENET0_MDIO
-set_location_assignment PIN_A21 -to ENET0_INT_N
-set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
-set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
-set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
-set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
-set_location_assignment PIN_B17 -to ENET0_TX_CLK
-set_location_assignment PIN_A18 -to ENET0_TX_EN
-set_location_assignment PIN_B18 -to ENET0_TX_ER
-set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
-set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
-set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
-set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
-set_location_assignment PIN_A15 -to ENET0_RX_CLK
-set_location_assignment PIN_C17 -to ENET0_RX_DV
-set_location_assignment PIN_D18 -to ENET0_RX_ER
-set_location_assignment PIN_D15 -to ENET0_RX_CRS
-set_location_assignment PIN_E15 -to ENET0_RX_COL
-set_location_assignment PIN_D13 -to ENET1_LINK100
-set_location_assignment PIN_C23 -to ENET1_GTX_CLK
-set_location_assignment PIN_D22 -to ENET1_RST_N
-set_location_assignment PIN_D23 -to ENET1_MDC
-set_location_assignment PIN_D25 -to ENET1_MDIO
-set_location_assignment PIN_D24 -to ENET1_INT_N
-set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
-set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
-set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
-set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
-set_location_assignment PIN_C22 -to ENET1_TX_CLK
-set_location_assignment PIN_B25 -to ENET1_TX_EN
-set_location_assignment PIN_A25 -to ENET1_TX_ER
-set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
-set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
-set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
-set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
-set_location_assignment PIN_B15 -to ENET1_RX_CLK
-set_location_assignment PIN_A22 -to ENET1_RX_DV
-set_location_assignment PIN_C24 -to ENET1_RX_ER
-set_location_assignment PIN_D20 -to ENET1_RX_CRS
-set_location_assignment PIN_B22 -to ENET1_RX_COL
-set_location_assignment PIN_E5 -to TD_HS
-set_location_assignment PIN_E4 -to TD_VS
-set_location_assignment PIN_B14 -to TD_CLK27
-set_location_assignment PIN_G7 -to TD_RESET_N
-set_location_assignment PIN_E8 -to TD_DATA[0]
-set_location_assignment PIN_A7 -to TD_DATA[1]
-set_location_assignment PIN_D8 -to TD_DATA[2]
-set_location_assignment PIN_C7 -to TD_DATA[3]
-set_location_assignment PIN_D7 -to TD_DATA[4]
-set_location_assignment PIN_D6 -to TD_DATA[5]
-set_location_assignment PIN_E7 -to TD_DATA[6]
-set_location_assignment PIN_F7 -to TD_DATA[7]
-set_location_assignment PIN_J6 -to OTG_DATA[0]
-set_location_assignment PIN_K4 -to OTG_DATA[1]
-set_location_assignment PIN_J5 -to OTG_DATA[2]
-set_location_assignment PIN_K3 -to OTG_DATA[3]
-set_location_assignment PIN_J4 -to OTG_DATA[4]
-set_location_assignment PIN_J3 -to OTG_DATA[5]
-set_location_assignment PIN_J7 -to OTG_DATA[6]
-set_location_assignment PIN_H6 -to OTG_DATA[7]
-set_location_assignment PIN_H3 -to OTG_DATA[8]
-set_location_assignment PIN_H4 -to OTG_DATA[9]
-set_location_assignment PIN_G1 -to OTG_DATA[10]
-set_location_assignment PIN_G2 -to OTG_DATA[11]
-set_location_assignment PIN_G3 -to OTG_DATA[12]
-set_location_assignment PIN_F1 -to OTG_DATA[13]
-set_location_assignment PIN_F3 -to OTG_DATA[14]
-set_location_assignment PIN_G4 -to OTG_DATA[15]
-set_location_assignment PIN_H7 -to OTG_ADDR[0]
-set_location_assignment PIN_C3 -to OTG_ADDR[1]
-set_location_assignment PIN_J1 -to OTG_DREQ[0]
-set_location_assignment PIN_A3 -to OTG_CS_N
-set_location_assignment PIN_A4 -to OTG_WR_N
-set_location_assignment PIN_B3 -to OTG_RD_N
-set_location_assignment PIN_D5 -to OTG_INT
-set_location_assignment PIN_C5 -to OTG_RST_N
-set_location_assignment PIN_Y15 -to IRDA_RXD
-set_location_assignment PIN_U7 -to DRAM_BA[0]
-set_location_assignment PIN_R4 -to DRAM_BA[1]
-set_location_assignment PIN_U2 -to DRAM_DQM[0]
-set_location_assignment PIN_W4 -to DRAM_DQM[1]
-set_location_assignment PIN_K8 -to DRAM_DQM[2]
-set_location_assignment PIN_N8 -to DRAM_DQM[3]
-set_location_assignment PIN_U6 -to DRAM_RAS_N
-set_location_assignment PIN_V7 -to DRAM_CAS_N
-set_location_assignment PIN_AA6 -to DRAM_CKE
-set_location_assignment PIN_AE5 -to DRAM_CLK
-set_location_assignment PIN_V6 -to DRAM_WE_N
-set_location_assignment PIN_T4 -to DRAM_CS_N
-set_location_assignment PIN_W3 -to DRAM_DQ[0]
-set_location_assignment PIN_W2 -to DRAM_DQ[1]
-set_location_assignment PIN_V4 -to DRAM_DQ[2]
-set_location_assignment PIN_W1 -to DRAM_DQ[3]
-set_location_assignment PIN_V3 -to DRAM_DQ[4]
-set_location_assignment PIN_V2 -to DRAM_DQ[5]
-set_location_assignment PIN_V1 -to DRAM_DQ[6]
-set_location_assignment PIN_U3 -to DRAM_DQ[7]
-set_location_assignment PIN_Y3 -to DRAM_DQ[8]
-set_location_assignment PIN_Y4 -to DRAM_DQ[9]
-set_location_assignment PIN_AB1 -to DRAM_DQ[10]
-set_location_assignment PIN_AA3 -to DRAM_DQ[11]
-set_location_assignment PIN_AB2 -to DRAM_DQ[12]
-set_location_assignment PIN_AC1 -to DRAM_DQ[13]
-set_location_assignment PIN_AB3 -to DRAM_DQ[14]
-set_location_assignment PIN_AC2 -to DRAM_DQ[15]
-set_location_assignment PIN_M8 -to DRAM_DQ[16]
-set_location_assignment PIN_L8 -to DRAM_DQ[17]
-set_location_assignment PIN_P2 -to DRAM_DQ[18]
-set_location_assignment PIN_N3 -to DRAM_DQ[19]
-set_location_assignment PIN_N4 -to DRAM_DQ[20]
-set_location_assignment PIN_M4 -to DRAM_DQ[21]
-set_location_assignment PIN_M7 -to DRAM_DQ[22]
-set_location_assignment PIN_L7 -to DRAM_DQ[23]
-set_location_assignment PIN_U5 -to DRAM_DQ[24]
-set_location_assignment PIN_R7 -to DRAM_DQ[25]
-set_location_assignment PIN_R1 -to DRAM_DQ[26]
-set_location_assignment PIN_R2 -to DRAM_DQ[27]
-set_location_assignment PIN_R3 -to DRAM_DQ[28]
-set_location_assignment PIN_T3 -to DRAM_DQ[29]
-set_location_assignment PIN_U4 -to DRAM_DQ[30]
-set_location_assignment PIN_U1 -to DRAM_DQ[31]
-set_location_assignment PIN_R6 -to DRAM_ADDR[0]
-set_location_assignment PIN_V8 -to DRAM_ADDR[1]
-set_location_assignment PIN_U8 -to DRAM_ADDR[2]
-set_location_assignment PIN_P1 -to DRAM_ADDR[3]
-set_location_assignment PIN_V5 -to DRAM_ADDR[4]
-set_location_assignment PIN_W8 -to DRAM_ADDR[5]
-set_location_assignment PIN_W7 -to DRAM_ADDR[6]
-set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
-set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
-set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
-set_location_assignment PIN_R5 -to DRAM_ADDR[10]
-set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
-set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
-set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
-set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
-set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
-set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
-set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
-set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
-set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
-set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
-set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
-set_location_assignment PIN_T7 -to SRAM_ADDR[9]
-set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
-set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
-set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
-set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
-set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
-set_location_assignment PIN_T8 -to SRAM_ADDR[19]
-set_location_assignment PIN_AH3 -to SRAM_DQ[0]
-set_location_assignment PIN_AF4 -to SRAM_DQ[1]
-set_location_assignment PIN_AG4 -to SRAM_DQ[2]
-set_location_assignment PIN_AH4 -to SRAM_DQ[3]
-set_location_assignment PIN_AF6 -to SRAM_DQ[4]
-set_location_assignment PIN_AG6 -to SRAM_DQ[5]
-set_location_assignment PIN_AH6 -to SRAM_DQ[6]
-set_location_assignment PIN_AF7 -to SRAM_DQ[7]
-set_location_assignment PIN_AD1 -to SRAM_DQ[8]
-set_location_assignment PIN_AD2 -to SRAM_DQ[9]
-set_location_assignment PIN_AE2 -to SRAM_DQ[10]
-set_location_assignment PIN_AE1 -to SRAM_DQ[11]
-set_location_assignment PIN_AE3 -to SRAM_DQ[12]
-set_location_assignment PIN_AE4 -to SRAM_DQ[13]
-set_location_assignment PIN_AF3 -to SRAM_DQ[14]
-set_location_assignment PIN_AG3 -to SRAM_DQ[15]
-set_location_assignment PIN_AC4 -to SRAM_UB_N
-set_location_assignment PIN_AD4 -to SRAM_LB_N
-set_location_assignment PIN_AF8 -to SRAM_CE_N
-set_location_assignment PIN_AD5 -to SRAM_OE_N
-set_location_assignment PIN_AE8 -to SRAM_WE_N
-set_location_assignment PIN_AG12 -to FL_ADDR[0]
-set_location_assignment PIN_AH7 -to FL_ADDR[1]
-set_location_assignment PIN_Y13 -to FL_ADDR[2]
-set_location_assignment PIN_Y14 -to FL_ADDR[3]
-set_location_assignment PIN_Y12 -to FL_ADDR[4]
-set_location_assignment PIN_AA13 -to FL_ADDR[5]
-set_location_assignment PIN_AA12 -to FL_ADDR[6]
-set_location_assignment PIN_AB13 -to FL_ADDR[7]
-set_location_assignment PIN_AB12 -to FL_ADDR[8]
-set_location_assignment PIN_AB10 -to FL_ADDR[9]
-set_location_assignment PIN_AE9 -to FL_ADDR[10]
-set_location_assignment PIN_AF9 -to FL_ADDR[11]
-set_location_assignment PIN_AA10 -to FL_ADDR[12]
-set_location_assignment PIN_AD8 -to FL_ADDR[13]
-set_location_assignment PIN_AC8 -to FL_ADDR[14]
-set_location_assignment PIN_Y10 -to FL_ADDR[15]
-set_location_assignment PIN_AA8 -to FL_ADDR[16]
-set_location_assignment PIN_AH12 -to FL_ADDR[17]
-set_location_assignment PIN_AC12 -to FL_ADDR[18]
-set_location_assignment PIN_AD12 -to FL_ADDR[19]
-set_location_assignment PIN_AE10 -to FL_ADDR[20]
-set_location_assignment PIN_AD10 -to FL_ADDR[21]
-set_location_assignment PIN_AD11 -to FL_ADDR[22]
-set_location_assignment PIN_AH8 -to FL_DQ[0]
-set_location_assignment PIN_AF10 -to FL_DQ[1]
-set_location_assignment PIN_AG10 -to FL_DQ[2]
-set_location_assignment PIN_AH10 -to FL_DQ[3]
-set_location_assignment PIN_AF11 -to FL_DQ[4]
-set_location_assignment PIN_AG11 -to FL_DQ[5]
-set_location_assignment PIN_AH11 -to FL_DQ[6]
-set_location_assignment PIN_AF12 -to FL_DQ[7]
-set_location_assignment PIN_AG7 -to FL_CE_N
-set_location_assignment PIN_AG8 -to FL_OE_N
-set_location_assignment PIN_AE11 -to FL_RST_N
-set_location_assignment PIN_Y1 -to FL_RY
-set_location_assignment PIN_AC10 -to FL_WE_N
-set_location_assignment PIN_AE12 -to FL_WP_N
-set_location_assignment PIN_AB22 -to GPIO[0]
-set_location_assignment PIN_AC15 -to GPIO[1]
-set_location_assignment PIN_AB21 -to GPIO[2]
-set_location_assignment PIN_Y17 -to GPIO[3]
-set_location_assignment PIN_AC21 -to GPIO[4]
-set_location_assignment PIN_Y16 -to GPIO[5]
-set_location_assignment PIN_AD21 -to GPIO[6]
-set_location_assignment PIN_AE16 -to GPIO[7]
-set_location_assignment PIN_AD15 -to GPIO[8]
-set_location_assignment PIN_AE15 -to GPIO[9]
-set_location_assignment PIN_AC19 -to GPIO[10]
-set_location_assignment PIN_AF16 -to GPIO[11]
-set_location_assignment PIN_AD19 -to GPIO[12]
-set_location_assignment PIN_AF15 -to GPIO[13]
-set_location_assignment PIN_AF24 -to GPIO[14]
-set_location_assignment PIN_AE21 -to GPIO[15]
-set_location_assignment PIN_AF25 -to GPIO[16]
-set_location_assignment PIN_AC22 -to GPIO[17]
-set_location_assignment PIN_AE22 -to GPIO[18]
-set_location_assignment PIN_AF21 -to GPIO[19]
-set_location_assignment PIN_AF22 -to GPIO[20]
-set_location_assignment PIN_AD22 -to GPIO[21]
-set_location_assignment PIN_AG25 -to GPIO[22]
-set_location_assignment PIN_AD25 -to GPIO[23]
-set_location_assignment PIN_AH25 -to GPIO[24]
-set_location_assignment PIN_AE25 -to GPIO[25]
-set_location_assignment PIN_AG22 -to GPIO[26]
-set_location_assignment PIN_AE24 -to GPIO[27]
-set_location_assignment PIN_AH22 -to GPIO[28]
-set_location_assignment PIN_AF26 -to GPIO[29]
-set_location_assignment PIN_AE20 -to GPIO[30]
-set_location_assignment PIN_AG23 -to GPIO[31]
-set_location_assignment PIN_AF20 -to GPIO[32]
-set_location_assignment PIN_AH26 -to GPIO[33]
-set_location_assignment PIN_AH23 -to GPIO[34]
-set_location_assignment PIN_AG26 -to GPIO[35]
-set_location_assignment PIN_AH15 -to HSMC_CLKIN0
-set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
-set_location_assignment PIN_AE26 -to HSMC_D[0]
-set_location_assignment PIN_AE28 -to HSMC_D[1]
-set_location_assignment PIN_AE27 -to HSMC_D[2]
-set_location_assignment PIN_AF27 -to HSMC_D[3]
-set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
-set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
-set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
-set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
-set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
-set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
-set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
-set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
-set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
-set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
-set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
-set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
-set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
-set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
-set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
-set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
-set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
-set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
-set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
-set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
-set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
-set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
-set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
-set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
-set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
-set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
-set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
-set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
-set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
-set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
-set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
-set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
-set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
-set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
-set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
-set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
-set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
-set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
-set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
-set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
-set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
-set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
-set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
-set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
-set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
-set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
-set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
-set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
-set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
-set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
-set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
-set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
-set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
-set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
-set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
-set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
-set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
-set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
-set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
-set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
-set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
-set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
-set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
-set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
-set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
-set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
-set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
-set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
-set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
-set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
-set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
-set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
-set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
-set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
-set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
-set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
-set_location_assignment PIN_J10 -to EX_IO[0]
-set_location_assignment PIN_J14 -to EX_IO[1]
-set_location_assignment PIN_H13 -to EX_IO[2]
-set_location_assignment PIN_H14 -to EX_IO[3]
-set_location_assignment PIN_F14 -to EX_IO[4]
-set_location_assignment PIN_E10 -to EX_IO[5]
-set_location_assignment PIN_D9 -to EX_IO[6]
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qws b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qws
deleted file mode 100644
index bfc7624..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(1).cnf.cdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(1).cnf.cdb
deleted file mode 100644
index 74cb428..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(1).cnf.hdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(1).cnf.hdb
deleted file mode 100644
index 1dec9c7..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm.qmsg b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm.qmsg
deleted file mode 100644
index 2dc70b1..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318860805 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318860805 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:27:40 2023 " "Processing started: Mon Mar 20 13:27:40 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318860805 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1679318860805 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1679318860805 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1679318860924 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1679318862373 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1679318862434 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318862612 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:27:42 2023 " "Processing ended: Mon Mar 20 13:27:42 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318862612 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318862612 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318862612 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1679318862612 ""}
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm.rdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm.rdb
deleted file mode 100644
index 7a699ea..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cbx.xml b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cbx.xml
deleted file mode 100644
index c0faa1f..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.idb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.idb
deleted file mode 100644
index 9d8057b..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.rdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.rdb
deleted file mode 100644
index 94b0645..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp_merge.kpt b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp_merge.kpt
deleted file mode 100644
index c9823b2..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index d9c61ce..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
deleted file mode 100644
index 218eca7..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
deleted file mode 100644
index 201d97d..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.db_info b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.db_info
deleted file mode 100644
index fe2c3ec..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Wed Mar 22 11:12:21 2023
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.eda.qmsg b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.eda.qmsg
deleted file mode 100644
index df55819..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.eda.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318864466 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318864466 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:27:44 2023 " "Processing started: Mon Mar 20 13:27:44 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318864466 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679318864466 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679318864467 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1679318864625 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "CmpN_Demo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/ simulation " "Generated file CmpN_Demo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1679318864649 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "611 " "Peak virtual memory: 611 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318864659 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:27:44 2023 " "Processing ended: Mon Mar 20 13:27:44 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318864659 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318864659 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318864659 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1679318864659 ""}
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.fit.qmsg b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.fit.qmsg
deleted file mode 100644
index c7ca0c1..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.fit.qmsg
+++ /dev/null
@@ -1,48 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1679318854798 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1679318854798 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "CmpN_Demo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"CmpN_Demo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1679318854800 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679318854841 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679318854841 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1679318855062 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1679318855065 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318855094 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318855094 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318855094 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318855094 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318855094 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318855094 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318855094 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318855094 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318855094 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1679318855094 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/" { { 0 { 0 ""} 0 618 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318855096 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/" { { 0 { 0 ""} 0 620 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318855096 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/" { { 0 { 0 ""} 0 622 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318855096 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/" { { 0 { 0 ""} 0 624 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318855096 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/" { { 0 { 0 ""} 0 626 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318855096 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1679318855096 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1679318855097 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "CmpN_Demo.sdc " "Synopsys Design Constraints File file not found: 'CmpN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1679318855551 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1679318855551 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1679318855551 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1679318855551 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1679318855552 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1679318855552 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1679318855552 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1679318855554 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679318855554 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679318855554 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1679318855554 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1679318855554 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1679318855554 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1679318855554 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1679318855555 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1679318855555 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1679318855555 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1679318855555 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318855572 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1679318855572 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318855579 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1679318855580 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1679318856986 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318857053 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1679318857077 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1679318857319 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318857320 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1679318857437 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y12 X115_Y23 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23"} { { 12 { 0 ""} 104 12 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1679318859317 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1679318859317 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1679318859438 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1679318859438 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1679318859438 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318859439 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1679318859508 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1679318859514 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1679318859660 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1679318859660 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1679318859798 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318860026 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1679318860186 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1679318860219 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 500 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 500 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1153 " "Peak virtual memory: 1153 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318860334 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:27:40 2023 " "Processing ended: Mon Mar 20 13:27:40 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318860334 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318860334 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318860334 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1679318860334 ""}
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.hier_info b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.hier_info
deleted file mode 100644
index b79a772..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.hier_info
+++ /dev/null
@@ -1,97 +0,0 @@
-|CmpN_Demo
-LEDG[0] <= CmpN:inst.equal
-LEDG[1] <= CmpN:inst.notEqual
-LEDG[2] <= CmpN:inst.ltSigned
-LEDG[3] <= CmpN:inst.ltUnsigned
-SW[0] => CmpN:inst.input1[0]
-SW[1] => CmpN:inst.input1[1]
-SW[2] => CmpN:inst.input1[2]
-SW[3] => CmpN:inst.input1[3]
-SW[4] => CmpN:inst.input0[0]
-SW[5] => CmpN:inst.input0[1]
-SW[6] => CmpN:inst.input0[2]
-SW[7] => CmpN:inst.input0[3]
-SW[8] => CmpN:inst3.input1[0]
-SW[9] => CmpN:inst3.input1[1]
-SW[10] => CmpN:inst3.input1[2]
-SW[11] => CmpN:inst3.input1[3]
-SW[12] => CmpN:inst3.input1[4]
-SW[13] => CmpN:inst3.input0[0]
-SW[14] => CmpN:inst3.input0[1]
-SW[15] => CmpN:inst3.input0[2]
-SW[16] => CmpN:inst3.input0[3]
-SW[17] => CmpN:inst3.input0[4]
-LEDR[0] <= CmpN:inst3.equal
-LEDR[1] <= CmpN:inst3.notEqual
-LEDR[2] <= CmpN:inst3.ltSigned
-LEDR[3] <= CmpN:inst3.ltUnsigned
-
-
-|CmpN_Demo|CmpN:inst
-input0[0] => Equal0.IN3
-input0[0] => LessThan0.IN4
-input0[0] => LessThan1.IN4
-input0[1] => Equal0.IN2
-input0[1] => LessThan0.IN3
-input0[1] => LessThan1.IN3
-input0[2] => Equal0.IN1
-input0[2] => LessThan0.IN2
-input0[2] => LessThan1.IN2
-input0[3] => Equal0.IN0
-input0[3] => LessThan0.IN1
-input0[3] => LessThan1.IN1
-input1[0] => Equal0.IN7
-input1[0] => LessThan0.IN8
-input1[0] => LessThan1.IN8
-input1[1] => Equal0.IN6
-input1[1] => LessThan0.IN7
-input1[1] => LessThan1.IN7
-input1[2] => Equal0.IN5
-input1[2] => LessThan0.IN6
-input1[2] => LessThan1.IN6
-input1[3] => Equal0.IN4
-input1[3] => LessThan0.IN5
-input1[3] => LessThan1.IN5
-equal <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
-notEqual <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
-ltSigned <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
-ltUnsigned <= LessThan1.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|CmpN_Demo|CmpN:inst3
-input0[0] => Equal0.IN4
-input0[0] => LessThan0.IN5
-input0[0] => LessThan1.IN5
-input0[1] => Equal0.IN3
-input0[1] => LessThan0.IN4
-input0[1] => LessThan1.IN4
-input0[2] => Equal0.IN2
-input0[2] => LessThan0.IN3
-input0[2] => LessThan1.IN3
-input0[3] => Equal0.IN1
-input0[3] => LessThan0.IN2
-input0[3] => LessThan1.IN2
-input0[4] => Equal0.IN0
-input0[4] => LessThan0.IN1
-input0[4] => LessThan1.IN1
-input1[0] => Equal0.IN9
-input1[0] => LessThan0.IN10
-input1[0] => LessThan1.IN10
-input1[1] => Equal0.IN8
-input1[1] => LessThan0.IN9
-input1[1] => LessThan1.IN9
-input1[2] => Equal0.IN7
-input1[2] => LessThan0.IN8
-input1[2] => LessThan1.IN8
-input1[3] => Equal0.IN6
-input1[3] => LessThan0.IN7
-input1[3] => LessThan1.IN7
-input1[4] => Equal0.IN5
-input1[4] => LessThan0.IN6
-input1[4] => LessThan1.IN6
-equal <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
-notEqual <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
-ltSigned <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
-ltUnsigned <= LessThan1.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.hif b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.hif
deleted file mode 100644
index e7d1531..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.hif and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.lpc.html b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.lpc.html
deleted file mode 100644
index 1682d8e..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.lpc.html
+++ /dev/null
@@ -1,50 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| inst3 |
-10 |
-0 |
-0 |
-0 |
-4 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
-| inst |
-8 |
-0 |
-0 |
-0 |
-4 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.lpc.rdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.lpc.rdb
deleted file mode 100644
index 0784d38..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.lpc.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.lpc.txt b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.lpc.txt
deleted file mode 100644
index a682372..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.lpc.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; inst3 ; 10 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; inst ; 8 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.ammdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.ammdb
deleted file mode 100644
index 790b913..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.kpt b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.kpt
deleted file mode 100644
index 4ad0f3b..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.qmsg b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.qmsg
deleted file mode 100644
index 4a2eda5..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.qmsg
+++ /dev/null
@@ -1,11 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679483663042 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679483663043 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 11:14:22 2023 " "Processing started: Wed Mar 22 11:14:22 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679483663043 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679483663043 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679483663043 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679483663209 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679483663209 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CmpN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file CmpN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CmpN-Behavioral " "Found design unit 1: CmpN-Behavioral" { } { { "CmpN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd" 18 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679483669409 ""} { "Info" "ISGN_ENTITY_NAME" "1 CmpN " "Found entity 1: CmpN" { } { { "CmpN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679483669409 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679483669409 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CmpN_Demo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file CmpN_Demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CmpN_Demo " "Found entity 1: CmpN_Demo" { } { { "CmpN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679483669415 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679483669415 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "CmpN " "Elaborating entity \"CmpN\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679483669445 ""}
-{ "Error" "EVRFX_VHDL_FORMAL_HAS_NO_VALUE" "N CmpN.vhd(5) " "VHDL error at CmpN.vhd(5): formal port or parameter \"N\" must have actual or default value" { } { { "CmpN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd" 5 0 0 } } } 0 10346 "VHDL error at %2!s!: formal port or parameter \"%1!s!\" must have actual or default value" 0 0 "Analysis & Synthesis" 0 -1 1679483669445 ""}
-{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Can't elaborate top-level user hierarchy" { } { } 0 12153 "Can't elaborate top-level user hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679483669446 ""}
-{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "424 " "Peak virtual memory: 424 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679483669500 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Mar 22 11:14:29 2023 " "Processing ended: Wed Mar 22 11:14:29 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679483669500 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679483669500 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:18 " "Total CPU time (on all processors): 00:00:18" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679483669500 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679483669500 ""}
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.rdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.rdb
deleted file mode 100644
index 9b80d9f..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.rtlv.hdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.rtlv.hdb
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sld_design_entry.sci b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sld_design_entry.sci
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sld_design_entry_dsc.sci
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.smart_action.txt b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.smart_action.txt
deleted file mode 100644
index 11b531f..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-SOURCE
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sta.qmsg b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sta.qmsg
deleted file mode 100644
index 0b5a650..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sta.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318863117 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318863117 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:27:43 2023 " "Processing started: Mon Mar 20 13:27:43 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318863117 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1679318863117 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta CmpN_Demo -c CmpN_Demo " "Command: quartus_sta CmpN_Demo -c CmpN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1679318863117 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1679318863138 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1679318863197 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1679318863197 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318863246 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318863246 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "CmpN_Demo.sdc " "Synopsys Design Constraints File file not found: 'CmpN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1679318863544 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318863545 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1679318863545 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1679318863545 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1679318863545 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1679318863545 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1679318863546 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1679318863548 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1679318863549 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863549 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863551 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863552 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863552 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863552 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863552 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679318863554 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1679318863566 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1679318863724 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318863736 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1679318863736 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1679318863736 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1679318863736 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863737 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863737 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863738 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863738 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863738 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863739 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679318863740 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318863775 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1679318863775 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1679318863775 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1679318863776 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863776 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863776 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863777 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863777 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318863777 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679318863981 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679318863981 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "536 " "Peak virtual memory: 536 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318863991 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:27:43 2023 " "Processing ended: Mon Mar 20 13:27:43 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318863991 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318863991 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318863991 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1679318863991 ""}
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sta.rdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sta.rdb
deleted file mode 100644
index c344b92..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sta.rdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tis_db_list.ddb
deleted file mode 100644
index 8134646..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tis_db_list.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index 219a91f..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tiscmp.fast_1200mv_0c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index 0aacb45..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tiscmp.slow_1200mv_0c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index 9cb507c..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.vpr.ammdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.vpr.ammdb
deleted file mode 100644
index b97800e..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.vpr.ammdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo_partition_pins.json b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo_partition_pins.json
deleted file mode 100644
index e162fc1..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo_partition_pins.json
+++ /dev/null
@@ -1,113 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "LEDG[3]",
- "strict" : false
- },
- {
- "name" : "LEDG[2]",
- "strict" : false
- },
- {
- "name" : "LEDG[1]",
- "strict" : false
- },
- {
- "name" : "LEDG[0]",
- "strict" : false
- },
- {
- "name" : "LEDR[3]",
- "strict" : false
- },
- {
- "name" : "LEDR[2]",
- "strict" : false
- },
- {
- "name" : "LEDR[1]",
- "strict" : false
- },
- {
- "name" : "LEDR[0]",
- "strict" : false
- },
- {
- "name" : "SW[2]",
- "strict" : false
- },
- {
- "name" : "SW[1]",
- "strict" : false
- },
- {
- "name" : "SW[5]",
- "strict" : false
- },
- {
- "name" : "SW[6]",
- "strict" : false
- },
- {
- "name" : "SW[0]",
- "strict" : false
- },
- {
- "name" : "SW[4]",
- "strict" : false
- },
- {
- "name" : "SW[7]",
- "strict" : false
- },
- {
- "name" : "SW[3]",
- "strict" : false
- },
- {
- "name" : "SW[11]",
- "strict" : false
- },
- {
- "name" : "SW[17]",
- "strict" : false
- },
- {
- "name" : "SW[12]",
- "strict" : false
- },
- {
- "name" : "SW[16]",
- "strict" : false
- },
- {
- "name" : "SW[9]",
- "strict" : false
- },
- {
- "name" : "SW[8]",
- "strict" : false
- },
- {
- "name" : "SW[13]",
- "strict" : false
- },
- {
- "name" : "SW[14]",
- "strict" : false
- },
- {
- "name" : "SW[10]",
- "strict" : false
- },
- {
- "name" : "SW[15]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/prev_cmp_CmpN_Demo.qmsg b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/prev_cmp_CmpN_Demo.qmsg
deleted file mode 100644
index 80fc708..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/prev_cmp_CmpN_Demo.qmsg
+++ /dev/null
@@ -1,140 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318761883 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318761883 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:26:01 2023 " "Processing started: Mon Mar 20 13:26:01 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318761883 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318761883 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318761883 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679318762007 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679318762007 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CmpN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file CmpN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CmpN-Behavioral " "Found design unit 1: CmpN-Behavioral" { } { { "CmpN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd" 18 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318766399 ""} { "Info" "ISGN_ENTITY_NAME" "1 CmpN " "Found entity 1: CmpN" { } { { "CmpN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318766399 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318766399 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CmpN_Demo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file CmpN_Demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CmpN_Demo " "Found entity 1: CmpN_Demo" { } { { "CmpN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318766399 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318766399 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "CmpN_Demo " "Elaborating entity \"CmpN_Demo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679318766423 ""}
-{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "SW1\[17..13\] SW " "Bus \"SW1\[17..13\]\" found using same base name as \"SW\", which might lead to a name conflict." { } { { "CmpN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { { 408 424 592 424 "SW1\[17..13\]" "" } { 408 424 592 424 "SW1\[17..13\]" "" } { 408 424 592 424 "SW1\[17..13\]" "" } { 408 424 592 424 "SW1\[17..13\]" "" } { 408 424 592 424 "SW1\[17..13\]" "" } { 408 424 592 424 "SW1\[17..13\]" "" } } } } } 0 275083 "Bus \"%1!s!\" found using same base name as \"%2!s!\", which might lead to a name conflict." 0 0 "Analysis & Synthesis" 0 -1 1679318766424 ""}
-{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "SW2\[12..8\] SW " "Bus \"SW2\[12..8\]\" found using same base name as \"SW\", which might lead to a name conflict." { } { { "CmpN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { { 424 424 592 440 "SW2\[12..8\]" "" } { 424 424 592 440 "SW2\[12..8\]" "" } { 424 424 592 440 "SW2\[12..8\]" "" } { 424 424 592 440 "SW2\[12..8\]" "" } { 424 424 592 440 "SW2\[12..8\]" "" } { 424 424 592 440 "SW2\[12..8\]" "" } } } } } 0 275083 "Bus \"%1!s!\" found using same base name as \"%2!s!\", which might lead to a name conflict." 0 0 "Analysis & Synthesis" 0 -1 1679318766424 ""}
-{ "Warning" "WGDFX_PROCESSING_BUS_NAME_WITH_MAXPLUS_II_NAMING" "SW " "Converted elements in bus name \"SW\" using legacy naming rules. Make any assignments on the new names, not on the original names." { { "Warning" "WGDFX_CONVERTING_BUS_NAME" "SW\[7..4\] SW7..4 " "Converted element name(s) from \"SW\[7..4\]\" to \"SW7..4\"" { } { { "CmpN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { { 240 424 592 256 "SW\[7..4\]" "" } } } } } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Design Software" 0 -1 1679318766424 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "SW\[3..0\] SW3..0 " "Converted element name(s) from \"SW\[3..0\]\" to \"SW3..0\"" { } { { "CmpN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { { 256 424 592 272 "SW\[3..0\]" "" } } } } } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Design Software" 0 -1 1679318766424 ""} } { { "CmpN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { { 240 424 592 256 "SW\[7..4\]" "" } { 256 424 592 272 "SW\[3..0\]" "" } } } } } 0 275080 "Converted elements in bus name \"%1!s!\" using legacy naming rules. Make any assignments on the new names, not on the original names." 0 0 "Analysis & Synthesis" 0 -1 1679318766424 ""}
-{ "Warning" "WGDFX_PROCESSING_BUS_NAME_WITH_MAXPLUS_II_NAMING" "SW1 " "Converted elements in bus name \"SW1\" using legacy naming rules. Make any assignments on the new names, not on the original names." { { "Warning" "WGDFX_CONVERTING_BUS_NAME" "SW1\[17..13\] SW117..13 " "Converted element name(s) from \"SW1\[17..13\]\" to \"SW117..13\"" { } { { "CmpN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { { 408 424 592 424 "SW1\[17..13\]" "" } } } } } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Design Software" 0 -1 1679318766424 ""} } { { "CmpN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { { 408 424 592 424 "SW1\[17..13\]" "" } } } } } 0 275080 "Converted elements in bus name \"%1!s!\" using legacy naming rules. Make any assignments on the new names, not on the original names." 0 0 "Analysis & Synthesis" 0 -1 1679318766424 ""}
-{ "Warning" "WGDFX_PROCESSING_BUS_NAME_WITH_MAXPLUS_II_NAMING" "SW2 " "Converted elements in bus name \"SW2\" using legacy naming rules. Make any assignments on the new names, not on the original names." { { "Warning" "WGDFX_CONVERTING_BUS_NAME" "SW2\[12..8\] SW212..8 " "Converted element name(s) from \"SW2\[12..8\]\" to \"SW212..8\"" { } { { "CmpN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { { 424 424 592 440 "SW2\[12..8\]" "" } } } } } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Design Software" 0 -1 1679318766424 ""} } { { "CmpN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { { 424 424 592 440 "SW2\[12..8\]" "" } } } } } 0 275080 "Converted elements in bus name \"%1!s!\" using legacy naming rules. Make any assignments on the new names, not on the original names." 0 0 "Analysis & Synthesis" 0 -1 1679318766424 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CmpN CmpN:inst " "Elaborating entity \"CmpN\" for hierarchy \"CmpN:inst\"" { } { { "CmpN_Demo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { { 216 600 792 328 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318766425 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CmpN CmpN:inst3 " "Elaborating entity \"CmpN\" for hierarchy \"CmpN:inst3\"" { } { { "CmpN_Demo.bdf" "inst3" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { { 384 600 792 496 "inst3" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318766426 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1679318766740 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1679318767024 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318767024 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "42 " "Implemented 42 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Implemented 18 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1679318767039 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1679318767039 ""} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Implemented 16 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1679318767039 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1679318767039 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318767042 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:26:07 2023 " "Processing ended: Mon Mar 20 13:26:07 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318767042 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318767042 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318767042 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318767042 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1679318767498 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318767498 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:26:07 2023 " "Processing started: Mon Mar 20 13:26:07 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318767498 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1679318767498 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo " "Command: quartus_fit --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1679318767498 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1679318767518 ""}
-{ "Info" "0" "" "Project = CmpN_Demo" { } { } 0 0 "Project = CmpN_Demo" 0 0 "Fitter" 0 0 1679318767518 ""}
-{ "Info" "0" "" "Revision = CmpN_Demo" { } { } 0 0 "Revision = CmpN_Demo" 0 0 "Fitter" 0 0 1679318767518 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1679318767550 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1679318767550 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "CmpN_Demo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"CmpN_Demo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1679318767552 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679318767593 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679318767593 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1679318767815 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1679318767818 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318767846 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318767846 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318767846 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318767846 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318767846 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318767846 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318767846 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318767846 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679318767846 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1679318767846 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/" { { 0 { 0 ""} 0 636 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318767848 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/" { { 0 { 0 ""} 0 638 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318767848 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/" { { 0 { 0 ""} 0 640 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318767848 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/" { { 0 { 0 ""} 0 642 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318767848 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/" { { 0 { 0 ""} 0 644 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679318767848 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1679318767848 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1679318767849 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "18 26 " "No exact pin location assignment(s) for 18 pins of 26 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1679318768200 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "CmpN_Demo.sdc " "Synopsys Design Constraints File file not found: 'CmpN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1679318768289 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1679318768290 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1679318768290 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1679318768290 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1679318768291 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1679318768291 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1679318768291 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1679318768292 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679318768292 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679318768293 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1679318768293 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1679318768293 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1679318768293 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1679318768293 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1679318768293 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1679318768293 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1679318768293 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1679318768293 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "18 unused 2.5V 18 0 0 " "Number of I/O pins in group: 18 (unused VREF, 2.5V VCCIO, 18 input, 0 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1679318768294 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1679318768294 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1679318768294 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 52 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 52 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1679318768295 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 63 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 63 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1679318768295 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 73 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 73 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1679318768295 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 71 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 71 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1679318768295 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 65 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 65 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1679318768295 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 57 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 57 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1679318768295 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 2.5V 8 64 " "I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 8 total pin(s) used -- 64 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1679318768295 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 71 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 71 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1679318768295 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1679318768295 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1679318768295 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679318768314 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1679318768314 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318768321 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1679318768323 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1679318769675 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318769741 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1679318769767 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1679318770089 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318770089 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1679318770207 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X81_Y61 X91_Y73 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X81_Y61 to location X91_Y73" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X81_Y61 to location X91_Y73"} { { 12 { 0 ""} 81 61 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1679318772106 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1679318772106 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1679318772219 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1679318772219 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1679318772219 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318772220 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1679318772289 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1679318772293 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1679318772442 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1679318772442 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1679318772583 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679318772803 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1679318772960 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1679318772994 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 519 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 519 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1146 " "Peak virtual memory: 1146 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318773112 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:26:13 2023 " "Processing ended: Mon Mar 20 13:26:13 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318773112 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318773112 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318773112 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1679318773112 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1679318773580 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318773580 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:26:13 2023 " "Processing started: Mon Mar 20 13:26:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318773580 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1679318773580 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1679318773581 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1679318773702 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1679318775139 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1679318775197 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "368 " "Peak virtual memory: 368 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318775375 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:26:15 2023 " "Processing ended: Mon Mar 20 13:26:15 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318775375 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318775375 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318775375 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1679318775375 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1679318775954 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1679318776330 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318776330 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:26:16 2023 " "Processing started: Mon Mar 20 13:26:16 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318776330 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1679318776330 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta CmpN_Demo -c CmpN_Demo " "Command: quartus_sta CmpN_Demo -c CmpN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1679318776330 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1679318776350 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1679318776408 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1679318776408 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318776452 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318776452 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "CmpN_Demo.sdc " "Synopsys Design Constraints File file not found: 'CmpN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1679318776740 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318776740 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1679318776740 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1679318776740 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1679318776740 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1679318776740 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1679318776741 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1679318776743 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1679318776744 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776744 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776746 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776746 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776746 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776747 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776747 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679318776748 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1679318776760 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1679318776912 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318776925 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1679318776925 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1679318776925 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1679318776925 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776926 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776926 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776927 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776927 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776927 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776928 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679318776929 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318776964 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1679318776964 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1679318776964 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1679318776964 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776965 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776965 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776966 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776966 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318776966 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679318777169 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679318777169 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "537 " "Peak virtual memory: 537 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318777178 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:26:17 2023 " "Processing ended: Mon Mar 20 13:26:17 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318777178 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318777178 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318777178 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1679318777178 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1679318778140 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318778145 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:26:18 2023 " "Processing started: Mon Mar 20 13:26:18 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318778145 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679318778145 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679318778145 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1679318778289 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "CmpN_Demo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/ simulation " "Generated file CmpN_Demo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1679318778313 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "611 " "Peak virtual memory: 611 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318778325 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:26:18 2023 " "Processing ended: Mon Mar 20 13:26:18 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318778325 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318778325 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318778325 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1679318778325 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 536 s " "Quartus Prime Full Compilation was successful. 0 errors, 536 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1679318778395 ""}
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/README b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.db_info b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.db_info
deleted file mode 100644
index 83ca47b..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Version_Index = 520278016
-Creation_Time = Fri Mar 17 11:57:34 2023
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.ammdb
deleted file mode 100644
index 118431c..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.cdb
deleted file mode 100644
index 209cebe..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.hdb
deleted file mode 100644
index de9d761..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.rcfdb
deleted file mode 100644
index 58046de..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.cdb
deleted file mode 100644
index e07cd87..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.dpi
deleted file mode 100644
index dd0439f..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.cdb
deleted file mode 100644
index d57a250..0000000
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.hdb
deleted file mode 100644
index a1e6054..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hdb
deleted file mode 100644
index 7513d18..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.kpt
deleted file mode 100644
index 48de6c9..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.kpt and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.rrp.hdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.rrp.hdb
deleted file mode 100644
index a2fec5d..0000000
Binary files a/1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.rrp.hdb and /dev/null differ
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.asm.rpt b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.asm.rpt
deleted file mode 100644
index 7c2ff63..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for CmpN_Demo
-Mon Mar 20 13:27:42 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: CmpN_Demo.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Mon Mar 20 13:27:42 2023 ;
-; Revision Name ; CmpN_Demo ;
-; Top-level Entity Name ; CmpN_Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+----------------------------------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+----------------------------------------------------------------------------------------------------+
-; File Name ;
-+----------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sof ;
-+----------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------+
-; Assembler Device Options: CmpN_Demo.sof ;
-+----------------+------------------------+
-; Option ; Setting ;
-+----------------+------------------------+
-; JTAG usercode ; 0x00565A9F ;
-; Checksum ; 0x00565A9F ;
-+----------------+------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Mon Mar 20 13:27:40 2023
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 367 megabytes
- Info: Processing ended: Mon Mar 20 13:27:42 2023
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.cdf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.cdf
deleted file mode 100644
index 5c9ca54..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.cdf
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition */
-JedecChain;
- FileRevision(JESD32A);
- DefaultMfr(6E);
-
- P ActionCode(Cfg)
- Device PartName(EP4CE115F29) Path("/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/") File("CmpN_Demo.sof") MfrSpec(OpMask(1));
-
-ChainEnd;
-
-AlteraBegin;
- ChainType(JTAG);
-AlteraEnd;
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.done b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.done
deleted file mode 100644
index 54309b4..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.done
+++ /dev/null
@@ -1 +0,0 @@
-Mon Mar 20 13:27:45 2023
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.eda.rpt b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.eda.rpt
deleted file mode 100644
index bb11c8b..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.eda.rpt
+++ /dev/null
@@ -1,94 +0,0 @@
-EDA Netlist Writer report for CmpN_Demo
-Mon Mar 20 13:27:44 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Mon Mar 20 13:27:44 2023 ;
-; Revision Name ; CmpN_Demo ;
-; Top-level Entity Name ; CmpN_Demo ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-; Tool Name ; ModelSim-Altera (VHDL) ;
-; Generate functional simulation netlist ; On ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+-----------------------------------------------------------------------------------------------------------+
-; Generated Files ;
-+-----------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo.vho ;
-+-----------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Mon Mar 20 13:27:44 2023
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file CmpN_Demo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 611 megabytes
- Info: Processing ended: Mon Mar 20 13:27:44 2023
- Info: Elapsed time: 00:00:00
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.rpt b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.rpt
deleted file mode 100644
index e98f4fb..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.rpt
+++ /dev/null
@@ -1,2622 +0,0 @@
-Fitter report for CmpN_Demo
-Mon Mar 20 13:27:40 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Ignored Assignments
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Routing Usage Summary
- 22. LAB Logic Elements
- 23. LAB Signals Sourced
- 24. LAB Signals Sourced Out
- 25. LAB Distinct Inputs
- 26. I/O Rules Summary
- 27. I/O Rules Details
- 28. I/O Rules Matrix
- 29. Fitter Device Options
- 30. Operating Settings and Conditions
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Mon Mar 20 13:27:40 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; CmpN_Demo ;
-; Top-level Entity Name ; CmpN_Demo ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; 16 / 114,480 ( < 1 % ) ;
-; Total combinational functions ; 16 / 114,480 ( < 1 % ) ;
-; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; Total registers ; 0 ;
-; Total pins ; 26 / 529 ( 5 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.1% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
-; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
-; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
-; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
-; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
-; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
-; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
-; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
-; Location ; ; ; CLOCK_50 ; PIN_Y2 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
-; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
-; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
-; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
-; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
-; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
-; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
-; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
-; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
-; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
-; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
-; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
-; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
-; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
-; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
-; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
-; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
-; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
-; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
-; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
-; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
-; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
-; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
-; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
-; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
-; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
-; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
-; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
-; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
-; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
-; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
-; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
-; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
-; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
-; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
-; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
-; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
-; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
-; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
-; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
-; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
-; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
-; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
-; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
-; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
-; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
-; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
-; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
-; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
-; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
-; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
-; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
-; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
-; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
-; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
-; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
-; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
-; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
-; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
-; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
-; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
-; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
-; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
-; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
-; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
-; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
-; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
-; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
-; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
-; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
-; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
-; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
-; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
-; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
-; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
-; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
-; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
-; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
-; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
-; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
-; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
-; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
-; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
-; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
-; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
-; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
-; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
-; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
-; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
-; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
-; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
-; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
-; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
-; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
-; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
-; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
-; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
-; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
-; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
-; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
-; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
-; Location ; ; ; KEY[0] ; PIN_M23 ; QSF Assignment ;
-; Location ; ; ; KEY[1] ; PIN_M21 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
-; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
-; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
-; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
-; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
-; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
-; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
-; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
-; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
-; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
-; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
-; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
-; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
-; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
-; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
-; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
-; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
-; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
-; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
-; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
-; Location ; ; ; LEDR[4] ; PIN_F18 ; QSF Assignment ;
-; Location ; ; ; LEDR[5] ; PIN_E18 ; QSF Assignment ;
-; Location ; ; ; LEDR[6] ; PIN_J19 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_H19 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
-; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
-; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
-; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
-; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
-; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
-; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
-; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
-; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
-; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
-; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
-; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
-; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
-; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
-; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
-; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
-; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
-; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
-; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
-; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
-; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
-; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
-; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
-; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
-; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
-; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
-; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
-; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
-; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
-; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
-; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
-; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
-; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
-; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
-; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
-; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
-; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
-; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
-; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
-; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
-; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
-; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
-; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
-; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
-; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
-; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
-; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
-; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
-; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
-+----------+----------------+--------------+------------------+---------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+-------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 79 ) ; 0.00 % ( 0 / 79 ) ; 0.00 % ( 0 / 79 ) ;
-; -- Achieved ; 0.00 % ( 0 / 79 ) ; 0.00 % ( 0 / 79 ) ; 0.00 % ( 0 / 79 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+-------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 69 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.pin.
-
-
-+----------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+------------------------+
-; Total logic elements ; 16 / 114,480 ( < 1 % ) ;
-; -- Combinational with no register ; 16 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 0 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 12 ;
-; -- 3 input functions ; 2 ;
-; -- <=2 input functions ; 2 ;
-; -- Register only ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 16 ;
-; -- arithmetic mode ; 0 ;
-; ; ;
-; Total registers* ; 0 / 117,053 ( 0 % ) ;
-; -- Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
-; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 2 / 7,155 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 26 / 529 ( 5 % ) ;
-; -- Clock pins ; 0 / 7 ( 0 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 432 ( 0 % ) ;
-; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 0 ;
-; -- Global clocks ; 0 / 20 ( 0 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.3% / 0.2% / 0.6% ;
-; Maximum fan-out ; 4 ;
-; Highest non-global fan-out ; 4 ;
-; Total fan-out ; 97 ;
-; Average fan-out ; 1.24 ;
-+---------------------------------------------+------------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+-----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 16 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
-; -- Combinational with no register ; 16 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 0 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 12 ; 0 ;
-; -- 3 input functions ; 2 ; 0 ;
-; -- <=2 input functions ; 2 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 16 ; 0 ;
-; -- arithmetic mode ; 0 ; 0 ;
-; ; ; ;
-; Total registers ; 0 ; 0 ;
-; -- Dedicated logic registers ; 0 / 114480 ( 0 % ) ; 0 / 114480 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 2 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 26 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 92 ; 5 ;
-; -- Registered Connections ; 0 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 18 ; 0 ;
-; -- Output Ports ; 8 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+-----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[10] ; AC24 ; 5 ; 115 ; 4 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[11] ; AB24 ; 5 ; 115 ; 5 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[12] ; AB23 ; 5 ; 115 ; 7 ; 14 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[13] ; AA24 ; 5 ; 115 ; 9 ; 21 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[14] ; AA23 ; 5 ; 115 ; 10 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[15] ; AA22 ; 5 ; 115 ; 6 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[16] ; Y24 ; 5 ; 115 ; 13 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[17] ; Y23 ; 5 ; 115 ; 14 ; 7 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[3] ; AD27 ; 5 ; 115 ; 13 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[4] ; AB27 ; 5 ; 115 ; 18 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[5] ; AC26 ; 5 ; 115 ; 11 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[6] ; AD26 ; 5 ; 115 ; 10 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[7] ; AB26 ; 5 ; 115 ; 15 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[8] ; AC25 ; 5 ; 115 ; 4 ; 21 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; SW[9] ; AB25 ; 5 ; 115 ; 16 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; LEDG[0] ; E21 ; 7 ; 107 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDG[1] ; E22 ; 7 ; 111 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDG[2] ; E25 ; 7 ; 83 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDG[3] ; E24 ; 7 ; 85 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[2] ; E19 ; 7 ; 94 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LEDR[3] ; F21 ; 7 ; 107 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
-; 2 ; 0 / 63 ( 0 % ) ; 2.5V ; -- ;
-; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 18 / 65 ( 28 % ) ; 2.5V ; -- ;
-; 6 ; 1 / 58 ( 2 % ) ; 2.5V ; -- ;
-; 7 ; 8 / 72 ( 11 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
-+----------+------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; 275 ; 5 ; SW[15] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA23 ; 280 ; 5 ; SW[14] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA24 ; 279 ; 5 ; SW[13] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB23 ; 276 ; 5 ; SW[12] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB24 ; 274 ; 5 ; SW[11] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB25 ; 292 ; 5 ; SW[9] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB26 ; 291 ; 5 ; SW[7] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB27 ; 296 ; 5 ; SW[4] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC24 ; 273 ; 5 ; SW[10] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC25 ; 272 ; 5 ; SW[8] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC26 ; 282 ; 5 ; SW[5] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD26 ; 281 ; 5 ; SW[6] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD27 ; 286 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E17 ; 456 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 421 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 407 ; 7 ; LEDG[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E22 ; 403 ; 7 ; LEDG[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E24 ; 433 ; 7 ; LEDG[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E25 ; 434 ; 7 ; LEDG[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F18 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F21 ; 408 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; G18 ; 452 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H19 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; M23 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y23 ; 288 ; 5 ; SW[17] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y24 ; 287 ; 5 ; SW[16] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+-------------------------------+
-; Pin Name ; Reason ;
-+----------+-------------------------------+
-; LEDG[3] ; Incomplete set of assignments ;
-; LEDG[2] ; Incomplete set of assignments ;
-; LEDG[1] ; Incomplete set of assignments ;
-; LEDG[0] ; Incomplete set of assignments ;
-; LEDR[3] ; Incomplete set of assignments ;
-; LEDR[2] ; Incomplete set of assignments ;
-; LEDR[1] ; Incomplete set of assignments ;
-; LEDR[0] ; Incomplete set of assignments ;
-; SW[2] ; Incomplete set of assignments ;
-; SW[1] ; Incomplete set of assignments ;
-; SW[5] ; Incomplete set of assignments ;
-; SW[6] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-; SW[4] ; Incomplete set of assignments ;
-; SW[7] ; Incomplete set of assignments ;
-; SW[3] ; Incomplete set of assignments ;
-; SW[11] ; Incomplete set of assignments ;
-; SW[17] ; Incomplete set of assignments ;
-; SW[12] ; Incomplete set of assignments ;
-; SW[16] ; Incomplete set of assignments ;
-; SW[9] ; Incomplete set of assignments ;
-; SW[8] ; Incomplete set of assignments ;
-; SW[13] ; Incomplete set of assignments ;
-; SW[14] ; Incomplete set of assignments ;
-; SW[10] ; Incomplete set of assignments ;
-; SW[15] ; Incomplete set of assignments ;
-+----------+-------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------+-------------+--------------+
-; |CmpN_Demo ; 16 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; 16 (0) ; 0 (0) ; 0 (0) ; |CmpN_Demo ; CmpN_Demo ; work ;
-; |CmpN:inst3| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; |CmpN_Demo|CmpN:inst3 ; CmpN ; work ;
-; |CmpN:inst| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; |CmpN_Demo|CmpN:inst ; CmpN ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-----------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-; LEDG[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDG[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDG[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDG[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; SW[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[5] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[4] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[7] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[3] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[11] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[17] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[12] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[16] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[9] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[8] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[13] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; SW[14] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[10] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; SW[15] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+-------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+-------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+-------------------------------+-------------------+---------+
-; SW[2] ; ; ;
-; - CmpN:inst|LessThan1~0 ; 0 ; 6 ;
-; - CmpN:inst|Equal0~0 ; 0 ; 6 ;
-; SW[1] ; ; ;
-; - CmpN:inst|LessThan1~0 ; 0 ; 6 ;
-; - CmpN:inst|Equal0~0 ; 0 ; 6 ;
-; SW[5] ; ; ;
-; - CmpN:inst|LessThan1~0 ; 1 ; 6 ;
-; - CmpN:inst|Equal0~0 ; 1 ; 6 ;
-; SW[6] ; ; ;
-; - CmpN:inst|LessThan1~0 ; 0 ; 6 ;
-; - CmpN:inst|Equal0~0 ; 0 ; 6 ;
-; SW[0] ; ; ;
-; - CmpN:inst|LessThan1~1 ; 0 ; 6 ;
-; - CmpN:inst|Equal0~1 ; 0 ; 6 ;
-; SW[4] ; ; ;
-; - CmpN:inst|LessThan1~1 ; 1 ; 6 ;
-; - CmpN:inst|Equal0~1 ; 1 ; 6 ;
-; SW[7] ; ; ;
-; - CmpN:inst|LessThan1~2 ; 1 ; 6 ;
-; - CmpN:inst|LessThan1~4 ; 1 ; 6 ;
-; - CmpN:inst|LessThan0~0 ; 1 ; 6 ;
-; SW[3] ; ; ;
-; - CmpN:inst|LessThan1~2 ; 0 ; 6 ;
-; - CmpN:inst|LessThan1~4 ; 0 ; 6 ;
-; - CmpN:inst|LessThan0~0 ; 0 ; 6 ;
-; SW[11] ; ; ;
-; - CmpN:inst3|LessThan1~0 ; 0 ; 6 ;
-; - CmpN:inst3|LessThan1~1 ; 0 ; 6 ;
-; SW[17] ; ; ;
-; - CmpN:inst3|LessThan1~0 ; 0 ; 6 ;
-; - CmpN:inst3|LessThan1~1 ; 0 ; 6 ;
-; - CmpN:inst3|LessThan1~4 ; 0 ; 6 ;
-; - CmpN:inst3|LessThan0~0 ; 0 ; 6 ;
-; SW[12] ; ; ;
-; - CmpN:inst3|LessThan1~0 ; 1 ; 6 ;
-; - CmpN:inst3|LessThan1~1 ; 1 ; 6 ;
-; - CmpN:inst3|LessThan1~4 ; 1 ; 6 ;
-; - CmpN:inst3|LessThan0~0 ; 1 ; 6 ;
-; SW[16] ; ; ;
-; - CmpN:inst3|LessThan1~0 ; 0 ; 6 ;
-; - CmpN:inst3|LessThan1~1 ; 0 ; 6 ;
-; SW[9] ; ; ;
-; - CmpN:inst3|LessThan1~2 ; 1 ; 6 ;
-; - CmpN:inst3|Equal0~0 ; 1 ; 6 ;
-; SW[8] ; ; ;
-; - CmpN:inst3|LessThan1~2 ; 1 ; 6 ;
-; - CmpN:inst3|Equal0~0 ; 1 ; 6 ;
-; SW[13] ; ; ;
-; - CmpN:inst3|LessThan1~2 ; 1 ; 6 ;
-; - CmpN:inst3|Equal0~0 ; 1 ; 6 ;
-; SW[14] ; ; ;
-; - CmpN:inst3|LessThan1~2 ; 0 ; 6 ;
-; - CmpN:inst3|Equal0~0 ; 0 ; 6 ;
-; SW[10] ; ; ;
-; - CmpN:inst3|LessThan1~3 ; 0 ; 6 ;
-; - CmpN:inst3|Equal0~1 ; 0 ; 6 ;
-; SW[15] ; ; ;
-; - CmpN:inst3|LessThan1~3 ; 0 ; 6 ;
-; - CmpN:inst3|Equal0~1 ; 0 ; 6 ;
-+-------------------------------+-------------------+---------+
-
-
-+------------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+------------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+------------------------+
-; Block interconnects ; 27 / 342,891 ( < 1 % ) ;
-; C16 interconnects ; 20 / 10,120 ( < 1 % ) ;
-; C4 interconnects ; 44 / 209,544 ( < 1 % ) ;
-; Direct links ; 1 / 342,891 ( < 1 % ) ;
-; Global clocks ; 0 / 20 ( 0 % ) ;
-; Local interconnects ; 9 / 119,088 ( < 1 % ) ;
-; R24 interconnects ; 6 / 9,963 ( < 1 % ) ;
-; R4 interconnects ; 19 / 289,782 ( < 1 % ) ;
-+-----------------------+------------------------+
-
-
-+--------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 2) ;
-+--------------------------------------------+-----------------------------+
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 2 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-+--------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 8.00) ; Number of LABs (Total = 2) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 2 ;
-+---------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 3.00) ; Number of LABs (Total = 2) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 2 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 9.00) ; Number of LABs (Total = 2) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-; 9 ; 0 ;
-; 10 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 12 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 18 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-; Total Pass ; 0 ; 26 ; 26 ; 0 ; 0 ; 26 ; 26 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 18 ; 8 ; 0 ; 18 ; 0 ; 0 ; 8 ; 0 ; 26 ; 26 ; 26 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 26 ; 0 ; 0 ; 26 ; 26 ; 0 ; 0 ; 26 ; 26 ; 26 ; 26 ; 26 ; 26 ; 18 ; 26 ; 26 ; 26 ; 8 ; 18 ; 26 ; 8 ; 26 ; 26 ; 18 ; 26 ; 0 ; 0 ; 0 ; 26 ; 26 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; LEDG[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDG[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDG[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDG[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[11] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[17] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[12] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[16] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[9] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[13] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[14] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[10] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-; SW[15] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE115F29C7 for design "CmpN_Demo"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C7 is compatible
- Info (176445): Device EP4CE40F29I7 is compatible
- Info (176445): Device EP4CE30F29C7 is compatible
- Info (176445): Device EP4CE30F29I7 is compatible
- Info (176445): Device EP4CE55F29C7 is compatible
- Info (176445): Device EP4CE55F29I7 is compatible
- Info (176445): Device EP4CE75F29C7 is compatible
- Info (176445): Device EP4CE75F29I7 is compatible
- Info (176445): Device EP4CE115F29I7 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'CmpN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
- Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 500 warnings
- Info: Peak virtual memory: 1153 megabytes
- Info: Processing ended: Mon Mar 20 13:27:40 2023
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:09
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.smsg.
-
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.smsg b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.summary b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.summary
deleted file mode 100644
index 5df7449..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Mon Mar 20 13:27:40 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : CmpN_Demo
-Top-level Entity Name : CmpN_Demo
-Family : Cyclone IV E
-Device : EP4CE115F29C7
-Timing Models : Final
-Total logic elements : 16 / 114,480 ( < 1 % )
- Total combinational functions : 16 / 114,480 ( < 1 % )
- Dedicated logic registers : 0 / 114,480 ( 0 % )
-Total registers : 0
-Total pins : 26 / 529 ( 5 % )
-Total virtual pins : 0
-Total memory bits : 0 / 3,981,312 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.flow.rpt b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.flow.rpt
deleted file mode 100644
index 367d36d..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.flow.rpt
+++ /dev/null
@@ -1,125 +0,0 @@
-Flow report for CmpN_Demo
-Wed Mar 22 11:14:29 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Flow Failed - Wed Mar 22 11:14:29 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; CmpN_Demo ;
-; Top-level Entity Name ; CmpN ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Total logic elements ; N/A until Partition Merge ;
-; Total combinational functions ; N/A until Partition Merge ;
-; Dedicated logic registers ; N/A until Partition Merge ;
-; Total registers ; N/A until Partition Merge ;
-; Total pins ; N/A until Partition Merge ;
-; Total virtual pins ; N/A until Partition Merge ;
-; Total memory bits ; N/A until Partition Merge ;
-; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
-; Total PLLs ; N/A until Partition Merge ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 03/22/2023 11:14:23 ;
-; Main task ; Compilation ;
-; Revision Name ; CmpN_Demo ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID ; 198516037997543.167948366314280 ; -- ; -- ; -- ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
-; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
-; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; CmpN ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; CmpN ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; CmpN ; Top ;
-; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-; TOP_LEVEL_ENTITY ; CmpN ; CmpN_Demo ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 424 MB ; 00:00:18 ;
-; Total ; 00:00:07 ; -- ; -- ; 00:00:18 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
-+----------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo
-
-
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.jdi b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.jdi
deleted file mode 100644
index 4027fa2..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.map.rpt b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.map.rpt
deleted file mode 100644
index fd1fde9..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.map.rpt
+++ /dev/null
@@ -1,183 +0,0 @@
-Analysis & Synthesis report for CmpN_Demo
-Wed Mar 22 11:14:29 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Failed - Wed Mar 22 11:14:29 2023 ;
-; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Revision Name ; CmpN_Demo ;
-; Top-level Entity Name ; CmpN ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; N/A until Partition Merge ;
-; Total combinational functions ; N/A until Partition Merge ;
-; Dedicated logic registers ; N/A until Partition Merge ;
-; Total registers ; N/A until Partition Merge ;
-; Total pins ; N/A until Partition Merge ;
-; Total virtual pins ; N/A until Partition Merge ;
-; Total memory bits ; N/A until Partition Merge ;
-; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
-; Total PLLs ; N/A until Partition Merge ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE115F29C7 ; ;
-; Top-level entity name ; CmpN ; CmpN_Demo ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-+----------------------------+-------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Wed Mar 22 11:14:22 2023
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 2 design units, including 1 entities, in source file CmpN.vhd
- Info (12022): Found design unit 1: CmpN-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd Line: 18
- Info (12023): Found entity 1: CmpN File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd Line: 5
-Info (12021): Found 1 design units, including 1 entities, in source file CmpN_Demo.bdf
- Info (12023): Found entity 1: CmpN_Demo
-Info (12127): Elaborating entity "CmpN" for the top level hierarchy
-Error (10346): VHDL error at CmpN.vhd(5): formal port or parameter "N" must have actual or default value File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd Line: 5
-Error (12153): Can't elaborate top-level user hierarchy
-Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning
- Error: Peak virtual memory: 424 megabytes
- Error: Processing ended: Wed Mar 22 11:14:29 2023
- Error: Elapsed time: 00:00:07
- Error: Total CPU time (on all processors): 00:00:18
-
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.map.summary b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.map.summary
deleted file mode 100644
index 99f5cfd..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Failed - Wed Mar 22 11:14:29 2023
-Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-Revision Name : CmpN_Demo
-Top-level Entity Name : CmpN
-Family : Cyclone IV E
-Total logic elements : N/A until Partition Merge
- Total combinational functions : N/A until Partition Merge
- Dedicated logic registers : N/A until Partition Merge
-Total registers : N/A until Partition Merge
-Total pins : N/A until Partition Merge
-Total virtual pins : N/A until Partition Merge
-Total memory bits : N/A until Partition Merge
-Embedded Multiplier 9-bit elements : N/A until Partition Merge
-Total PLLs : N/A until Partition Merge
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.pin b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.pin
deleted file mode 100644
index 6ab6699..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.pin
+++ /dev/null
@@ -1,851 +0,0 @@
- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-CHIP "CmpN_Demo" ASSIGNED TO AN: EP4CE115F29C7
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A2 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-VCCIO8 : A5 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
-VCCIO8 : A9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
-VCCIO8 : A13 : power : : 2.5V : 8 :
-GND+ : A14 : : : : 8 :
-GND+ : A15 : : : : 7 :
-VCCIO7 : A16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
-VCCIO7 : A20 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
-VCCIO7 : A24 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
-VCCIO7 : A27 : power : : 2.5V : 7 :
-VCCIO2 : AA1 : power : : 2.5V : 2 :
-GND : AA2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
-GNDA1 : AA9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
-VCCIO3 : AA11 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
-VCCIO4 : AA18 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
-GNDA4 : AA20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
-SW[15] : AA22 : input : 2.5 V : : 5 : Y
-SW[14] : AA23 : input : 2.5 V : : 5 : Y
-SW[13] : AA24 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
-GND : AA27 : gnd : : : :
-VCCIO5 : AA28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
-SW[12] : AB23 : input : 2.5 V : : 5 : Y
-SW[11] : AB24 : input : 2.5 V : : 5 : Y
-SW[9] : AB25 : input : 2.5 V : : 5 : Y
-SW[7] : AB26 : input : 2.5 V : : 5 : Y
-SW[4] : AB27 : input : 2.5 V : : 5 : Y
-SW[0] : AB28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
-GND : AC6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
-GND : AC9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
-GND : AC13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
-GND : AC16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
-GND : AC20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
-GND : AC23 : gnd : : : :
-SW[10] : AC24 : input : 2.5 V : : 5 : Y
-SW[8] : AC25 : input : 2.5 V : : 5 : Y
-SW[5] : AC26 : input : 2.5 V : : 5 : Y
-SW[2] : AC27 : input : 2.5 V : : 5 : Y
-SW[1] : AC28 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
-VCCIO3 : AD6 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
-VCCIO3 : AD9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
-VCCIO3 : AD13 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
-VCCIO4 : AD16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
-VCCIO4 : AD20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
-VCCIO4 : AD23 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
-SW[6] : AD26 : input : 2.5 V : : 5 : Y
-SW[3] : AD27 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
-GND : AF1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
-GND : AF28 : gnd : : : :
-VCCIO2 : AG1 : power : : 2.5V : 2 :
-GND : AG2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
-GND : AG5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
-GND : AG13 : gnd : : : :
-GND+ : AG14 : : : : 3 :
-GND+ : AG15 : : : : 4 :
-GND : AG16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
-GND : AG20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
-GND : AG27 : gnd : : : :
-VCCIO5 : AG28 : power : : 2.5V : 5 :
-VCCIO3 : AH2 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
-VCCIO3 : AH5 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
-VCCIO3 : AH9 : power : : 2.5V : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
-VCCIO3 : AH13 : power : : 2.5V : 3 :
-GND+ : AH14 : : : : 3 :
-GND+ : AH15 : : : : 4 :
-VCCIO4 : AH16 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
-VCCIO4 : AH20 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
-VCCIO4 : AH24 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
-VCCIO4 : AH27 : power : : 2.5V : 4 :
-VCCIO1 : B1 : power : : 2.5V : 1 :
-GND : B2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
-GND : B5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
-GND : B9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
-GND : B12 : gnd : : : :
-GND : B13 : gnd : : : :
-GND+ : B14 : : : : 8 :
-GND+ : B15 : : : : 7 :
-GND : B16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
-GND : B20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
-GND : B27 : gnd : : : :
-VCCIO6 : B28 : power : : 2.5V : 6 :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
-GND : C28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
-VCCIO8 : E6 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
-VCCIO8 : E9 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
-VCCIO8 : E13 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
-VCCIO7 : E16 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7 :
-LEDR[2] : E19 : output : 2.5 V : : 7 : Y
-VCCIO7 : E20 : power : : 2.5V : 7 :
-LEDG[0] : E21 : output : 2.5 V : : 7 : Y
-LEDG[1] : E22 : output : 2.5 V : : 7 : Y
-VCCIO7 : E23 : power : : 2.5V : 7 :
-LEDG[3] : E24 : output : 2.5 V : : 7 : Y
-LEDG[2] : E25 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
-GND : F6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GND : F9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
-GND : F13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
-GND : F16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7 :
-LEDR[1] : F19 : output : 2.5 V : : 7 : Y
-GND : F20 : gnd : : : :
-LEDR[3] : F21 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
-GND : F23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
-LEDR[0] : G19 : output : 2.5 V : : 7 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
-VCCIO1 : H1 : power : : 2.5V : 1 :
-GND : H2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
-GNDA3 : H9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
-VCCIO8 : H11 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
-VCCIO7 : H18 : power : : 2.5V : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
-GNDA2 : H20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
-GND : H27 : gnd : : : :
-VCCIO6 : H28 : power : : 2.5V : 6 :
-GND+ : J1 : : : : 1 :
-GND : J2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
-VCCA3 : J8 : power : : 2.5V : :
-VCCD_PLL3 : J9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
-GND : J11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7 :
-VCCD_PLL2 : J20 : power : : 1.2V : :
-VCCA2 : J21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
-GND+ : J27 : : : : 6 :
-GND+ : J28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
-VCCIO1 : K5 : power : : 2.5V : 1 :
-GND : K6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
-VCCINT : K9 : power : : 1.2V : :
-GND : K10 : gnd : : : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-VCCINT : K13 : power : : 1.2V : :
-GND : K14 : gnd : : : :
-VCCINT : K15 : power : : 1.2V : :
-GND : K16 : gnd : : : :
-VCCINT : K17 : power : : 1.2V : :
-GND : K18 : gnd : : : :
-VCCINT : K19 : power : : 1.2V : :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
-GND : K23 : gnd : : : :
-VCCIO6 : K24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
-GND : L9 : gnd : : : :
-VCCINT : L10 : power : : 1.2V : :
-GND : L11 : gnd : : : :
-VCCINT : L12 : power : : 1.2V : :
-GND : L13 : gnd : : : :
-VCCINT : L14 : power : : 1.2V : :
-GND : L15 : gnd : : : :
-VCCINT : L16 : power : : 1.2V : :
-GND : L17 : gnd : : : :
-VCCINT : L18 : power : : 1.2V : :
-GND : L19 : gnd : : : :
-VCCINT : L20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
-nSTATUS : M6 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
-VCCINT : M9 : power : : 1.2V : :
-GND : M10 : gnd : : : :
-VCCINT : M11 : power : : 1.2V : :
-GND : M12 : gnd : : : :
-VCCINT : M13 : power : : 1.2V : :
-GND : M14 : gnd : : : :
-VCCINT : M15 : power : : 1.2V : :
-GND : M16 : gnd : : : :
-VCCINT : M17 : power : : 1.2V : :
-GND : M18 : gnd : : : :
-VCCINT : M19 : power : : 1.2V : :
-GND : M20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6 :
-MSEL2 : M22 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
-VCCIO1 : N1 : power : : 2.5V : 1 :
-GND : N2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
-VCCIO1 : N5 : power : : 2.5V : 1 :
-GND : N6 : gnd : : : :
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
-GND : N9 : gnd : : : :
-VCCINT : N10 : power : : 1.2V : :
-GND : N11 : gnd : : : :
-VCCINT : N12 : power : : 1.2V : :
-GND : N13 : gnd : : : :
-VCCINT : N14 : power : : 1.2V : :
-GND : N15 : gnd : : : :
-VCCINT : N16 : power : : 1.2V : :
-GND : N17 : gnd : : : :
-VCCINT : N18 : power : : 1.2V : :
-GND : N19 : gnd : : : :
-VCCINT : N20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
-MSEL0 : N22 : : : : 6 :
-GND : N23 : gnd : : : :
-VCCIO6 : N24 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
-GND : N27 : gnd : : : :
-VCCIO6 : N28 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
-~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
-nCONFIG : P4 : : : : 1 :
-TCK : P5 : input : : : 1 :
-TDO : P6 : output : : : 1 :
-TDI : P7 : input : : : 1 :
-TMS : P8 : input : : : 1 :
-VCCINT : P9 : power : : 1.2V : :
-GND : P10 : gnd : : : :
-VCCINT : P11 : power : : 1.2V : :
-GND : P12 : gnd : : : :
-VCCINT : P13 : power : : 1.2V : :
-GND : P14 : gnd : : : :
-VCCINT : P15 : power : : 1.2V : :
-GND : P16 : gnd : : : :
-VCCINT : P17 : power : : 1.2V : :
-GND : P18 : gnd : : : :
-VCCINT : P19 : power : : 1.2V : :
-GND : P20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
-MSEL3 : P22 : : : : 6 :
-MSEL1 : P23 : : : : 6 :
-CONF_DONE : P24 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
-nCE : R8 : : : : 1 :
-GND : R9 : gnd : : : :
-VCCINT : R10 : power : : 1.2V : :
-GND : R11 : gnd : : : :
-VCCINT : R12 : power : : 1.2V : :
-GND : R13 : gnd : : : :
-VCCINT : R14 : power : : 1.2V : :
-GND : R15 : gnd : : : :
-VCCINT : R16 : power : : 1.2V : :
-GND : R17 : gnd : : : :
-VCCINT : R18 : power : : 1.2V : :
-GND : R19 : gnd : : : :
-VCCINT : R20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
-VCCIO2 : T1 : power : : 2.5V : 2 :
-GND : T2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
-VCCIO2 : T5 : power : : 2.5V : 2 :
-GND : T6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
-VCCINT : T9 : power : : 1.2V : :
-GND : T10 : gnd : : : :
-VCCINT : T11 : power : : 1.2V : :
-GND : T12 : gnd : : : :
-VCCINT : T13 : power : : 1.2V : :
-GND : T14 : gnd : : : :
-VCCINT : T15 : power : : 1.2V : :
-GND : T16 : gnd : : : :
-VCCINT : T17 : power : : 1.2V : :
-GND : T18 : gnd : : : :
-VCCINT : T19 : power : : 1.2V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
-GND : T23 : gnd : : : :
-VCCIO5 : T24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
-GND : T27 : gnd : : : :
-VCCIO5 : T28 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
-GND : U9 : gnd : : : :
-VCCINT : U10 : power : : 1.2V : :
-GND : U11 : gnd : : : :
-VCCINT : U12 : power : : 1.2V : :
-GND : U13 : gnd : : : :
-VCCINT : U14 : power : : 1.2V : :
-GND : U15 : gnd : : : :
-VCCINT : U16 : power : : 1.2V : :
-GND : U17 : gnd : : : :
-VCCINT : U18 : power : : 1.2V : :
-GND : U19 : gnd : : : :
-VCCINT : U20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
-VCCINT : V9 : power : : 1.2V : :
-GND : V10 : gnd : : : :
-VCCINT : V11 : power : : 1.2V : :
-GND : V12 : gnd : : : :
-VCCINT : V13 : power : : 1.2V : :
-GND : V14 : gnd : : : :
-VCCINT : V15 : power : : 1.2V : :
-GND : V16 : gnd : : : :
-VCCINT : V17 : power : : 1.2V : :
-GND : V18 : gnd : : : :
-VCCINT : V19 : power : : 1.2V : :
-GND : V20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
-VCCIO2 : W5 : power : : 2.5V : 2 :
-GND : W6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
-GND : W9 : gnd : : : :
-VCCINT : W10 : power : : 1.2V : :
-GND : W11 : gnd : : : :
-VCCINT : W12 : power : : 1.2V : :
-GND : W13 : gnd : : : :
-VCCINT : W14 : power : : 1.2V : :
-GND : W15 : gnd : : : :
-VCCINT : W16 : power : : 1.2V : :
-GND : W17 : gnd : : : :
-VCCINT : W18 : power : : 1.2V : :
-GND : W19 : gnd : : : :
-VCCINT : W20 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
-GND : W23 : gnd : : : :
-VCCIO5 : W24 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
-GND+ : Y1 : : : : 2 :
-GND+ : Y2 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
-VCCA1 : Y8 : power : : 2.5V : :
-VCCD_PLL1 : Y9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
-GND : Y11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
-GND : Y18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
-VCCD_PLL4 : Y20 : power : : 1.2V : :
-VCCA4 : Y21 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
-SW[17] : Y23 : input : 2.5 V : : 5 : Y
-SW[16] : Y24 : input : 2.5 V : : 5 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
-GND+ : Y27 : : : : 5 :
-GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sld b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sta.rpt b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sta.rpt
deleted file mode 100644
index 185823a..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sta.rpt
+++ /dev/null
@@ -1,521 +0,0 @@
-Timing Analyzer report for CmpN_Demo
-Mon Mar 20 13:27:43 2023
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Metastability Summary
- 13. Slow 1200mV 0C Model Fmax Summary
- 14. Slow 1200mV 0C Model Setup Summary
- 15. Slow 1200mV 0C Model Hold Summary
- 16. Slow 1200mV 0C Model Recovery Summary
- 17. Slow 1200mV 0C Model Removal Summary
- 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1200mV 0C Model Metastability Summary
- 20. Fast 1200mV 0C Model Setup Summary
- 21. Fast 1200mV 0C Model Hold Summary
- 22. Fast 1200mV 0C Model Recovery Summary
- 23. Fast 1200mV 0C Model Removal Summary
- 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 25. Fast 1200mV 0C Model Metastability Summary
- 26. Multicorner Timing Analysis Summary
- 27. Board Trace Model Assignments
- 28. Input Transition Times
- 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 32. Clock Transfers
- 33. Report TCCS
- 34. Report RSKM
- 35. Unconstrained Paths Summary
- 36. Unconstrained Input Ports
- 37. Unconstrained Output Ports
- 38. Unconstrained Input Ports
- 39. Unconstrained Output Ports
- 40. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2020 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; CmpN_Demo ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE115F29C7 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.2% ;
-+----------------------------+-------------+
-
-
-----------
-; Clocks ;
-----------
-No clocks to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Fmax Summary ;
---------------------------------------
-No paths to report.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
----------------------------------------
-; Slow 1200mV 85C Model Setup Summary ;
----------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 85C Model Hold Summary ;
---------------------------------------
-No paths to report.
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
------------------------------------------------------
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
------------------------------------------------------
-No paths to report.
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Fmax Summary ;
--------------------------------------
-No paths to report.
-
-
---------------------------------------
-; Slow 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Slow 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
---------------------------------------
-; Fast 1200mV 0C Model Setup Summary ;
---------------------------------------
-No paths to report.
-
-
--------------------------------------
-; Fast 1200mV 0C Model Hold Summary ;
--------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-----------------------------------------------------
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
-No paths to report.
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+------+----------+---------+---------------------+
-; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-+------------------+-------+------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDG[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDG[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDG[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[11] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[17] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[12] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[16] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[13] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[14] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[10] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[15] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
--------------------
-; Clock Transfers ;
--------------------
-Nothing to report.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 18 ; 18 ;
-; Unconstrained Input Port Paths ; 72 ; 72 ;
-; Unconstrained Output Ports ; 8 ; 8 ;
-; Unconstrained Output Port Paths ; 72 ; 72 ;
-+---------------------------------+-------+------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[16] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[17] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[16] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[17] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDG[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Mon Mar 20 13:27:43 2023
-Info: Command: quartus_sta CmpN_Demo -c CmpN_Demo
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'CmpN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332159): No clocks to report
-Info: Analyzing Slow 1200mV 85C Model
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No fmax paths to report
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info: Analyzing Fast 1200mV 0C Model
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
-Warning (332068): No clocks defined in design.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332140): No Setup paths to report
-Info (332140): No Hold paths to report
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332140): No Minimum Pulse Width paths to report
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 536 megabytes
- Info: Processing ended: Mon Mar 20 13:27:43 2023
- Info: Elapsed time: 00:00:00
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sta.summary b/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sta.summary
deleted file mode 100644
index aa5b327..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sta.summary
+++ /dev/null
@@ -1,5 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo.sft b/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo.vho b/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo.vho
deleted file mode 100644
index 8e81e8a..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo.vho
+++ /dev/null
@@ -1,773 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/20/2023 13:27:44"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY hard_block IS
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic
- );
-END hard_block;
-
--- Design Ports Information
--- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
--- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
-
-
-ARCHITECTURE structure OF hard_block IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
-SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
-SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
-
-BEGIN
-
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-END structure;
-
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY CmpN_Demo IS
- PORT (
- LEDG : OUT std_logic_vector(3 DOWNTO 0);
- SW : IN std_logic_vector(17 DOWNTO 0);
- LEDR : OUT std_logic_vector(3 DOWNTO 0)
- );
-END CmpN_Demo;
-
--- Design Ports Information
--- LEDG[3] => Location: PIN_E24, I/O Standard: 2.5 V, Current Strength: Default
--- LEDG[2] => Location: PIN_E25, I/O Standard: 2.5 V, Current Strength: Default
--- LEDG[1] => Location: PIN_E22, I/O Standard: 2.5 V, Current Strength: Default
--- LEDG[0] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
--- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
--- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
--- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
--- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
--- SW[11] => Location: PIN_AB24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[17] => Location: PIN_Y23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[12] => Location: PIN_AB23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[16] => Location: PIN_Y24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[9] => Location: PIN_AB25, I/O Standard: 2.5 V, Current Strength: Default
--- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default
--- SW[13] => Location: PIN_AA24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[14] => Location: PIN_AA23, I/O Standard: 2.5 V, Current Strength: Default
--- SW[10] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default
--- SW[15] => Location: PIN_AA22, I/O Standard: 2.5 V, Current Strength: Default
-
-
-ARCHITECTURE structure OF CmpN_Demo IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_LEDG : std_logic_vector(3 DOWNTO 0);
-SIGNAL ww_SW : std_logic_vector(17 DOWNTO 0);
-SIGNAL ww_LEDR : std_logic_vector(3 DOWNTO 0);
-SIGNAL \LEDG[3]~output_o\ : std_logic;
-SIGNAL \LEDG[2]~output_o\ : std_logic;
-SIGNAL \LEDG[1]~output_o\ : std_logic;
-SIGNAL \LEDG[0]~output_o\ : std_logic;
-SIGNAL \LEDR[3]~output_o\ : std_logic;
-SIGNAL \LEDR[2]~output_o\ : std_logic;
-SIGNAL \LEDR[1]~output_o\ : std_logic;
-SIGNAL \LEDR[0]~output_o\ : std_logic;
-SIGNAL \SW[3]~input_o\ : std_logic;
-SIGNAL \SW[7]~input_o\ : std_logic;
-SIGNAL \inst|LessThan1~2_combout\ : std_logic;
-SIGNAL \SW[4]~input_o\ : std_logic;
-SIGNAL \SW[0]~input_o\ : std_logic;
-SIGNAL \inst|LessThan1~1_combout\ : std_logic;
-SIGNAL \SW[1]~input_o\ : std_logic;
-SIGNAL \SW[5]~input_o\ : std_logic;
-SIGNAL \SW[6]~input_o\ : std_logic;
-SIGNAL \SW[2]~input_o\ : std_logic;
-SIGNAL \inst|Equal0~0_combout\ : std_logic;
-SIGNAL \inst|LessThan1~0_combout\ : std_logic;
-SIGNAL \inst|LessThan1~3_combout\ : std_logic;
-SIGNAL \inst|LessThan1~4_combout\ : std_logic;
-SIGNAL \inst|LessThan0~0_combout\ : std_logic;
-SIGNAL \inst|Equal0~1_combout\ : std_logic;
-SIGNAL \SW[17]~input_o\ : std_logic;
-SIGNAL \SW[12]~input_o\ : std_logic;
-SIGNAL \SW[11]~input_o\ : std_logic;
-SIGNAL \SW[16]~input_o\ : std_logic;
-SIGNAL \inst3|LessThan1~1_combout\ : std_logic;
-SIGNAL \SW[13]~input_o\ : std_logic;
-SIGNAL \SW[9]~input_o\ : std_logic;
-SIGNAL \SW[8]~input_o\ : std_logic;
-SIGNAL \SW[14]~input_o\ : std_logic;
-SIGNAL \inst3|LessThan1~2_combout\ : std_logic;
-SIGNAL \SW[10]~input_o\ : std_logic;
-SIGNAL \SW[15]~input_o\ : std_logic;
-SIGNAL \inst3|LessThan1~3_combout\ : std_logic;
-SIGNAL \inst3|LessThan1~0_combout\ : std_logic;
-SIGNAL \inst3|LessThan1~4_combout\ : std_logic;
-SIGNAL \inst3|LessThan0~0_combout\ : std_logic;
-SIGNAL \inst3|Equal0~0_combout\ : std_logic;
-SIGNAL \inst3|Equal0~1_combout\ : std_logic;
-SIGNAL \inst3|ALT_INV_Equal0~1_combout\ : std_logic;
-SIGNAL \inst|ALT_INV_Equal0~1_combout\ : std_logic;
-
-COMPONENT hard_block
- PORT (
- devoe : IN std_logic;
- devclrn : IN std_logic;
- devpor : IN std_logic);
-END COMPONENT;
-
-BEGIN
-
-LEDG <= ww_LEDG;
-ww_SW <= SW;
-LEDR <= ww_LEDR;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\inst3|ALT_INV_Equal0~1_combout\ <= NOT \inst3|Equal0~1_combout\;
-\inst|ALT_INV_Equal0~1_combout\ <= NOT \inst|Equal0~1_combout\;
-auto_generated_inst : hard_block
-PORT MAP (
- devoe => ww_devoe,
- devclrn => ww_devclrn,
- devpor => ww_devpor);
-
--- Location: IOOBUF_X85_Y73_N23
-\LEDG[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|LessThan1~4_combout\,
- devoe => ww_devoe,
- o => \LEDG[3]~output_o\);
-
--- Location: IOOBUF_X83_Y73_N2
-\LEDG[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|LessThan0~0_combout\,
- devoe => ww_devoe,
- o => \LEDG[2]~output_o\);
-
--- Location: IOOBUF_X111_Y73_N9
-\LEDG[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|ALT_INV_Equal0~1_combout\,
- devoe => ww_devoe,
- o => \LEDG[1]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N9
-\LEDG[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst|Equal0~1_combout\,
- devoe => ww_devoe,
- o => \LEDG[0]~output_o\);
-
--- Location: IOOBUF_X107_Y73_N16
-\LEDR[3]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst3|LessThan1~4_combout\,
- devoe => ww_devoe,
- o => \LEDR[3]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N9
-\LEDR[2]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst3|LessThan0~0_combout\,
- devoe => ww_devoe,
- o => \LEDR[2]~output_o\);
-
--- Location: IOOBUF_X94_Y73_N2
-\LEDR[1]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst3|ALT_INV_Equal0~1_combout\,
- devoe => ww_devoe,
- o => \LEDR[1]~output_o\);
-
--- Location: IOOBUF_X69_Y73_N16
-\LEDR[0]~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \inst3|Equal0~1_combout\,
- devoe => ww_devoe,
- o => \LEDR[0]~output_o\);
-
--- Location: IOIBUF_X115_Y13_N8
-\SW[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(3),
- o => \SW[3]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N1
-\SW[7]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(7),
- o => \SW[7]~input_o\);
-
--- Location: LCCOMB_X114_Y17_N6
-\inst|LessThan1~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|LessThan1~2_combout\ = \SW[3]~input_o\ $ (\SW[7]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101101001011010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datac => \SW[7]~input_o\,
- combout => \inst|LessThan1~2_combout\);
-
--- Location: IOIBUF_X115_Y18_N8
-\SW[4]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(4),
- o => \SW[4]~input_o\);
-
--- Location: IOIBUF_X115_Y17_N1
-\SW[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(0),
- o => \SW[0]~input_o\);
-
--- Location: LCCOMB_X114_Y17_N4
-\inst|LessThan1~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|LessThan1~1_combout\ = (!\SW[4]~input_o\ & \SW[0]~input_o\)
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000111100000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- datac => \SW[4]~input_o\,
- datad => \SW[0]~input_o\,
- combout => \inst|LessThan1~1_combout\);
-
--- Location: IOIBUF_X115_Y14_N1
-\SW[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(1),
- o => \SW[1]~input_o\);
-
--- Location: IOIBUF_X115_Y11_N8
-\SW[5]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(5),
- o => \SW[5]~input_o\);
-
--- Location: IOIBUF_X115_Y10_N1
-\SW[6]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(6),
- o => \SW[6]~input_o\);
-
--- Location: IOIBUF_X115_Y15_N8
-\SW[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(2),
- o => \SW[2]~input_o\);
-
--- Location: LCCOMB_X114_Y17_N26
-\inst|Equal0~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|Equal0~0_combout\ = (\SW[1]~input_o\ & (\SW[5]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\)))) # (!\SW[1]~input_o\ & (!\SW[5]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001000000001001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[1]~input_o\,
- datab => \SW[5]~input_o\,
- datac => \SW[6]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \inst|Equal0~0_combout\);
-
--- Location: LCCOMB_X114_Y17_N24
-\inst|LessThan1~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|LessThan1~0_combout\ = (\SW[6]~input_o\ & (\SW[1]~input_o\ & (!\SW[5]~input_o\ & \SW[2]~input_o\))) # (!\SW[6]~input_o\ & ((\SW[2]~input_o\) # ((\SW[1]~input_o\ & !\SW[5]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0010111100000010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[1]~input_o\,
- datab => \SW[5]~input_o\,
- datac => \SW[6]~input_o\,
- datad => \SW[2]~input_o\,
- combout => \inst|LessThan1~0_combout\);
-
--- Location: LCCOMB_X114_Y17_N0
-\inst|LessThan1~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|LessThan1~3_combout\ = (!\inst|LessThan1~2_combout\ & ((\inst|LessThan1~0_combout\) # ((\inst|LessThan1~1_combout\ & \inst|Equal0~0_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0101010101000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|LessThan1~2_combout\,
- datab => \inst|LessThan1~1_combout\,
- datac => \inst|Equal0~0_combout\,
- datad => \inst|LessThan1~0_combout\,
- combout => \inst|LessThan1~3_combout\);
-
--- Location: LCCOMB_X114_Y17_N10
-\inst|LessThan1~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|LessThan1~4_combout\ = (\inst|LessThan1~3_combout\) # ((\SW[3]~input_o\ & !\SW[7]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1100111011001110",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \inst|LessThan1~3_combout\,
- datac => \SW[7]~input_o\,
- combout => \inst|LessThan1~4_combout\);
-
--- Location: LCCOMB_X114_Y17_N12
-\inst|LessThan0~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|LessThan0~0_combout\ = (\inst|LessThan1~3_combout\) # ((!\SW[3]~input_o\ & \SW[7]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1101110011011100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[3]~input_o\,
- datab => \inst|LessThan1~3_combout\,
- datac => \SW[7]~input_o\,
- combout => \inst|LessThan0~0_combout\);
-
--- Location: LCCOMB_X114_Y17_N22
-\inst|Equal0~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst|Equal0~1_combout\ = (\inst|Equal0~0_combout\ & (!\inst|LessThan1~2_combout\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000010000010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst|Equal0~0_combout\,
- datab => \SW[0]~input_o\,
- datac => \SW[4]~input_o\,
- datad => \inst|LessThan1~2_combout\,
- combout => \inst|Equal0~1_combout\);
-
--- Location: IOIBUF_X115_Y14_N8
-\SW[17]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(17),
- o => \SW[17]~input_o\);
-
--- Location: IOIBUF_X115_Y7_N15
-\SW[12]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(12),
- o => \SW[12]~input_o\);
-
--- Location: IOIBUF_X115_Y5_N15
-\SW[11]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(11),
- o => \SW[11]~input_o\);
-
--- Location: IOIBUF_X115_Y13_N1
-\SW[16]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(16),
- o => \SW[16]~input_o\);
-
--- Location: LCCOMB_X114_Y10_N10
-\inst3|LessThan1~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst3|LessThan1~1_combout\ = (\SW[17]~input_o\ & (\SW[12]~input_o\ & (\SW[11]~input_o\ $ (!\SW[16]~input_o\)))) # (!\SW[17]~input_o\ & (!\SW[12]~input_o\ & (\SW[11]~input_o\ $ (!\SW[16]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1001000000001001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[17]~input_o\,
- datab => \SW[12]~input_o\,
- datac => \SW[11]~input_o\,
- datad => \SW[16]~input_o\,
- combout => \inst3|LessThan1~1_combout\);
-
--- Location: IOIBUF_X115_Y9_N22
-\SW[13]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(13),
- o => \SW[13]~input_o\);
-
--- Location: IOIBUF_X115_Y16_N8
-\SW[9]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(9),
- o => \SW[9]~input_o\);
-
--- Location: IOIBUF_X115_Y4_N22
-\SW[8]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(8),
- o => \SW[8]~input_o\);
-
--- Location: IOIBUF_X115_Y10_N8
-\SW[14]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(14),
- o => \SW[14]~input_o\);
-
--- Location: LCCOMB_X114_Y10_N28
-\inst3|LessThan1~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst3|LessThan1~2_combout\ = (\SW[9]~input_o\ & (((!\SW[13]~input_o\ & \SW[8]~input_o\)) # (!\SW[14]~input_o\))) # (!\SW[9]~input_o\ & (!\SW[13]~input_o\ & (\SW[8]~input_o\ & !\SW[14]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0100000011011100",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[13]~input_o\,
- datab => \SW[9]~input_o\,
- datac => \SW[8]~input_o\,
- datad => \SW[14]~input_o\,
- combout => \inst3|LessThan1~2_combout\);
-
--- Location: IOIBUF_X115_Y4_N15
-\SW[10]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(10),
- o => \SW[10]~input_o\);
-
--- Location: IOIBUF_X115_Y6_N15
-\SW[15]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SW(15),
- o => \SW[15]~input_o\);
-
--- Location: LCCOMB_X114_Y10_N6
-\inst3|LessThan1~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst3|LessThan1~3_combout\ = (\inst3|LessThan1~1_combout\ & ((\inst3|LessThan1~2_combout\ & ((\SW[10]~input_o\) # (!\SW[15]~input_o\))) # (!\inst3|LessThan1~2_combout\ & (\SW[10]~input_o\ & !\SW[15]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000000010101000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst3|LessThan1~1_combout\,
- datab => \inst3|LessThan1~2_combout\,
- datac => \SW[10]~input_o\,
- datad => \SW[15]~input_o\,
- combout => \inst3|LessThan1~3_combout\);
-
--- Location: LCCOMB_X114_Y10_N24
-\inst3|LessThan1~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst3|LessThan1~0_combout\ = (\SW[11]~input_o\ & (!\SW[16]~input_o\ & (\SW[17]~input_o\ $ (!\SW[12]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000010010000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[17]~input_o\,
- datab => \SW[12]~input_o\,
- datac => \SW[11]~input_o\,
- datad => \SW[16]~input_o\,
- combout => \inst3|LessThan1~0_combout\);
-
--- Location: LCCOMB_X114_Y10_N8
-\inst3|LessThan1~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst3|LessThan1~4_combout\ = (\inst3|LessThan1~3_combout\) # ((\inst3|LessThan1~0_combout\) # ((\SW[12]~input_o\ & !\SW[17]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111101011111110",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst3|LessThan1~3_combout\,
- datab => \SW[12]~input_o\,
- datac => \inst3|LessThan1~0_combout\,
- datad => \SW[17]~input_o\,
- combout => \inst3|LessThan1~4_combout\);
-
--- Location: LCCOMB_X114_Y10_N26
-\inst3|LessThan0~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst3|LessThan0~0_combout\ = (\inst3|LessThan1~3_combout\) # ((\inst3|LessThan1~0_combout\) # ((!\SW[12]~input_o\ & \SW[17]~input_o\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1111101111111010",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst3|LessThan1~3_combout\,
- datab => \SW[12]~input_o\,
- datac => \inst3|LessThan1~0_combout\,
- datad => \SW[17]~input_o\,
- combout => \inst3|LessThan0~0_combout\);
-
--- Location: LCCOMB_X114_Y10_N12
-\inst3|Equal0~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst3|Equal0~0_combout\ = (\SW[13]~input_o\ & (\SW[8]~input_o\ & (\SW[9]~input_o\ $ (!\SW[14]~input_o\)))) # (!\SW[13]~input_o\ & (!\SW[8]~input_o\ & (\SW[9]~input_o\ $ (!\SW[14]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000010000100001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \SW[13]~input_o\,
- datab => \SW[9]~input_o\,
- datac => \SW[8]~input_o\,
- datad => \SW[14]~input_o\,
- combout => \inst3|Equal0~0_combout\);
-
--- Location: LCCOMB_X114_Y10_N14
-\inst3|Equal0~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \inst3|Equal0~1_combout\ = (\inst3|Equal0~0_combout\ & (\inst3|LessThan1~1_combout\ & (\SW[15]~input_o\ $ (!\SW[10]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000001000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \inst3|Equal0~0_combout\,
- datab => \SW[15]~input_o\,
- datac => \SW[10]~input_o\,
- datad => \inst3|LessThan1~1_combout\,
- combout => \inst3|Equal0~1_combout\);
-
-ww_LEDG(3) <= \LEDG[3]~output_o\;
-
-ww_LEDG(2) <= \LEDG[2]~output_o\;
-
-ww_LEDG(1) <= \LEDG[1]~output_o\;
-
-ww_LEDG(0) <= \LEDG[0]~output_o\;
-
-ww_LEDR(3) <= \LEDR[3]~output_o\;
-
-ww_LEDR(2) <= \LEDR[2]~output_o\;
-
-ww_LEDR(1) <= \LEDR[1]~output_o\;
-
-ww_LEDR(0) <= \LEDR[0]~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo_modelsim.xrf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo_modelsim.xrf
deleted file mode 100644
index 5f8288d..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo_modelsim.xrf
+++ /dev/null
@@ -1,53 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cbx.xml
-design_name = hard_block
-design_name = CmpN_Demo
-instance = comp, \LEDG[3]~output\, LEDG[3]~output, CmpN_Demo, 1
-instance = comp, \LEDG[2]~output\, LEDG[2]~output, CmpN_Demo, 1
-instance = comp, \LEDG[1]~output\, LEDG[1]~output, CmpN_Demo, 1
-instance = comp, \LEDG[0]~output\, LEDG[0]~output, CmpN_Demo, 1
-instance = comp, \LEDR[3]~output\, LEDR[3]~output, CmpN_Demo, 1
-instance = comp, \LEDR[2]~output\, LEDR[2]~output, CmpN_Demo, 1
-instance = comp, \LEDR[1]~output\, LEDR[1]~output, CmpN_Demo, 1
-instance = comp, \LEDR[0]~output\, LEDR[0]~output, CmpN_Demo, 1
-instance = comp, \SW[3]~input\, SW[3]~input, CmpN_Demo, 1
-instance = comp, \SW[7]~input\, SW[7]~input, CmpN_Demo, 1
-instance = comp, \inst|LessThan1~2\, inst|LessThan1~2, CmpN_Demo, 1
-instance = comp, \SW[4]~input\, SW[4]~input, CmpN_Demo, 1
-instance = comp, \SW[0]~input\, SW[0]~input, CmpN_Demo, 1
-instance = comp, \inst|LessThan1~1\, inst|LessThan1~1, CmpN_Demo, 1
-instance = comp, \SW[1]~input\, SW[1]~input, CmpN_Demo, 1
-instance = comp, \SW[5]~input\, SW[5]~input, CmpN_Demo, 1
-instance = comp, \SW[6]~input\, SW[6]~input, CmpN_Demo, 1
-instance = comp, \SW[2]~input\, SW[2]~input, CmpN_Demo, 1
-instance = comp, \inst|Equal0~0\, inst|Equal0~0, CmpN_Demo, 1
-instance = comp, \inst|LessThan1~0\, inst|LessThan1~0, CmpN_Demo, 1
-instance = comp, \inst|LessThan1~3\, inst|LessThan1~3, CmpN_Demo, 1
-instance = comp, \inst|LessThan1~4\, inst|LessThan1~4, CmpN_Demo, 1
-instance = comp, \inst|LessThan0~0\, inst|LessThan0~0, CmpN_Demo, 1
-instance = comp, \inst|Equal0~1\, inst|Equal0~1, CmpN_Demo, 1
-instance = comp, \SW[17]~input\, SW[17]~input, CmpN_Demo, 1
-instance = comp, \SW[12]~input\, SW[12]~input, CmpN_Demo, 1
-instance = comp, \SW[11]~input\, SW[11]~input, CmpN_Demo, 1
-instance = comp, \SW[16]~input\, SW[16]~input, CmpN_Demo, 1
-instance = comp, \inst3|LessThan1~1\, inst3|LessThan1~1, CmpN_Demo, 1
-instance = comp, \SW[13]~input\, SW[13]~input, CmpN_Demo, 1
-instance = comp, \SW[9]~input\, SW[9]~input, CmpN_Demo, 1
-instance = comp, \SW[8]~input\, SW[8]~input, CmpN_Demo, 1
-instance = comp, \SW[14]~input\, SW[14]~input, CmpN_Demo, 1
-instance = comp, \inst3|LessThan1~2\, inst3|LessThan1~2, CmpN_Demo, 1
-instance = comp, \SW[10]~input\, SW[10]~input, CmpN_Demo, 1
-instance = comp, \SW[15]~input\, SW[15]~input, CmpN_Demo, 1
-instance = comp, \inst3|LessThan1~3\, inst3|LessThan1~3, CmpN_Demo, 1
-instance = comp, \inst3|LessThan1~0\, inst3|LessThan1~0, CmpN_Demo, 1
-instance = comp, \inst3|LessThan1~4\, inst3|LessThan1~4, CmpN_Demo, 1
-instance = comp, \inst3|LessThan0~0\, inst3|LessThan0~0, CmpN_Demo, 1
-instance = comp, \inst3|Equal0~0\, inst3|Equal0~0, CmpN_Demo, 1
-instance = comp, \inst3|Equal0~1\, inst3|Equal0~1, CmpN_Demo, 1
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/Cmp8.vwf.vht b/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/Cmp8.vwf.vht
deleted file mode 100644
index f5edf6e..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/Cmp8.vwf.vht
+++ /dev/null
@@ -1,226 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- *****************************************************************************
--- This file contains a Vhdl test bench with test vectors .The test vectors
--- are exported from a vector file in the Quartus Waveform Editor and apply to
--- the top level entity of the current Quartus project .The user can use this
--- testbench to simulate his design using a third-party simulation tool .
--- *****************************************************************************
--- Generated on "03/17/2023 12:07:03"
-
--- Vhdl Test Bench(with test vectors) for design : CmpN
---
--- Simulation tool : 3rd Party
---
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY CmpN_vhd_vec_tst IS
-END CmpN_vhd_vec_tst;
-ARCHITECTURE CmpN_arch OF CmpN_vhd_vec_tst IS
--- constants
--- signals
-SIGNAL equal : STD_LOGIC;
-SIGNAL input0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL input1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL ltSigned : STD_LOGIC;
-SIGNAL ltUnsigned : STD_LOGIC;
-SIGNAL notEqual : STD_LOGIC;
-COMPONENT CmpN
- PORT (
- equal : OUT STD_LOGIC;
- input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- ltSigned : OUT STD_LOGIC;
- ltUnsigned : OUT STD_LOGIC;
- notEqual : OUT STD_LOGIC
- );
-END COMPONENT;
-BEGIN
- i1 : CmpN
- PORT MAP (
--- list connections between master ports and signals
- equal => equal,
- input0 => input0,
- input1 => input1,
- ltSigned => ltSigned,
- ltUnsigned => ltUnsigned,
- notEqual => notEqual
- );
--- input0[7]
-t_prcs_input0_7: PROCESS
-BEGIN
- input0(7) <= '0';
- WAIT FOR 80000 ps;
- input0(7) <= '1';
- WAIT FOR 80000 ps;
- input0(7) <= '0';
-WAIT;
-END PROCESS t_prcs_input0_7;
--- input0[6]
-t_prcs_input0_6: PROCESS
-BEGIN
- input0(6) <= '1';
- WAIT FOR 80000 ps;
- input0(6) <= '0';
- WAIT FOR 80000 ps;
- input0(6) <= '1';
- WAIT FOR 80000 ps;
- input0(6) <= '0';
-WAIT;
-END PROCESS t_prcs_input0_6;
--- input0[5]
-t_prcs_input0_5: PROCESS
-BEGIN
- input0(5) <= '1';
- WAIT FOR 80000 ps;
- input0(5) <= '0';
- WAIT FOR 80000 ps;
- input0(5) <= '1';
- WAIT FOR 80000 ps;
- input0(5) <= '0';
-WAIT;
-END PROCESS t_prcs_input0_5;
--- input0[4]
-t_prcs_input0_4: PROCESS
-BEGIN
- input0(4) <= '1';
- WAIT FOR 80000 ps;
- input0(4) <= '0';
- WAIT FOR 80000 ps;
- input0(4) <= '1';
- WAIT FOR 80000 ps;
- input0(4) <= '0';
-WAIT;
-END PROCESS t_prcs_input0_4;
--- input0[3]
-t_prcs_input0_3: PROCESS
-BEGIN
- input0(3) <= '1';
- WAIT FOR 80000 ps;
- input0(3) <= '0';
- WAIT FOR 80000 ps;
- input0(3) <= '1';
- WAIT FOR 80000 ps;
- input0(3) <= '0';
-WAIT;
-END PROCESS t_prcs_input0_3;
--- input0[2]
-t_prcs_input0_2: PROCESS
-BEGIN
- input0(2) <= '1';
- WAIT FOR 80000 ps;
- input0(2) <= '0';
- WAIT FOR 80000 ps;
- input0(2) <= '1';
- WAIT FOR 80000 ps;
- input0(2) <= '0';
-WAIT;
-END PROCESS t_prcs_input0_2;
--- input0[1]
-t_prcs_input0_1: PROCESS
-BEGIN
- input0(1) <= '1';
- WAIT FOR 80000 ps;
- input0(1) <= '0';
- WAIT FOR 80000 ps;
- input0(1) <= '1';
- WAIT FOR 80000 ps;
- input0(1) <= '0';
-WAIT;
-END PROCESS t_prcs_input0_1;
--- input0[0]
-t_prcs_input0_0: PROCESS
-BEGIN
- input0(0) <= '1';
- WAIT FOR 80000 ps;
- input0(0) <= '0';
- WAIT FOR 80000 ps;
- input0(0) <= '1';
- WAIT FOR 80000 ps;
- input0(0) <= '0';
-WAIT;
-END PROCESS t_prcs_input0_0;
--- input1[7]
-t_prcs_input1_7: PROCESS
-BEGIN
- input1(7) <= '1';
- WAIT FOR 80000 ps;
- input1(7) <= '0';
- WAIT FOR 80000 ps;
- input1(7) <= '1';
- WAIT FOR 80000 ps;
- input1(7) <= '0';
-WAIT;
-END PROCESS t_prcs_input1_7;
--- input1[6]
-t_prcs_input1_6: PROCESS
-BEGIN
- input1(6) <= '1';
- WAIT FOR 80000 ps;
- input1(6) <= '0';
-WAIT;
-END PROCESS t_prcs_input1_6;
--- input1[5]
-t_prcs_input1_5: PROCESS
-BEGIN
- input1(5) <= '1';
- WAIT FOR 80000 ps;
- input1(5) <= '0';
-WAIT;
-END PROCESS t_prcs_input1_5;
--- input1[4]
-t_prcs_input1_4: PROCESS
-BEGIN
- input1(4) <= '1';
- WAIT FOR 80000 ps;
- input1(4) <= '0';
-WAIT;
-END PROCESS t_prcs_input1_4;
--- input1[3]
-t_prcs_input1_3: PROCESS
-BEGIN
- input1(3) <= '1';
- WAIT FOR 80000 ps;
- input1(3) <= '0';
-WAIT;
-END PROCESS t_prcs_input1_3;
--- input1[2]
-t_prcs_input1_2: PROCESS
-BEGIN
- input1(2) <= '1';
- WAIT FOR 80000 ps;
- input1(2) <= '0';
-WAIT;
-END PROCESS t_prcs_input1_2;
--- input1[1]
-t_prcs_input1_1: PROCESS
-BEGIN
- input1(1) <= '1';
- WAIT FOR 80000 ps;
- input1(1) <= '0';
-WAIT;
-END PROCESS t_prcs_input1_1;
--- input1[0]
-t_prcs_input1_0: PROCESS
-BEGIN
- input1(0) <= '1';
- WAIT FOR 80000 ps;
- input1(0) <= '0';
-WAIT;
-END PROCESS t_prcs_input1_0;
-END CmpN_arch;
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.do b/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.do
deleted file mode 100644
index 7bd22cf..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.do
+++ /dev/null
@@ -1,17 +0,0 @@
-onerror {exit -code 1}
-vlib work
-vcom -work work CmpN_Demo.vho
-vcom work Cmp8.vwf.vht
-vsim -novopt -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CmpN_vhd_vec_tst
-vcd file -direction CmpN_Demo.msim.vcd
-vcd add -internal CmpN_vhd_vec_tst/*
-vcd add -internal CmpN_vhd_vec_tst/i1/*
-proc simTimestamp {} {
- echo "Simulation time: $::now ps"
- if { [string equal running [runStatus]] } {
- after 2500 simTimestamp
- }
-}
-after 2500 simTimestamp
-run -all
-quit -f
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.sft b/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.vho b/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.vho
deleted file mode 100644
index 9ff5618..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.vho
+++ /dev/null
@@ -1,663 +0,0 @@
--- Copyright (C) 2020 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details, at
--- https://fpgasoftware.intel.com/eula.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-
--- DATE "03/17/2023 12:07:04"
-
---
--- Device: Altera EP4CE115F29C7 Package FBGA780
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY CYCLONEIVE;
-LIBRARY IEEE;
-USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY CmpN IS
- PORT (
- input0 : IN std_logic_vector(7 DOWNTO 0);
- input1 : IN std_logic_vector(7 DOWNTO 0);
- equal : OUT std_logic;
- notEqual : OUT std_logic;
- ltSigned : OUT std_logic;
- ltUnsigned : OUT std_logic
- );
-END CmpN;
-
-ARCHITECTURE structure OF CmpN IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_input0 : std_logic_vector(7 DOWNTO 0);
-SIGNAL ww_input1 : std_logic_vector(7 DOWNTO 0);
-SIGNAL ww_equal : std_logic;
-SIGNAL ww_notEqual : std_logic;
-SIGNAL ww_ltSigned : std_logic;
-SIGNAL ww_ltUnsigned : std_logic;
-SIGNAL \equal~output_o\ : std_logic;
-SIGNAL \notEqual~output_o\ : std_logic;
-SIGNAL \ltSigned~output_o\ : std_logic;
-SIGNAL \ltUnsigned~output_o\ : std_logic;
-SIGNAL \input0[0]~input_o\ : std_logic;
-SIGNAL \input0[1]~input_o\ : std_logic;
-SIGNAL \input1[1]~input_o\ : std_logic;
-SIGNAL \input1[0]~input_o\ : std_logic;
-SIGNAL \Equal0~0_combout\ : std_logic;
-SIGNAL \input0[2]~input_o\ : std_logic;
-SIGNAL \input0[3]~input_o\ : std_logic;
-SIGNAL \input1[3]~input_o\ : std_logic;
-SIGNAL \input1[2]~input_o\ : std_logic;
-SIGNAL \Equal0~1_combout\ : std_logic;
-SIGNAL \input0[4]~input_o\ : std_logic;
-SIGNAL \input0[5]~input_o\ : std_logic;
-SIGNAL \input1[5]~input_o\ : std_logic;
-SIGNAL \input1[4]~input_o\ : std_logic;
-SIGNAL \Equal0~2_combout\ : std_logic;
-SIGNAL \input0[6]~input_o\ : std_logic;
-SIGNAL \input0[7]~input_o\ : std_logic;
-SIGNAL \input1[7]~input_o\ : std_logic;
-SIGNAL \input1[6]~input_o\ : std_logic;
-SIGNAL \Equal0~3_combout\ : std_logic;
-SIGNAL \Equal0~4_combout\ : std_logic;
-SIGNAL \LessThan0~1_cout\ : std_logic;
-SIGNAL \LessThan0~3_cout\ : std_logic;
-SIGNAL \LessThan0~5_cout\ : std_logic;
-SIGNAL \LessThan0~7_cout\ : std_logic;
-SIGNAL \LessThan0~9_cout\ : std_logic;
-SIGNAL \LessThan0~11_cout\ : std_logic;
-SIGNAL \LessThan0~13_cout\ : std_logic;
-SIGNAL \LessThan0~14_combout\ : std_logic;
-SIGNAL \LessThan1~1_cout\ : std_logic;
-SIGNAL \LessThan1~3_cout\ : std_logic;
-SIGNAL \LessThan1~5_cout\ : std_logic;
-SIGNAL \LessThan1~7_cout\ : std_logic;
-SIGNAL \LessThan1~9_cout\ : std_logic;
-SIGNAL \LessThan1~11_cout\ : std_logic;
-SIGNAL \LessThan1~13_cout\ : std_logic;
-SIGNAL \LessThan1~14_combout\ : std_logic;
-SIGNAL \ALT_INV_Equal0~4_combout\ : std_logic;
-
-BEGIN
-
-ww_input0 <= input0;
-ww_input1 <= input1;
-equal <= ww_equal;
-notEqual <= ww_notEqual;
-ltSigned <= ww_ltSigned;
-ltUnsigned <= ww_ltUnsigned;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-\ALT_INV_Equal0~4_combout\ <= NOT \Equal0~4_combout\;
-
-\equal~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \Equal0~4_combout\,
- devoe => ww_devoe,
- o => \equal~output_o\);
-
-\notEqual~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \ALT_INV_Equal0~4_combout\,
- devoe => ww_devoe,
- o => \notEqual~output_o\);
-
-\ltSigned~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \LessThan0~14_combout\,
- devoe => ww_devoe,
- o => \ltSigned~output_o\);
-
-\ltUnsigned~output\ : cycloneive_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false")
--- pragma translate_on
-PORT MAP (
- i => \LessThan1~14_combout\,
- devoe => ww_devoe,
- o => \ltUnsigned~output_o\);
-
-\input0[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input0(0),
- o => \input0[0]~input_o\);
-
-\input0[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input0(1),
- o => \input0[1]~input_o\);
-
-\input1[1]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input1(1),
- o => \input1[1]~input_o\);
-
-\input1[0]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input1(0),
- o => \input1[0]~input_o\);
-
-\Equal0~0\ : cycloneive_lcell_comb
--- Equation(s):
--- \Equal0~0_combout\ = (\input0[0]~input_o\ & (\input1[0]~input_o\ & (\input0[1]~input_o\ $ (!\input1[1]~input_o\)))) # (!\input0[0]~input_o\ & (!\input1[0]~input_o\ & (\input0[1]~input_o\ $ (!\input1[1]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000001001000001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[0]~input_o\,
- datab => \input0[1]~input_o\,
- datac => \input1[1]~input_o\,
- datad => \input1[0]~input_o\,
- combout => \Equal0~0_combout\);
-
-\input0[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input0(2),
- o => \input0[2]~input_o\);
-
-\input0[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input0(3),
- o => \input0[3]~input_o\);
-
-\input1[3]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input1(3),
- o => \input1[3]~input_o\);
-
-\input1[2]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input1(2),
- o => \input1[2]~input_o\);
-
-\Equal0~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \Equal0~1_combout\ = (\input0[2]~input_o\ & (\input1[2]~input_o\ & (\input0[3]~input_o\ $ (!\input1[3]~input_o\)))) # (!\input0[2]~input_o\ & (!\input1[2]~input_o\ & (\input0[3]~input_o\ $ (!\input1[3]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000001001000001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[2]~input_o\,
- datab => \input0[3]~input_o\,
- datac => \input1[3]~input_o\,
- datad => \input1[2]~input_o\,
- combout => \Equal0~1_combout\);
-
-\input0[4]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input0(4),
- o => \input0[4]~input_o\);
-
-\input0[5]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input0(5),
- o => \input0[5]~input_o\);
-
-\input1[5]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input1(5),
- o => \input1[5]~input_o\);
-
-\input1[4]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input1(4),
- o => \input1[4]~input_o\);
-
-\Equal0~2\ : cycloneive_lcell_comb
--- Equation(s):
--- \Equal0~2_combout\ = (\input0[4]~input_o\ & (\input1[4]~input_o\ & (\input0[5]~input_o\ $ (!\input1[5]~input_o\)))) # (!\input0[4]~input_o\ & (!\input1[4]~input_o\ & (\input0[5]~input_o\ $ (!\input1[5]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000001001000001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[4]~input_o\,
- datab => \input0[5]~input_o\,
- datac => \input1[5]~input_o\,
- datad => \input1[4]~input_o\,
- combout => \Equal0~2_combout\);
-
-\input0[6]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input0(6),
- o => \input0[6]~input_o\);
-
-\input0[7]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input0(7),
- o => \input0[7]~input_o\);
-
-\input1[7]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input1(7),
- o => \input1[7]~input_o\);
-
-\input1[6]~input\ : cycloneive_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_input1(6),
- o => \input1[6]~input_o\);
-
-\Equal0~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \Equal0~3_combout\ = (\input0[6]~input_o\ & (\input1[6]~input_o\ & (\input0[7]~input_o\ $ (!\input1[7]~input_o\)))) # (!\input0[6]~input_o\ & (!\input1[6]~input_o\ & (\input0[7]~input_o\ $ (!\input1[7]~input_o\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000001001000001",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[6]~input_o\,
- datab => \input0[7]~input_o\,
- datac => \input1[7]~input_o\,
- datad => \input1[6]~input_o\,
- combout => \Equal0~3_combout\);
-
-\Equal0~4\ : cycloneive_lcell_comb
--- Equation(s):
--- \Equal0~4_combout\ = (\Equal0~0_combout\ & (\Equal0~1_combout\ & (\Equal0~2_combout\ & \Equal0~3_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1000000000000000",
- sum_lutc_input => "datac")
--- pragma translate_on
-PORT MAP (
- dataa => \Equal0~0_combout\,
- datab => \Equal0~1_combout\,
- datac => \Equal0~2_combout\,
- datad => \Equal0~3_combout\,
- combout => \Equal0~4_combout\);
-
-\LessThan0~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan0~1_cout\ = CARRY((!\input0[0]~input_o\ & \input1[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000001000100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[0]~input_o\,
- datab => \input1[0]~input_o\,
- datad => VCC,
- cout => \LessThan0~1_cout\);
-
-\LessThan0~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan0~3_cout\ = CARRY((\input0[1]~input_o\ & ((!\LessThan0~1_cout\) # (!\input1[1]~input_o\))) # (!\input0[1]~input_o\ & (!\input1[1]~input_o\ & !\LessThan0~1_cout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000101011",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[1]~input_o\,
- datab => \input1[1]~input_o\,
- datad => VCC,
- cin => \LessThan0~1_cout\,
- cout => \LessThan0~3_cout\);
-
-\LessThan0~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan0~5_cout\ = CARRY((\input0[2]~input_o\ & (\input1[2]~input_o\ & !\LessThan0~3_cout\)) # (!\input0[2]~input_o\ & ((\input1[2]~input_o\) # (!\LessThan0~3_cout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000001001101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[2]~input_o\,
- datab => \input1[2]~input_o\,
- datad => VCC,
- cin => \LessThan0~3_cout\,
- cout => \LessThan0~5_cout\);
-
-\LessThan0~7\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan0~7_cout\ = CARRY((\input0[3]~input_o\ & ((!\LessThan0~5_cout\) # (!\input1[3]~input_o\))) # (!\input0[3]~input_o\ & (!\input1[3]~input_o\ & !\LessThan0~5_cout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000101011",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[3]~input_o\,
- datab => \input1[3]~input_o\,
- datad => VCC,
- cin => \LessThan0~5_cout\,
- cout => \LessThan0~7_cout\);
-
-\LessThan0~9\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan0~9_cout\ = CARRY((\input0[4]~input_o\ & (\input1[4]~input_o\ & !\LessThan0~7_cout\)) # (!\input0[4]~input_o\ & ((\input1[4]~input_o\) # (!\LessThan0~7_cout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000001001101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[4]~input_o\,
- datab => \input1[4]~input_o\,
- datad => VCC,
- cin => \LessThan0~7_cout\,
- cout => \LessThan0~9_cout\);
-
-\LessThan0~11\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan0~11_cout\ = CARRY((\input0[5]~input_o\ & ((!\LessThan0~9_cout\) # (!\input1[5]~input_o\))) # (!\input0[5]~input_o\ & (!\input1[5]~input_o\ & !\LessThan0~9_cout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000101011",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[5]~input_o\,
- datab => \input1[5]~input_o\,
- datad => VCC,
- cin => \LessThan0~9_cout\,
- cout => \LessThan0~11_cout\);
-
-\LessThan0~13\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan0~13_cout\ = CARRY((\input0[6]~input_o\ & (\input1[6]~input_o\ & !\LessThan0~11_cout\)) # (!\input0[6]~input_o\ & ((\input1[6]~input_o\) # (!\LessThan0~11_cout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000001001101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[6]~input_o\,
- datab => \input1[6]~input_o\,
- datad => VCC,
- cin => \LessThan0~11_cout\,
- cout => \LessThan0~13_cout\);
-
-\LessThan0~14\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan0~14_combout\ = (\input1[7]~input_o\ & (\input0[7]~input_o\ & \LessThan0~13_cout\)) # (!\input1[7]~input_o\ & ((\input0[7]~input_o\) # (\LessThan0~13_cout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1101010011010100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input1[7]~input_o\,
- datab => \input0[7]~input_o\,
- cin => \LessThan0~13_cout\,
- combout => \LessThan0~14_combout\);
-
-\LessThan1~1\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan1~1_cout\ = CARRY((!\input0[0]~input_o\ & \input1[0]~input_o\))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000001000100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[0]~input_o\,
- datab => \input1[0]~input_o\,
- datad => VCC,
- cout => \LessThan1~1_cout\);
-
-\LessThan1~3\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan1~3_cout\ = CARRY((\input0[1]~input_o\ & ((!\LessThan1~1_cout\) # (!\input1[1]~input_o\))) # (!\input0[1]~input_o\ & (!\input1[1]~input_o\ & !\LessThan1~1_cout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000101011",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[1]~input_o\,
- datab => \input1[1]~input_o\,
- datad => VCC,
- cin => \LessThan1~1_cout\,
- cout => \LessThan1~3_cout\);
-
-\LessThan1~5\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan1~5_cout\ = CARRY((\input0[2]~input_o\ & (\input1[2]~input_o\ & !\LessThan1~3_cout\)) # (!\input0[2]~input_o\ & ((\input1[2]~input_o\) # (!\LessThan1~3_cout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000001001101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[2]~input_o\,
- datab => \input1[2]~input_o\,
- datad => VCC,
- cin => \LessThan1~3_cout\,
- cout => \LessThan1~5_cout\);
-
-\LessThan1~7\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan1~7_cout\ = CARRY((\input0[3]~input_o\ & ((!\LessThan1~5_cout\) # (!\input1[3]~input_o\))) # (!\input0[3]~input_o\ & (!\input1[3]~input_o\ & !\LessThan1~5_cout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000101011",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[3]~input_o\,
- datab => \input1[3]~input_o\,
- datad => VCC,
- cin => \LessThan1~5_cout\,
- cout => \LessThan1~7_cout\);
-
-\LessThan1~9\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan1~9_cout\ = CARRY((\input0[4]~input_o\ & (\input1[4]~input_o\ & !\LessThan1~7_cout\)) # (!\input0[4]~input_o\ & ((\input1[4]~input_o\) # (!\LessThan1~7_cout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000001001101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[4]~input_o\,
- datab => \input1[4]~input_o\,
- datad => VCC,
- cin => \LessThan1~7_cout\,
- cout => \LessThan1~9_cout\);
-
-\LessThan1~11\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan1~11_cout\ = CARRY((\input0[5]~input_o\ & ((!\LessThan1~9_cout\) # (!\input1[5]~input_o\))) # (!\input0[5]~input_o\ & (!\input1[5]~input_o\ & !\LessThan1~9_cout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000000101011",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[5]~input_o\,
- datab => \input1[5]~input_o\,
- datad => VCC,
- cin => \LessThan1~9_cout\,
- cout => \LessThan1~11_cout\);
-
-\LessThan1~13\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan1~13_cout\ = CARRY((\input0[6]~input_o\ & (\input1[6]~input_o\ & !\LessThan1~11_cout\)) # (!\input0[6]~input_o\ & ((\input1[6]~input_o\) # (!\LessThan1~11_cout\))))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "0000000001001101",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[6]~input_o\,
- datab => \input1[6]~input_o\,
- datad => VCC,
- cin => \LessThan1~11_cout\,
- cout => \LessThan1~13_cout\);
-
-\LessThan1~14\ : cycloneive_lcell_comb
--- Equation(s):
--- \LessThan1~14_combout\ = (\input0[7]~input_o\ & (\input1[7]~input_o\ & \LessThan1~13_cout\)) # (!\input0[7]~input_o\ & ((\input1[7]~input_o\) # (\LessThan1~13_cout\)))
-
--- pragma translate_off
-GENERIC MAP (
- lut_mask => "1101010011010100",
- sum_lutc_input => "cin")
--- pragma translate_on
-PORT MAP (
- dataa => \input0[7]~input_o\,
- datab => \input1[7]~input_o\,
- cin => \LessThan1~13_cout\,
- combout => \LessThan1~14_combout\);
-
-ww_equal <= \equal~output_o\;
-
-ww_notEqual <= \notEqual~output_o\;
-
-ww_ltSigned <= \ltSigned~output_o\;
-
-ww_ltUnsigned <= \ltUnsigned~output_o\;
-END structure;
-
-
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo_modelsim.xrf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo_modelsim.xrf
deleted file mode 100644
index 8956b9e..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo_modelsim.xrf
+++ /dev/null
@@ -1,50 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
-source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cbx.xml
-design_name = CmpN
-instance = comp, \equal~output\, equal~output, CmpN, 1
-instance = comp, \notEqual~output\, notEqual~output, CmpN, 1
-instance = comp, \ltSigned~output\, ltSigned~output, CmpN, 1
-instance = comp, \ltUnsigned~output\, ltUnsigned~output, CmpN, 1
-instance = comp, \input0[0]~input\, input0[0]~input, CmpN, 1
-instance = comp, \input0[1]~input\, input0[1]~input, CmpN, 1
-instance = comp, \input1[1]~input\, input1[1]~input, CmpN, 1
-instance = comp, \input1[0]~input\, input1[0]~input, CmpN, 1
-instance = comp, \Equal0~0\, Equal0~0, CmpN, 1
-instance = comp, \input0[2]~input\, input0[2]~input, CmpN, 1
-instance = comp, \input0[3]~input\, input0[3]~input, CmpN, 1
-instance = comp, \input1[3]~input\, input1[3]~input, CmpN, 1
-instance = comp, \input1[2]~input\, input1[2]~input, CmpN, 1
-instance = comp, \Equal0~1\, Equal0~1, CmpN, 1
-instance = comp, \input0[4]~input\, input0[4]~input, CmpN, 1
-instance = comp, \input0[5]~input\, input0[5]~input, CmpN, 1
-instance = comp, \input1[5]~input\, input1[5]~input, CmpN, 1
-instance = comp, \input1[4]~input\, input1[4]~input, CmpN, 1
-instance = comp, \Equal0~2\, Equal0~2, CmpN, 1
-instance = comp, \input0[6]~input\, input0[6]~input, CmpN, 1
-instance = comp, \input0[7]~input\, input0[7]~input, CmpN, 1
-instance = comp, \input1[7]~input\, input1[7]~input, CmpN, 1
-instance = comp, \input1[6]~input\, input1[6]~input, CmpN, 1
-instance = comp, \Equal0~3\, Equal0~3, CmpN, 1
-instance = comp, \Equal0~4\, Equal0~4, CmpN, 1
-instance = comp, \LessThan0~1\, LessThan0~1, CmpN, 1
-instance = comp, \LessThan0~3\, LessThan0~3, CmpN, 1
-instance = comp, \LessThan0~5\, LessThan0~5, CmpN, 1
-instance = comp, \LessThan0~7\, LessThan0~7, CmpN, 1
-instance = comp, \LessThan0~9\, LessThan0~9, CmpN, 1
-instance = comp, \LessThan0~11\, LessThan0~11, CmpN, 1
-instance = comp, \LessThan0~13\, LessThan0~13, CmpN, 1
-instance = comp, \LessThan0~14\, LessThan0~14, CmpN, 1
-instance = comp, \LessThan1~1\, LessThan1~1, CmpN, 1
-instance = comp, \LessThan1~3\, LessThan1~3, CmpN, 1
-instance = comp, \LessThan1~5\, LessThan1~5, CmpN, 1
-instance = comp, \LessThan1~7\, LessThan1~7, CmpN, 1
-instance = comp, \LessThan1~9\, LessThan1~9, CmpN, 1
-instance = comp, \LessThan1~11\, LessThan1~11, CmpN, 1
-instance = comp, \LessThan1~13\, LessThan1~13, CmpN, 1
-instance = comp, \LessThan1~14\, LessThan1~14, CmpN, 1
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/transcript
deleted file mode 100644
index de392d6..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/transcript
+++ /dev/null
@@ -1,23 +0,0 @@
-# do CmpN_Demo.do
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 12:07:05 on Mar 17,2023
-# vcom -work work CmpN_Demo.vho
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package VITAL_Timing
-# -- Loading package VITAL_Primitives
-# -- Loading package cycloneive_atom_pack
-# -- Loading package cycloneive_components
-# -- Compiling entity CmpN
-# -- Compiling architecture structure of CmpN
-# End time: 12:07:05 on Mar 17,2023, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 0
-# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-# Start time: 12:07:05 on Mar 17,2023
-# vcom work Cmp8.vwf.vht
-# ** Error: (vcom-2054) File "work" is a directory.
-# End time: 12:07:05 on Mar 17,2023, Elapsed time: 0:00:00
-# Errors: 1, Warnings: 0
-# ** Error: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/vcom failed.
-# Executing ONERROR command at macro ./CmpN_Demo.do line 4
diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_info
deleted file mode 100644
index a0a242f..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_info
+++ /dev/null
@@ -1,60 +0,0 @@
-m255
-K4
-z2
-!s11e vcom 2020.1 2020.02, Feb 28 2020
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-Z0 d/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim
-Ecmpn
-Z1 w1679054824
-Z2 DPx4 ieee 16 vital_primitives 0 22 G>kiXP8Q9dRClKfK1Zn7j1
-Z3 DPx10 cycloneive 20 cycloneive_atom_pack 0 22 WOh:M[al;oVzG5c`D0
-Z4 DPx4 ieee 12 vital_timing 0 22 J>EBealN09f8GzldA[z2>3
-Z5 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
-Z6 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
-Z7 DPx10 cycloneive 21 cycloneive_components 0 22 zGMDhP>8e@2k@f0eTibM5a3
-!s100 DKWf7]9gNH:nYKbGKeG;^1
-R10
-32
-R11
-!i10b 1
-R12
-R13
-Z16 !s107 CmpN_Demo.vho|
-!i113 1
-R14
-R15
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diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_vmake b/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_vmake
deleted file mode 100644
index 37aa36a..0000000
--- a/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_vmake
+++ /dev/null
@@ -1,4 +0,0 @@
-m255
-K4
-z0
-cModel Technology